Some reworks to prepare for transition to makefile. Stack bugfixes.

diff --git a/7seg.v b/7seg.v
index 8e91b038669690cbb954c8f7178d602cda72eb30..c64e7d5ceb9af8a76d981ae140c27c364d39823c 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -6,7 +6,7 @@ module AddrMon(
        input freeze
        );
 
-       reg [10:0] clkdv;
+       reg [5:0] clkdv;
        reg [1:0] dcount;
        
        reg [15:0] latch = 0;
@@ -17,42 +17,40 @@ module AddrMon(
                (dcount == 2'b10) ? latch[11:8] :
                                     latch[15:12];
 
-       always @ (negedge clk)
-       begin
-               clkdv <= clkdv + 1;
-               if (~freeze)
-                       latch <= addr;
-       end
+       always @ (negedge clk) begin
+               if (clkdv == 31) begin
+                       clkdv <= 0;
+                       dcount <= dcount + 1;
 
-       always @ (posedge clkdv[10])
-       begin
-               dcount <= dcount + 1;
+                       case(dcount)
+                       2'b00: digit <= 4'b1110;
+                       2'b01: digit <= 4'b1101;
+                       2'b10: digit <= 4'b1011;
+                       2'b11: digit <= 4'b0111;
+                       endcase
 
-               case(dcount)
-               2'b00: digit <= 4'b1110;
-               2'b01: digit <= 4'b1101;
-               2'b10: digit <= 4'b1011;
-               2'b11: digit <= 4'b0111;
-               endcase
-
-               case(curval)
-                            /* ABCDEFGP */
-               4'h0: out <= ~8'b11111100;
-               4'h1: out <= ~8'b01100000;
-               4'h2: out <= ~8'b11011010;
-               4'h3: out <= ~8'b11110010;
-               4'h4: out <= ~8'b01100110;
-               4'h5: out <= ~8'b10110110;
-               4'h6: out <= ~8'b10111110;
-               4'h7: out <= ~8'b11100000;
-               4'h8: out <= ~8'b11111110;
-               4'h9: out <= ~8'b11110110;
-               4'hA: out <= ~8'b11101110;
-               4'hB: out <= ~8'b00111110;
-               4'hC: out <= ~8'b10011100;
-               4'hD: out <= ~8'b01111010;
-               4'hE: out <= ~8'b10011110;
-               4'hF: out <= ~8'b10001110;
-               endcase
+                       case(curval)
+                                                       /* ABCDEFGP */
+                       4'h0: out <= ~8'b11111100;
+                       4'h1: out <= ~8'b01100000;
+                       4'h2: out <= ~8'b11011010;
+                       4'h3: out <= ~8'b11110010;
+                       4'h4: out <= ~8'b01100110;
+                       4'h5: out <= ~8'b10110110;
+                       4'h6: out <= ~8'b10111110;
+                       4'h7: out <= ~8'b11100000;
+                       4'h8: out <= ~8'b11111110;
+                       4'h9: out <= ~8'b11110110;
+                       4'hA: out <= ~8'b11101110;
+                       4'hB: out <= ~8'b00111110;
+                       4'hC: out <= ~8'b10011100;
+                       4'hD: out <= ~8'b01111010;
+                       4'hE: out <= ~8'b10011110;
+                       4'hF: out <= ~8'b10001110;
+                       endcase
+               end else
+                       clkdv <= clkdv + 1;
+               if (~freeze)
+                       latch <= addr;
        end
 endmodule

diff --git a/FPGABoy.ise b/FPGABoy.ise
index 7ef4156167ad5f7bf685c02e058026229cb6c003..3ac09a13b9814b7d8a8692afeb126383ffb7b3e3 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 57c22d20e27188d7f633bb66a1f74189ca8ebfbd..ae6ff0076d3676591d162f1b6a1eb5b903b83087 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -95,8 +95,8 @@ module GBZ80Core(
        output reg buswr = 0, output reg busrd = 0,
        input irq, input [7:0] jaddr);
        
-       reg [1:0] state = 0;                                    /* State within this bus cycle (see STATE_*). */
-       reg [2:0] cycle = 0;                                    /* Cycle for instructions. */
+       reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
+       reg [2:0] cycle;                                        /* Cycle for instructions. */
        
        reg [7:0] registers[11:0];
        
@@ -105,7 +105,7 @@ module GBZ80Core(
        reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
        
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
-       reg rd = 1, wr = 0, newcycle = 1;
+       reg rd, wr, newcycle;
        
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
@@ -127,7 +127,6 @@ module GBZ80Core(
                registers[ 9] <= 0;
                registers[10] <= 0;
                registers[11] <= 0;
-               ie <= 0;
                rd <= 1;
                wr <= 0;
                newcycle <= 1;
@@ -136,7 +135,11 @@ module GBZ80Core(
                busrd <= 0;
                buswr <= 0;
                busaddress <= 0;
+               ie <= 0;
                iedelay <= 0;
+               opcode <= 0;
+               state <= `STATE_WRITEBACK;
+               cycle <= 0;
        end
 
        always @(posedge clk)
@@ -302,7 +305,7 @@ module GBZ80Core(
                                        end
                                1:      begin
                                                wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
                                                case (opcode[5:4])
                                                `INSN_stack_AF: wdata <= registers[`REG_F];
                                                `INSN_stack_BC: wdata <= registers[`REG_C];
@@ -325,7 +328,7 @@ module GBZ80Core(
                                        end
                                1:      begin
                                                rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end
                                2:      begin
                                                `EXEC_NEWCYCLE;
@@ -677,18 +680,16 @@ module GBZ80Core(
                        end
                        `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
                                case (cycle)
-                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                               1:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                               0:      begin /* type F */ end
+                               1:      begin /* type F */ end
                                2:      begin /* type F */ end
-                               3:      begin /* type F */ end
+                               3:      {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                               {registers[`REG_SPH],registers[`REG_SPL]} - 2;
                                endcase
                        end
                        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                                case (cycle)
-                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                               0:      begin end
                                1:      begin
                                                case (opcode[5:4])
                                                `INSN_stack_AF: registers[`REG_F] <= rdata;
@@ -696,8 +697,6 @@ module GBZ80Core(
                                                `INSN_stack_DE: registers[`REG_E] <= rdata;
                                                `INSN_stack_HL: registers[`REG_L] <= rdata;
                                                endcase
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end
                                2:      begin
                                                case (opcode[5:4])
@@ -706,6 +705,8 @@ module GBZ80Core(
                                                `INSN_stack_DE: registers[`REG_D] <= rdata;
                                                `INSN_stack_HL: registers[`REG_H] <= rdata;
                                                endcase
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
                                        end
                                endcase
                        end
@@ -939,12 +940,13 @@ module GBZ80Core(
                        `INSN_VOP_INTR: begin
                                case (cycle)
                                0:      begin end
-                               1:      {registers[`REG_SPH],registers[`REG_SPL]}
-                                               <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+                               1:      begin end
                                2:      begin
                                                ie <= 0;
                                                {registers[`REG_PCH],registers[`REG_PCL]} <=
                                                        {8'b0,jaddr};
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 2;
                                        end
                                endcase
                        end

diff --git a/Makefile b/Makefile
index bf5d69890e7fc7ec8ccbc160e5e425951baf0938..d89b58697d6c3578e8a509baf3f4d9cd9c2b4d70 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,24 @@
-all: CoreTop.svf
+VLOGS=Uart.v Timer.v Interrupt.v GBZ80Core.v CPUDCM.v 7seg.v System.v
+
+all: CoreTop.svf CoreTop.twr
+
+CoreTyp.ngc: CoreTop.xst CoreTop.prj $(VLOGS) CoreTop.ucf
+       xst -ifn CoreTop.xst -ofn CoreTop.syr
+
+CoreTop.ngd: CoreTop.ngc foo.bmm
+       ngdbuild -dd _ngo  -nt timestamp -i -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
+
+CoreTop_map.ncd: CoreTop.ngd
+       map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
+
+CoreTop.ncd: CoreTop_map.ncd
+       par -w -ol std -t 1 CoreTop_map.ncd CoreTop.ncd CoreTop.pcf
+
+CoreTop.twr: CoreTop_map.ncd
+       trce -e 3 -s 5 -xml CoreTop CoreTop.ncd -o CoreTop.twr CoreTop.pcf -ucf CoreTop.ucf
+
+CoreTop.bit: CoreTop.ut CoreTop.ncd
+       bitgen -f CoreTop.ut CoreTop.ncd
 
 CoreTop_rom.bit: rom.hex CoreTop.bit foo_bd.bmm
        data2mem -bm foo_bd.bmm -bd rom.mem -bt CoreTop.bit -o b CoreTop_rom.bit

diff --git a/System.v b/System.v
index 7319ebf6aceb8cc2f7b7f72a3f0877bb93a39aaa..5d4fbedf2acadf14bd48a28dfb153570ed63a1cf 100644 (file)
--- a/System.v
+++ b/System.v
@@ -46,7 +46,7 @@ module Switches(
        input clk,
        input wr, rd,
        input [7:0] switches,
-       output reg [7:0] ledout);
+       output reg [7:0] ledout = 0);
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
@@ -162,8 +162,8 @@ module TestBench();
        wire irq, tmrirq;
        wire [7:0] jaddr;
        
-//     wire [7:0] leds;
-//     wire [7:0] switches;
+       wire [7:0] leds;
+       wire [7:0] switches;
        
        always #10 clk <= ~clk;
        GBZ80Core core(
@@ -220,12 +220,12 @@ module TestBench();
                .master(irq),
                .jaddr(jaddr));
        
-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
+       Switches sw(
+               .clk(clk),
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd),
+               .switches(switches),
+               .ledout(leds));
 endmodule

diff --git a/rom.asm b/rom.asm
index 437f01e5c5e036687992cf8a7ea646588eb7695d..512cfcedf6c6bb4f7ebb6dbea41ae8b88cd7aa54 100644 (file)
--- a/rom.asm
+++ b/rom.asm
@@ -5,14 +5,22 @@ main:
        ld a, $FF
        ld [c],a
        
-       ld sp, $DFFF
+       ld sp, $DFF0
+       
+       ld hl, $DF81
+       ld a, $80
+       ld [hl], a
+
+;      ld c, $07
+;      ld a, $04       ;start timer, 4.096KHz
+;      ld [c], a
+diqs:; ei
+       jr diqs
 
        ld hl, signon
        call puts
 
-       ld c, $07
-       ld a, $04       ;start timer, 4.096KHz
-       ld [c], a
+       
        ei
        
        call memtest
@@ -24,17 +32,37 @@ main:
 
        jr main
 
-       section "fuq",HOME[$100]
+       section "fuq",HOME[$50]
 irqhand:
        PUSH AF
        PUSH BC
        PUSH DE
        PUSH HL
+       
+;      ld c, $51
+;      ld a, $F0
+;      ld [c], a
+       
        xor a
        ld c, $0F       ; ack the irq
        ld [c], a
-       ld a, $41       ; print A
-       call putc
+       
+       ;ld a, $41      ; print A
+       ;call putc
+       
+       ld hl, $DF81
+       ld a, [hl]
+;      ld b, 1
+;      add b
+       ld c, $51
+;      ld [c], a
+;      ld [hl], a
+
+
+;      ld c, $51
+;      ld a, $0F
+;      ld [c], a
+       
        POP HL
        POP DE
        POP BC
@@ -49,7 +77,7 @@ memtest:
        ld hl,memteststr
        call puts
        
-       ld hl, $C000            ; Write loop
+       ld hl, $C001            ; Write loop
 .wr:
        ld a,h
        xor l
@@ -61,7 +89,7 @@ memtest:
        cp l
        jr nz, .wr
 
-       ld hl, $C000            ; Read loop
+       ld hl, $C001            ; Read loop
 .rd:
        ld a,h
        xor l
@@ -135,6 +163,7 @@ waitsw:
 .loop1:
        ld a,[c]
        cp b
+       ei
        jr z,.loop1
 .loop2:
        ld a,[c]
@@ -269,8 +298,6 @@ puts:
        ld a, [hli]
        ld b, $00
        cp b
-       jr z, .done
+       ret z
        call putc
        jr puts
-.done:
-       ret