Some reworks to prepare for transition to makefile. Stack bugfixes.
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg [7:0] rom [2047:0];
10         initial $readmemh("rom.hex", rom);
11
12         wire decode = address[15:13] == 0;
13         wire [7:0] odata = rom[address[11:0]];
14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15         //assign data = rd ? odata : 8'bzzzzzzzz;
16 endmodule
17
18 module InternalRAM(
19         input [15:0] address,
20         inout [7:0] data,
21         input clk,
22         input wr, rd);
23         
24         // synthesis attribute ram_style of reg is block
25         reg [7:0] ram [8191:0];
26         
27         wire decode = address[15:13] == 3'b110;
28         reg [7:0] odata;
29         wire idata = data;
30         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
31         
32         always @(negedge clk)
33         begin
34                 if (decode)     // This has to go this way. The only way XST knows how to do
35                 begin                           // block ram is chip select, write enable, and always
36                         if (wr)         // reading. "else if rd" does not cut it ...
37                                 ram[address[12:0]] <= data;
38                         odata <= ram[address[12:0]];
39                 end
40         end
41 endmodule
42
43 module Switches(
44         input [15:0] address,
45         inout [7:0] data,
46         input clk,
47         input wr, rd,
48         input [7:0] switches,
49         output reg [7:0] ledout = 0);
50         
51         wire decode = address == 16'hFF51;
52         reg [7:0] odata;
53         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
54         
55         always @(negedge clk)
56         begin
57                 if (decode && rd)
58                         odata <= switches;
59                 else if (decode && wr)
60                         ledout <= data;
61         end
62 endmodule
63
64 module CoreTop(
65         input xtal,
66         input [7:0] switches,
67         input [3:0] buttons,
68         output wire [7:0] leds,
69         output serio,
70         output wire [3:0] digits,
71         output wire [7:0] seven);
72         
73         wire clk;       
74         CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
75
76         wire [15:0] addr;       
77         wire [7:0] data;
78         wire wr, rd;
79         
80         wire irq, tmrirq;
81         wire [7:0] jaddr;
82
83         GBZ80Core core(
84                 .clk(clk),
85                 .busaddress(addr),
86                 .busdata(data),
87                 .buswr(wr),
88                 .busrd(rd),
89                 .irq(irq),
90                 .jaddr(jaddr));
91         
92         ROM rom(
93                 .address(addr),
94                 .data(data),
95                 .clk(clk),
96                 .wr(wr),
97                 .rd(rd));
98         
99         AddrMon amon(
100     .addr(addr), 
101     .clk(clk), 
102     .digit(digits), 
103     .out(seven),
104          .freeze(buttons[0])
105     );
106          
107         Switches sw(
108                 .address(addr),
109                 .data(data),
110                 .clk(clk),
111                 .wr(wr),
112                 .rd(rd),
113                 .ledout(leds),
114                 .switches(switches)
115                 );
116
117         UART nouart (   /* no u */
118     .clk(clk), 
119     .wr(wr), 
120     .rd(rd), 
121     .addr(addr), 
122     .data(data), 
123     .serial(serio)
124     );
125
126   InternalRAM ram(
127                 .address(addr),
128                 .data(data),
129                 .clk(clk),
130                 .wr(wr),
131                 .rd(rd));
132
133         Timer tmr(
134                 .clk(clk),
135                 .wr(wr),
136                 .rd(rd),
137                 .addr(addr),
138                 .data(data),
139                 .irq(tmrirq));
140         
141         Interrupt intr(
142                 .clk(clk),
143                 .rd(rd),
144                 .wr(wr),
145                 .addr(addr),
146                 .data(data),
147                 .vblank(0),
148                 .lcdc(0),
149                 .tovf(tmrirq),
150                 .serial(0),
151                 .buttons(0),
152                 .master(irq),
153                 .jaddr(jaddr));
154 endmodule
155
156 module TestBench();
157         reg clk = 1;
158         wire [15:0] addr;
159         wire [7:0] data;
160         wire wr, rd;
161         
162         wire irq, tmrirq;
163         wire [7:0] jaddr;
164         
165         wire [7:0] leds;
166         wire [7:0] switches;
167         
168         always #10 clk <= ~clk;
169         GBZ80Core core(
170                 .clk(clk),
171                 .busaddress(addr),
172                 .busdata(data),
173                 .buswr(wr),
174                 .busrd(rd),
175                 .irq(irq),
176                 .jaddr(jaddr));
177         
178         ROM rom(
179                 .clk(clk),
180                 .address(addr),
181                 .data(data),
182                 .wr(wr),
183                 .rd(rd));
184         
185         InternalRAM ram(
186                 .address(addr),
187                 .data(data),
188                 .clk(clk),
189                 .wr(wr),
190                 .rd(rd));
191
192         wire serio;
193         UART uart(
194                 .addr(addr),
195                 .data(data),
196                 .clk(clk),
197                 .wr(wr),
198                 .rd(rd),
199                 .serial(serio));
200         
201         Timer tmr(
202                 .clk(clk),
203                 .wr(wr),
204                 .rd(rd),
205                 .addr(addr),
206                 .data(data),
207                 .irq(tmrirq));
208         
209         Interrupt intr(
210                 .clk(clk),
211                 .rd(rd),
212                 .wr(wr),
213                 .addr(addr),
214                 .data(data),
215                 .vblank(0),
216                 .lcdc(0),
217                 .tovf(tmrirq),
218                 .serial(0),
219                 .buttons(0),
220                 .master(irq),
221                 .jaddr(jaddr));
222         
223         Switches sw(
224                 .clk(clk),
225                 .address(addr),
226                 .data(data),
227                 .wr(wr),
228                 .rd(rd),
229                 .switches(switches),
230                 .ledout(leds));
231 endmodule
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