System.v

   1
   2 `timescale 1ns / 1ps
   3 module ROM(
   4         input [15:0] address,
   5         inout [7:0] data,
   6         input clk,
   7         input wr, rd);
   8
   9         reg [7:0] rom [2047:0];
  10         initial $readmemh("rom.hex", rom);
  11
  12         wire decode = address[15:13] == 0;
  13         wire [7:0] odata = rom[address[11:0]];
  14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  15         //assign data = rd ? odata : 8'bzzzzzzzz;
  16 endmodule
  17
  18 module InternalRAM(
  19         input [15:0] address,
  20         inout [7:0] data,
  21         input clk,
  22         input wr, rd);
  23
  24         // synthesis attribute ram_style of reg is block
  25         reg [7:0] ram [8191:0];
  26
  27         wire decode = address[15:13] == 3'b110;
  28         reg [7:0] odata;
  29         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  30
  31         always @(negedge clk)
  32         begin
  33                 if (decode)     // This has to go this way. The only way XST knows how to do
  34                 begin                           // block ram is chip select, write enable, and always
  35                         if (wr)         // reading. "else if rd" does not cut it ...
  36                                 ram[address[12:0]] <= data;
  37                         odata <= ram[address[12:0]];
  38                 end
  39         end
  40 endmodule
  41
  42 module Switches(
  43         input [15:0] address,
  44         inout [7:0] data,
  45         input clk,
  46         input wr, rd,
  47         input [7:0] switches,
  48         output reg [7:0] ledout = 0);
  49
  50         wire decode = address == 16'hFF51;
  51         reg [7:0] odata;
  52         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
  53
  54         always @(negedge clk)
  55         begin
  56                 if (decode && rd)
  57                         odata <= switches;
  58                 else if (decode && wr)
  59                         ledout <= data;
  60         end
  61 endmodule
  62
  63 module CoreTop(
  64         input xtal,
  65         input [7:0] switches,
  66         input [3:0] buttons,
  67         output wire [7:0] leds,
  68         output serio,
  69         output wire [3:0] digits,
  70         output wire [7:0] seven);
  71
  72         wire clk;
  73         CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
  74
  75         wire cclk;
  76         IBUFG ibuf (.O(cclk), .I(switches[0]));
  77
  78         wire [15:0] addr;
  79         wire [7:0] data;
  80         wire wr, rd;
  81
  82         wire irq, tmrirq;
  83         wire [7:0] jaddr;
  84         wire [1:0] state;
  85
  86         GBZ80Core core(
  87                 .clk(cclk),
  88                 .busaddress(addr),
  89                 .busdata(data),
  90                 .buswr(wr),
  91                 .busrd(rd),
  92                 .irq(irq),
  93                 .jaddr(jaddr),
  94                 .state(state));
  95
  96         ROM rom(
  97                 .address(addr),
  98                 .data(data),
  99                 .clk(clk),
 100                 .wr(wr),
 101                 .rd(rd));
 102
 103         AddrMon amon(
 104                 .addr(addr),
 105                 .clk(clk),
 106                 .digit(digits),
 107                 .out(seven),
 108                 .freeze(buttons[0]),
 109                 .periods(
 110                         (state == 2'b00) ? 4'b1000 :
 111                         (state == 2'b01) ? 4'b0100 :
 112                         (state == 2'b10) ? 4'b0010 :
 113                                            4'b0001) );
 114
 115         Switches sw(
 116                 .address(addr),
 117                 .data(data),
 118                 .clk(clk),
 119                 .wr(wr),
 120                 .rd(rd),
 121                 .ledout(leds),
 122                 .switches({switches[7:1],1'b0})
 123                 );
 124
 125         UART nouart (   /* no u */
 126                 .clk(clk),
 127                 .wr(wr),
 128                 .rd(rd),
 129                 .addr(addr),
 130                 .data(data),
 131                 .serial(serio)
 132                 );
 133
 134         InternalRAM ram(
 135                 .address(addr),
 136                 .data(data),
 137                 .clk(clk),
 138                 .wr(wr),
 139                 .rd(rd)
 140                 );
 141
 142         Timer tmr(
 143                 .clk(clk),
 144                 .wr(wr),
 145                 .rd(rd),
 146                 .addr(addr),
 147                 .data(data),
 148                 .irq(tmrirq)
 149                 );
 150
 151         Interrupt intr(
 152                 .clk(clk),
 153                 .rd(rd),
 154                 .wr(wr),
 155                 .addr(addr),
 156                 .data(data),
 157                 .vblank(0),
 158                 .lcdc(0),
 159                 .tovf(tmrirq),
 160                 .serial(0),
 161                 .buttons(0),
 162                 .master(irq),
 163                 .jaddr(jaddr));
 164 endmodule
 165
 166 module TestBench();
 167         reg clk = 1;
 168         wire [15:0] addr;
 169         wire [7:0] data;
 170         wire wr, rd;
 171
 172         wire irq, tmrirq;
 173         wire [7:0] jaddr;
 174
 175         wire [7:0] leds;
 176         wire [7:0] switches;
 177
 178         always #10 clk <= ~clk;
 179         GBZ80Core core(
 180                 .clk(clk),
 181                 .busaddress(addr),
 182                 .busdata(data),
 183                 .buswr(wr),
 184                 .busrd(rd),
 185                 .irq(irq),
 186                 .jaddr(jaddr));
 187
 188         ROM rom(
 189                 .clk(clk),
 190                 .address(addr),
 191                 .data(data),
 192                 .wr(wr),
 193                 .rd(rd));
 194
 195         InternalRAM ram(
 196                 .address(addr),
 197                 .data(data),
 198                 .clk(clk),
 199                 .wr(wr),
 200                 .rd(rd));
 201
 202         wire serio;
 203         UART uart(
 204                 .addr(addr),
 205                 .data(data),
 206                 .clk(clk),
 207                 .wr(wr),
 208                 .rd(rd),
 209                 .serial(serio));
 210
 211         Timer tmr(
 212                 .clk(clk),
 213                 .wr(wr),
 214                 .rd(rd),
 215                 .addr(addr),
 216                 .data(data),
 217                 .irq(tmrirq));
 218
 219         Interrupt intr(
 220                 .clk(clk),
 221                 .rd(rd),
 222                 .wr(wr),
 223                 .addr(addr),
 224                 .data(data),
 225                 .vblank(0),
 226                 .lcdc(0),
 227                 .tovf(tmrirq),
 228                 .serial(0),
 229                 .buttons(0),
 230                 .master(irq),
 231                 .jaddr(jaddr));
 232
 233         Switches sw(
 234                 .clk(clk),
 235                 .address(addr),
 236                 .data(data),
 237                 .wr(wr),
 238                 .rd(rd),
 239                 .switches(switches),
 240                 .ledout(leds));
 241 endmodule