Add bootrom
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg [7:0] rom [1023:0];
10         initial $readmemh("rom.hex", rom);
11
12         wire decode = address[15:13] == 0;
13         wire [7:0] odata = rom[address[10:0]];
14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15         //assign data = rd ? odata : 8'bzzzzzzzz;
16 endmodule
17
18 module MiniRAM(                 /* XXX will need to go INSIDE the CPU for when we do DMA */
19         input [15:0] address,
20         inout [7:0] data,
21         input clk,
22         input wr, rd);
23         
24         reg [7:0] ram [127:0];
25         
26         wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
27         reg [7:0] odata;
28         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
29         
30         always @(negedge clk)
31         begin
32                 if (decode)     // This has to go this way. The only way XST knows how to do
33                 begin                           // block ram is chip select, write enable, and always
34                         if (wr)         // reading. "else if rd" does not cut it ...
35                                 ram[address[6:0]] <= data;
36                         odata <= ram[address[6:0]];
37                 end
38         end
39
40 module InternalRAM(
41         input [15:0] address,
42         inout [7:0] data,
43         input clk,
44         input wr, rd);
45         
46         // synthesis attribute ram_style of ram is block
47         reg [7:0] ram [8191:0];
48         
49         wire decode = address[15:13] == 3'b110;
50         reg [7:0] odata;
51         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
52         
53         always @(negedge clk)
54         begin
55                 if (decode)     // This has to go this way. The only way XST knows how to do
56                 begin                           // block ram is chip select, write enable, and always
57                         if (wr)         // reading. "else if rd" does not cut it ...
58                                 ram[address[12:0]] <= data;
59                         odata <= ram[address[12:0]];
60                 end
61         end
62 endmodule
63
64 module Switches(
65         input [15:0] address,
66         inout [7:0] data,
67         input clk,
68         input wr, rd,
69         input [7:0] switches,
70         output reg [7:0] ledout = 0);
71         
72         wire decode = address == 16'hFF51;
73         reg [7:0] odata;
74         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
75         
76         always @(negedge clk)
77         begin
78                 if (decode && rd)
79                         odata <= switches;
80                 else if (decode && wr)
81                         ledout <= data;
82         end
83 endmodule
84
85 module CoreTop(
86         input xtal,
87         input [7:0] switches,
88         input [3:0] buttons,
89         output wire [7:0] leds,
90         output serio,
91         output wire [3:0] digits,
92         output wire [7:0] seven,
93         output wire hs, vs,
94         output wire [2:0] r, g,
95         output wire [1:0] b);
96         
97         wire xtalb, clk, vgaclk;
98         IBUFG iclkbuf(.O(xtalb), .I(xtal));
99         CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
100         pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
101         
102         wire [15:0] addr;       
103         wire [7:0] data;
104         wire wr, rd;
105         
106         wire irq, tmrirq, lcdcirq, vblankirq;
107         wire [7:0] jaddr;
108         wire [1:0] state;
109         
110         GBZ80Core core(
111                 .clk(clk),
112                 .busaddress(addr),
113                 .busdata(data),
114                 .buswr(wr),
115                 .busrd(rd),
116                 .irq(irq),
117                 .jaddr(jaddr),
118                 .state(state));
119         
120         ROM rom(
121                 .address(addr),
122                 .data(data),
123                 .clk(clk),
124                 .wr(wr),
125                 .rd(rd));
126         
127         wire lcdhs, lcdvs, lcdclk;
128         wire [2:0] lcdr, lcdg;
129         wire [1:0] lcdb;
130         
131         LCDC lcdc(
132                 .addr(addr),
133                 .data(data),
134                 .clk(clk),
135                 .wr(wr),
136                 .rd(rd),
137                 .lcdcirq(lcdcirq),
138                 .vblankirq(vblankirq),
139                 .lcdclk(lcdclk),
140                 .lcdhs(lcdhs),
141                 .lcdvs(lcdvs),
142                 .lcdr(lcdr),
143                 .lcdg(lcdg),
144                 .lcdb(lcdb));
145         
146         Framebuffer fb(
147                 .lcdclk(lcdclk),
148                 .lcdhs(lcdhs),
149                 .lcdvs(lcdvs),
150                 .lcdr(lcdr),
151                 .lcdg(lcdg),
152                 .lcdb(lcdb),
153                 .vgaclk(vgaclk),
154                 .vgahs(hs),
155                 .vgavs(vs),
156                 .vgar(r),
157                 .vgag(g),
158                 .vgab(b));
159         
160         AddrMon amon(
161                 .addr(addr), 
162                 .clk(clk), 
163                 .digit(digits), 
164                 .out(seven),
165                 .freeze(buttons[0]),
166                 .periods(
167                         (state == 2'b00) ? 4'b0010 :
168                         (state == 2'b01) ? 4'b0001 :
169                         (state == 2'b10) ? 4'b1000 :
170                                            4'b0100) );
171          
172         Switches sw(
173                 .address(addr),
174                 .data(data),
175                 .clk(clk),
176                 .wr(wr),
177                 .rd(rd),
178                 .ledout(leds),
179                 .switches(switches)
180                 );
181
182         UART nouart (   /* no u */
183                 .clk(clk), 
184                 .wr(wr), 
185                 .rd(rd), 
186                 .addr(addr), 
187                 .data(data), 
188                 .serial(serio)
189                 );
190
191         InternalRAM ram(
192                 .address(addr),
193                 .data(data),
194                 .clk(clk),
195                 .wr(wr),
196                 .rd(rd)
197                 );
198         
199         MiniRAM mram(
200                 .address(addr),
201                 .data(data),
202                 .clk(clk),
203                 .wr(wr),
204                 .rd(rd)
205                 );
206
207         Timer tmr(
208                 .clk(clk),
209                 .wr(wr),
210                 .rd(rd),
211                 .addr(addr),
212                 .data(data),
213                 .irq(tmrirq)
214                 );
215         
216         Interrupt intr(
217                 .clk(clk),
218                 .rd(rd),
219                 .wr(wr),
220                 .addr(addr),
221                 .data(data),
222                 .vblank(vblankirq),
223                 .lcdc(lcdcirq),
224                 .tovf(tmrirq),
225                 .serial(0),
226                 .buttons(0),
227                 .master(irq),
228                 .jaddr(jaddr));
229 endmodule
230
231 module TestBench();
232         reg clk = 1;
233         wire [15:0] addr;
234         wire [7:0] data;
235         wire wr, rd;
236         
237         wire irq, tmrirq;
238         wire [7:0] jaddr;
239         
240         wire [7:0] leds;
241         wire [7:0] switches;
242         
243         always #62 clk <= ~clk;
244         GBZ80Core core(
245                 .clk(clk),
246                 .busaddress(addr),
247                 .busdata(data),
248                 .buswr(wr),
249                 .busrd(rd),
250                 .irq(irq),
251                 .jaddr(jaddr));
252         
253         ROM rom(
254                 .clk(clk),
255                 .address(addr),
256                 .data(data),
257                 .wr(wr),
258                 .rd(rd));
259         
260         InternalRAM ram(
261                 .address(addr),
262                 .data(data),
263                 .clk(clk),
264                 .wr(wr),
265                 .rd(rd));
266
267         wire serio;
268         UART uart(
269                 .addr(addr),
270                 .data(data),
271                 .clk(clk),
272                 .wr(wr),
273                 .rd(rd),
274                 .serial(serio));
275         
276         Timer tmr(
277                 .clk(clk),
278                 .wr(wr),
279                 .rd(rd),
280                 .addr(addr),
281                 .data(data),
282                 .irq(tmrirq));
283         
284         Interrupt intr(
285                 .clk(clk),
286                 .rd(rd),
287                 .wr(wr),
288                 .addr(addr),
289                 .data(data),
290                 .vblank(0),
291                 .lcdc(0),
292                 .tovf(tmrirq),
293                 .serial(0),
294                 .buttons(0),
295                 .master(irq),
296                 .jaddr(jaddr));
297         
298         Switches sw(
299                 .clk(clk),
300                 .address(addr),
301                 .data(data),
302                 .wr(wr),
303                 .rd(rd),
304                 .switches(switches),
305                 .ledout(leds));
306 endmodule
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