It works, but why?
[fpgaboy.git] / System.v
1
2 `timescale 1ns / 1ps
3 module ROM(
4         input [15:0] address,
5         inout [7:0] data,
6         input clk,
7         input wr, rd);
8
9         reg [7:0] rom [2047:0];
10         initial $readmemh("rom.hex", rom);
11
12         wire decode = address[15:13] == 0;
13         wire [7:0] odata = rom[address[11:0]];
14         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15         //assign data = rd ? odata : 8'bzzzzzzzz;
16 endmodule
17
18 module InternalRAM(
19         input [15:0] address,
20         inout [7:0] data,
21         input clk,
22         input wr, rd);
23         
24         // synthesis attribute ram_style of reg is block
25         reg [7:0] ram [8191:0];
26         
27         wire decode = address[15:13] == 3'b110;
28         reg [7:0] odata;
29         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
30         
31         always @(negedge clk)
32         begin
33                 if (decode)     // This has to go this way. The only way XST knows how to do
34                 begin                           // block ram is chip select, write enable, and always
35                         if (wr)         // reading. "else if rd" does not cut it ...
36                                 ram[address[12:0]] <= data;
37                         odata <= ram[address[12:0]];
38                 end
39         end
40 endmodule
41
42 module Switches(
43         input [15:0] address,
44         inout [7:0] data,
45         input clk,
46         input wr, rd,
47         input [7:0] switches,
48         output reg [7:0] ledout = 0);
49         
50         wire decode = address == 16'hFF51;
51         reg [7:0] odata;
52         assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
53         
54         always @(negedge clk)
55         begin
56                 if (decode && rd)
57                         odata <= switches;
58                 else if (decode && wr)
59                         ledout <= data;
60         end
61 endmodule
62
63 module CoreTop(
64         input xtal,
65         input [7:0] switches,
66         input [3:0] buttons,
67         output wire [7:0] leds,
68         output serio,
69         output wire [3:0] digits,
70         output wire [7:0] seven);
71         
72         wire clk;       
73         CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
74         
75         wire cclk;
76 //      IBUFG ibuf (.O(cclk), .I(switches[0] & clk));
77         assign cclk = clk;
78
79         wire [15:0] addr;       
80         wire [7:0] data;
81         wire wr, rd;
82         
83         wire irq, tmrirq;
84         wire [7:0] jaddr;
85         wire [1:0] state;
86         
87         GBZ80Core core(
88                 .clk(clk),
89                 .busaddress(addr),
90                 .busdata(data),
91                 .buswr(wr),
92                 .busrd(rd),
93                 .irq(irq),
94                 .jaddr(jaddr),
95                 .state(state));
96         
97         ROM rom(
98                 .address(addr),
99                 .data(data),
100                 .clk(clk),
101                 .wr(wr),
102                 .rd(rd));
103         
104         AddrMon amon(
105                 .addr(addr), 
106                 .clk(clk), 
107                 .digit(digits), 
108                 .out(seven),
109                 .freeze(buttons[0]),
110                 .periods(
111                         (state == 2'b00) ? 4'b0010 :
112                         (state == 2'b01) ? 4'b0001 :
113                         (state == 2'b10) ? 4'b1000 :
114                                            4'b0100) );
115          
116         Switches sw(
117                 .address(addr),
118                 .data(data),
119                 .clk(clk),
120                 .wr(wr),
121                 .rd(rd),
122                 .ledout(leds),
123                 .switches({switches[7:1],1'b0})
124                 );
125
126         UART nouart (   /* no u */
127                 .clk(clk), 
128                 .wr(wr), 
129                 .rd(rd), 
130                 .addr(addr), 
131                 .data(data), 
132                 .serial(serio)
133                 );
134
135         InternalRAM ram(
136                 .address(addr),
137                 .data(data),
138                 .clk(clk),
139                 .wr(wr),
140                 .rd(rd)
141                 );
142
143         Timer tmr(
144                 .clk(clk),
145                 .wr(wr),
146                 .rd(rd),
147                 .addr(addr),
148                 .data(data),
149                 .irq(tmrirq)
150                 );
151         
152         Interrupt intr(
153                 .clk(clk),
154                 .rd(rd),
155                 .wr(wr),
156                 .addr(addr),
157                 .data(data),
158                 .vblank(0),
159                 .lcdc(0),
160                 .tovf(tmrirq),
161                 .serial(0),
162                 .buttons(0),
163                 .master(irq),
164                 .jaddr(jaddr));
165 endmodule
166
167 module TestBench();
168         reg clk = 1;
169         wire [15:0] addr;
170         wire [7:0] data;
171         wire wr, rd;
172         
173         wire irq, tmrirq;
174         wire [7:0] jaddr;
175         
176         wire [7:0] leds;
177         wire [7:0] switches;
178         
179         always #62 clk <= ~clk;
180         GBZ80Core core(
181                 .clk(clk),
182                 .busaddress(addr),
183                 .busdata(data),
184                 .buswr(wr),
185                 .busrd(rd),
186                 .irq(irq),
187                 .jaddr(jaddr));
188         
189         ROM rom(
190                 .clk(clk),
191                 .address(addr),
192                 .data(data),
193                 .wr(wr),
194                 .rd(rd));
195         
196         InternalRAM ram(
197                 .address(addr),
198                 .data(data),
199                 .clk(clk),
200                 .wr(wr),
201                 .rd(rd));
202
203         wire serio;
204         UART uart(
205                 .addr(addr),
206                 .data(data),
207                 .clk(clk),
208                 .wr(wr),
209                 .rd(rd),
210                 .serial(serio));
211         
212         Timer tmr(
213                 .clk(clk),
214                 .wr(wr),
215                 .rd(rd),
216                 .addr(addr),
217                 .data(data),
218                 .irq(tmrirq));
219         
220         Interrupt intr(
221                 .clk(clk),
222                 .rd(rd),
223                 .wr(wr),
224                 .addr(addr),
225                 .data(data),
226                 .vblank(0),
227                 .lcdc(0),
228                 .tovf(tmrirq),
229                 .serial(0),
230                 .buttons(0),
231                 .master(irq),
232                 .jaddr(jaddr));
233         
234         Switches sw(
235                 .clk(clk),
236                 .address(addr),
237                 .data(data),
238                 .wr(wr),
239                 .rd(rd),
240                 .switches(switches),
241                 .ledout(leds));
242 endmodule
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