ICache, Fetch: Re-pipe things such that the icache now has a one-cycle latency. ...
[firearm.git] / Decode.v
CommitLineData
26049339
CL
1`include "ARM_Constants.v"
2
bae77231
CL
3module Decode(
4 input clk,
e74c7936 5 input stall,
be64a9df 6 input [31:0] insn,
bae77231 7 input [31:0] inpc,
821617bb 8 input [31:0] incpsr,
cb0428b6 9 input [31:0] inspsr,
bae77231
CL
10 output reg [31:0] op0,
11 output reg [31:0] op1,
12 output reg [31:0] op2,
42c1e610 13 output reg carry,
ab7ee9fc 14 output reg [31:0] outcpsr,
cb0428b6 15 output reg [31:0] outspsr,
bae77231 16
fbe84cc1
JW
17 output reg [3:0] read_0,
18 output reg [3:0] read_1,
19 output reg [3:0] read_2,
821617bb
JW
20 input [31:0] rdata_0,
21 input [31:0] rdata_1,
22 input [31:0] rdata_2
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CL
23 );
24
fbe84cc1
JW
25 wire [31:0] regs0, regs1, regs2;
26 reg [31:0] rpc;
27 reg [31:0] op0_out, op1_out, op2_out;
28 reg carry_out;
bae77231
CL
29
30 /* shifter stuff */
31 wire [31:0] shift_oper;
32 wire [31:0] shift_res;
33 wire shift_cflag_out;
a0c8a75c 34 wire [31:0] rotate_res;
bae77231 35
821617bb
JW
36 assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
37 assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
38 assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231 39
96f7e6e1
JW
40 IREALLYHATEARMSHIFT shift(.insn(insn),
41 .operand(regs1),
42 .reg_amt(regs2),
43 .cflag_in(incpsr[`CPSR_C]),
44 .res(shift_res),
45 .cflag_out(shift_cflag_out));
e2c5d224 46
a0c8a75c
CL
47 SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
48 .amt(insn[11:8]),
49 .res(rotate_res));
50
be64a9df
JW
51 always @(*)
52 casez (insn)
2c523f8a
JW
53 `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
54// `DECODE_ALU_MUL_LONG, /* Multiply long */
55 `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
56 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
57 `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
58 `DECODE_ALU_SWP, /* Atomic swap */
59 `DECODE_ALU_BX, /* Branch and exchange */
60 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
61 `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
62 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
63 `DECODE_LDRSTR, /* Single data transfer */
64 `DECODE_LDMSTM, /* Block data transfer */
65 `DECODE_BRANCH, /* Branch */
66 `DECODE_LDCSTC, /* Coprocessor data transfer */
67 `DECODE_CDP, /* Coprocessor data op */
2c523f8a 68 `DECODE_SWI: /* SWI */
b3bb2fb8 69 rpc = inpc + 8;
04d95cf5
JW
70 `DECODE_MRCMCR: /* Coprocessor register transfer */
71 rpc = inpc + 12;
2c523f8a 72 `DECODE_ALU: /* ALU */
b3bb2fb8 73 rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
2c523f8a 74 default: /* X everything else out */
be64a9df
JW
75 rpc = 32'hxxxxxxxx;
76 endcase
96f7e6e1 77
326fd4c3
JW
78 always @(*) begin
79 read_0 = 4'hx;
80 read_1 = 4'hx;
81 read_2 = 4'hx;
82
74b05f6e
JW
83 casez (insn)
84 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
85 begin
86 read_0 = insn[15:12]; /* Rn */
87 read_1 = insn[3:0]; /* Rm */
88 read_2 = insn[11:8]; /* Rs */
89 end
90 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
91 begin end
92 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
93 read_0 = insn[3:0]; /* Rm */
94 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
95 read_0 = insn[3:0]; /* Rm */
96 `DECODE_ALU_SWP: /* Atomic swap */
97 begin
98 read_0 = insn[19:16]; /* Rn */
99 read_1 = insn[3:0]; /* Rm */
100 end
101 `DECODE_ALU_BX: /* Branch and exchange */
102 read_0 = insn[3:0]; /* Rn */
103 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
104 begin
105 read_0 = insn[19:16];
106 read_1 = insn[3:0];
107 read_2 = insn[15:12];
108 end
109 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
110 begin
111 read_0 = insn[19:16];
112 read_1 = insn[15:12];
113 end
114 `DECODE_ALU: /* ALU */
115 begin
116 read_0 = insn[19:16]; /* Rn */
117 read_1 = insn[3:0]; /* Rm */
118 read_2 = insn[11:8]; /* Rs for shift */
119 end
120 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
121 begin end
122 `DECODE_LDRSTR: /* Single data transfer */
123 begin
124 read_0 = insn[19:16]; /* Rn */
125 read_1 = insn[3:0]; /* Rm */
126 read_2 = insn[15:12];
127 end
128 `DECODE_LDMSTM: /* Block data transfer */
129 read_0 = insn[19:16];
130 `DECODE_BRANCH: /* Branch */
131 begin end
132 `DECODE_LDCSTC: /* Coprocessor data transfer */
133 read_0 = insn[19:16];
134 `DECODE_CDP: /* Coprocessor data op */
135 begin end
136 `DECODE_MRCMCR: /* Coprocessor register transfer */
137 read_0 = insn[15:12];
138 `DECODE_SWI: /* SWI */
139 begin end
140 default:
141 $display("Undecoded instruction");
142 endcase
143 end
144
145 always @(*) begin
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JW
146 op0_out = 32'hxxxxxxxx;
147 op1_out = 32'hxxxxxxxx;
148 op2_out = 32'hxxxxxxxx;
149 carry_out = 1'bx;
150
0bc7ede9 151 casez (insn)
2c523f8a 152 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3 153 begin
96f7e6e1
JW
154 op0_out = regs0;
155 op1_out = regs1;
156 op2_out = regs2;
326fd4c3 157 end
2c523f8a 158 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
42c1e610 159 begin end
96f7e6e1 160 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
96f7e6e1 161 op0_out = regs0;
2c523f8a 162 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
96f7e6e1
JW
163 if(insn[25]) begin /* the constant case */
164 op0_out = rotate_res;
165 end else begin
166 op0_out = regs0;
167 end
2c523f8a 168 `DECODE_ALU_SWP: /* Atomic swap */
326fd4c3 169 begin
96f7e6e1
JW
170 op0_out = regs0;
171 op1_out = regs1;
326fd4c3 172 end
2c523f8a 173 `DECODE_ALU_BX: /* Branch and exchange */
96f7e6e1 174 op0_out = regs0;
2c523f8a 175 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
326fd4c3 176 begin
96f7e6e1
JW
177 op0_out = regs0;
178 op1_out = regs1;
778ef14f 179 op2_out = regs2;
326fd4c3 180 end
2c523f8a 181 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
326fd4c3 182 begin
96f7e6e1
JW
183 op0_out = regs0;
184 op1_out = {24'b0, insn[11:8], insn[3:0]};
778ef14f 185 op2_out = regs1;
326fd4c3 186 end
2c523f8a
JW
187 `DECODE_ALU: /* ALU */
188 begin
2c523f8a
JW
189 op0_out = regs0;
190 if(insn[25]) begin /* the constant case */
191 carry_out = incpsr[`CPSR_C];
192 op1_out = rotate_res;
193 end else begin
194 carry_out = shift_cflag_out;
195 op1_out = shift_res;
196 end
197 end
96f7e6e1
JW
198 `DECODE_LDRSTR: /* Single data transfer */
199 begin
42c1e610 200 op0_out = regs0;
ac3ba6ad 201 if(!insn[25] /* immediate */) begin
42c1e610
JW
202 op1_out = {20'b0, insn[11:0]};
203 carry_out = incpsr[`CPSR_C];
bae77231 204 end else begin
42c1e610
JW
205 op1_out = shift_res;
206 carry_out = shift_cflag_out;
bae77231 207 end
6d0f9d82 208 op2_out = regs2;
bae77231 209 end
96f7e6e1
JW
210 `DECODE_LDMSTM: /* Block data transfer */
211 begin
42c1e610
JW
212 op0_out = regs0;
213 op1_out = {16'b0, insn[15:0]};
bae77231 214 end
96f7e6e1 215 `DECODE_BRANCH: /* Branch */
42c1e610 216 op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
96f7e6e1
JW
217 `DECODE_LDCSTC: /* Coprocessor data transfer */
218 begin
42c1e610
JW
219 op0_out = regs0;
220 op1_out = {24'b0, insn[7:0]};
bae77231 221 end
96f7e6e1 222 `DECODE_CDP: /* Coprocessor data op */
74b05f6e 223 begin end
96f7e6e1 224 `DECODE_MRCMCR: /* Coprocessor register transfer */
42c1e610 225 op0_out = regs0;
96f7e6e1 226 `DECODE_SWI: /* SWI */
74b05f6e 227 begin end
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CL
228 endcase
229 end
96f7e6e1 230
bae77231 231 always @ (posedge clk) begin
e74c7936
JW
232 if (!stall)
233 begin
234 op0 <= op0_out; /* Rn - always */
235 op1 <= op1_out; /* 'operand 2' - Rm */
236 op2 <= op2_out; /* thirdedge - Rs */
237 carry <= carry_out;
238 outcpsr <= incpsr;
239 outspsr <= inspsr;
240 end
bae77231
CL
241 end
242
243endmodule
244
e2c5d224 245module IREALLYHATEARMSHIFT(
bae77231
CL
246 input [31:0] insn,
247 input [31:0] operand,
248 input [31:0] reg_amt,
249 input cflag_in,
fbe84cc1
JW
250 output reg [31:0] res,
251 output reg cflag_out
bae77231 252);
bae77231 253 wire [5:0] shift_amt;
f61f8d6f
JW
254 reg is_arith, is_rot;
255 wire rshift_cout;
256 wire [31:0] rshift_res;
e2c5d224
CL
257
258 assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
259 : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231 260
96f7e6e1 261 SuckLessShifter barrel(.oper(operand),
e2c5d224
CL
262 .carryin(cflag_in),
263 .amt(shift_amt),
264 .is_arith(is_arith),
265 .is_rot(is_rot),
266 .res(rshift_res),
267 .carryout(rshift_cout));
bae77231 268
821617bb 269 always @(*)
e2c5d224
CL
270 case (insn[6:5])
271 `SHIFT_LSL: begin
e5fb7d86 272 /* meaningless */
e2c5d224
CL
273 is_rot = 1'b0;
274 is_arith = 1'b0;
26049339 275 end
e2c5d224
CL
276 `SHIFT_LSR: begin
277 is_rot = 1'b0;
278 is_arith = 1'b0;
279 end
280 `SHIFT_ASR: begin
281 is_rot = 1'b0;
282 is_arith = 1'b1;
283 end
284 `SHIFT_ROR: begin
285 is_rot = 1'b1;
286 is_arith = 1'b0;
287 end
288 endcase
289
821617bb 290 always @(*)
26049339 291 case (insn[6:5]) /* shift type */
e2c5d224
CL
292 `SHIFT_LSL:
293 {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231 294 `SHIFT_LSR: begin
e2c5d224
CL
295 res = rshift_res;
296 cflag_out = rshift_cout;
bae77231
CL
297 end
298 `SHIFT_ASR: begin
e2c5d224
CL
299 res = rshift_res;
300 cflag_out = rshift_cout;
bae77231
CL
301 end
302 `SHIFT_ROR: begin
e2c5d224 303 if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231
CL
304 res = {cflag_in, operand[31:1]};
305 cflag_out = operand[0];
e5fb7d86 306 end else begin
e2c5d224
CL
307 res = rshift_res;
308 cflag_out = rshift_cout;
bae77231
CL
309 end
310 end
26049339 311 endcase
bae77231 312endmodule
e2c5d224
CL
313
314module SuckLessShifter(
315 input [31:0] oper,
316 input carryin,
317 input [5:0] amt,
318 input is_arith,
319 input is_rot,
f61f8d6f
JW
320 output wire [31:0] res,
321 output wire carryout
e2c5d224
CL
322);
323
324 wire [32:0] stage1, stage2, stage3, stage4, stage5;
325
e5fb7d86 326 wire pushbits = is_arith & oper[31];
e2c5d224
CL
327
328 /* do a barrel shift */
329 assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
6c715b10
CL
330 assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
331 assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
332 assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
333 assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
334 assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
e2c5d224
CL
335
336endmodule
a0c8a75c
CL
337
338module SuckLessRotator(
339 input [31:0] oper,
340 input [3:0] amt,
f61f8d6f 341 output wire [31:0] res
a0c8a75c
CL
342);
343
344 wire [31:0] stage1, stage2, stage3;
345 assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
346 assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
347 assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
348 assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
349
350endmodule
96f7e6e1 351
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