Deal with at least one case of A in decode by moving rpc out to its own case statemen...
[firearm.git] / Decode.v
CommitLineData
26049339
CL
1`include "ARM_Constants.v"
2
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3module Decode(
4 input clk,
be64a9df 5 input [31:0] insn,
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6 input [31:0] inpc,
7 input [31:0] cps_in,
8 output reg [31:0] op0,
9 output reg [31:0] op1,
10 output reg [31:0] op2,
11 output reg [31:0] cps_out,
12
13 output [3:0] regsel0,
14 output [3:0] regsel1,
15 output [3:0] regsel2,
16 input [31:0] iregs0,
17 input [31:0] iregs1,
18 input [31:0] iregs2
19 );
20
21 wire [31:0] regs0, regs1, regs2, rpc;
22 wire [31:0] op1_res, new_cps;
23
24 /* shifter stuff */
25 wire [31:0] shift_oper;
26 wire [31:0] shift_res;
27 wire shift_cflag_out;
28
29 assign regs0 = (regsel0 == 4'b1111) ? rpc : iregs0;
30 assign regs1 = (regsel1 == 4'b1111) ? rpc : iregs1;
31 assign regs2 = iregs2; /* use regs2 for things that cannot be r15 */
32
be64a9df 33 IHATEARMSHIFT blowme(.insn(insn),
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34 .operand(regs1),
35 .reg_amt(regs2),
36 .cflag_in(cps_in[`CPSR_C]),
37 .res(shift_res),
38 .cflag_out(shift_cflag_out));
be64a9df
JW
39
40 always @(*)
41 casez (insn)
42 32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
43// 32'b????00001???????????????1001????, /* Multiply long */
44 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
45 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
46 32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
47 32'b????00010?00????????00001001????, /* Atomic swap */
48 32'b????000100101111111111110001????, /* Branch */
49 32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
50 32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
51 32'b????011????????????????????1????, /* Undefined. I hate ARM */
52 32'b????01??????????????????????????, /* Single data transfer */
53 32'b????100?????????????????????????, /* Block data transfer */
54 32'b????101?????????????????????????, /* Branch */
55 32'b????110?????????????????????????, /* Coprocessor data transfer */
56 32'b????1110???????????????????0????, /* Coprocessor data op */
57 32'b????1110???????????????????1????, /* Coprocessor register transfer */
58 32'b????1111????????????????????????: /* SWI */
59 rpc = inpc - 8;
60 32'b????00??????????????????????????: /* ALU */
61 rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
62 default: /* X everything else out */
63 rpc = 32'hxxxxxxxx;
64 endcase
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65
66 always @ (*) begin
be64a9df 67 casez (insn)
bae77231 68 32'b????000000??????????????1001????: begin /* Multiply */
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69 regsel0 = insn[15:12]; /* Rn */
70 regsel1 = insn[3:0]; /* Rm */
71 regsel2 = insn[11:8]; /* Rs */
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72 op1_res = regs1;
73 new_cps = cps_in;
74 end
75/*
76 32'b????00001???????????????1001????: begin * Multiply long *
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JW
77 regsel0 = insn[11:8]; * Rn *
78 regsel1 = insn[3:0]; * Rm *
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79 regsel2 = 4'b0; * anyus *
80 op1_res = regs1;
81 end
82*/
83 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
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84 new_cps = cps_in;
85 end
86 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
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87 new_cps = cps_in;
88 end
89 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
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90 new_cps = cps_in;
91 end
92 32'b????00??????????????????????????: begin /* ALU */
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JW
93 regsel0 = insn[19:16]; /* Rn */
94 regsel1 = insn[3:0]; /* Rm */
95 regsel2 = insn[11:8]; /* Rs for shift */
96 if(insn[25]) begin /* the constant case */
bae77231 97 new_cps = cps_in;
be64a9df 98 op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
bae77231 99 end else begin
26049339 100 new_cps = {cps_in[31:30], shift_cflag_out, cps_in[28:0]};
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101 op1_res = shift_res;
102 end
103 end
104 32'b????00010?00????????00001001????: begin /* Atomic swap */
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105 regsel0 = insn[19:16]; /* Rn */
106 regsel1 = insn[3:0]; /* Rm */
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107 regsel2 = 4'b0; /* anyus */
108 op1_res = regs1;
109 end
110 32'b????000100101111111111110001????: begin /* Branch and exchange */
be64a9df 111 regsel0 = insn[3:0]; /* Rn */
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112 new_cps = cps_in;
113 end
114 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
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115 regsel0 = insn[19:16];
116 regsel1 = insn[3:0];
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117 regsel2 = 4'b0;
118 op1_res = regs1;
119 new_cps = cps_in;
120 end
121 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
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122 regsel0 = insn[19:16];
123 regsel1 = insn[3:0];
124 op1_res = {24'b0, insn[11:8], insn[3:0]};
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125 new_cps = cps_in;
126 end
127 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
128 /* eat shit */
129 end
130 32'b????01??????????????????????????: begin /* Single data transfer */
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JW
131 regsel0 = insn[19:16]; /* Rn */
132 regsel1 = insn[3:0]; /* Rm */
133 if(insn[25]) begin
134 op1_res = {20'b0, insn[11:0]};
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135 new_cps = cps_in;
136 end else begin
137 op1_res = shift_res;
26049339 138 new_cps = {cps_in[31:30], shift_cflag_out, cps_in[28:0]};
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139 end
140 end
141 32'b????100?????????????????????????: begin /* Block data transfer */
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JW
142 regsel0 = insn[19:16];
143 op1_res = {16'b0, insn[15:0]};
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144 new_cps = cps_in;
145 end
146 32'b????101?????????????????????????: begin /* Branch */
be64a9df 147 op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
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148 new_cps = cps_in;
149 end
150 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
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JW
151 regsel0 = insn[19:16];
152 op1_res = {24'b0, insn[7:0]};
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153 new_cps = cps_in;
154 end
155 32'b????1110???????????????????0????: begin /* Coprocessor data op */
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156 new_cps = cps_in;
157 end
158 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
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159 new_cps = cps_in;
160 end
161 32'b????1111????????????????????????: begin /* SWI */
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162 new_cps = cps_in;
163 end
26049339 164 default: begin end
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165 endcase
166 end
167
168 always @ (posedge clk) begin
169 op0 <= regs0; /* Rn - always */
170 op1 <= op1_res; /* 'operand 2' - Rm */
171 op2 <= regs2; /* thirdedge - Rs */
172 cps_out <= new_cps;
173 end
174
175endmodule
176
177module IHATEARMSHIFT(
178 input [31:0] insn,
179 input [31:0] operand,
180 input [31:0] reg_amt,
181 input cflag_in,
182 output [31:0] res,
183 output cflag_out
184);
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185 wire [5:0] shift_amt;
186 wire elanus;
187
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188
189 /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
190 always @ (*) begin
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CL
191 if(insn[4]) begin
192 shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
193 elanus = 1'b1;
194 end else begin
195 shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
196 elanus = 1'b0;
197 end
198
199 case (insn[6:5]) /* shift type */
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200 `SHIFT_LSL: begin
201 {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
202 end
203 `SHIFT_LSR: begin
204 {res, cflag_out} = {operand, cflag_in} >> shift_amt;
205 end
206 `SHIFT_ASR: begin
207 {res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
208 end
209 `SHIFT_ROR: begin
210 if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
211 res = {cflag_in, operand[31:1]};
212 cflag_out = operand[0];
26049339 213 end else if(shift_amt == 6'b0) begin
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214 res = operand;
215 cflag_out = cflag_in;
216 end else begin
217 res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]);
218 cflag_out = operand[shift_amt[4:0] - 5'b1];
219 end
220 end
26049339 221 endcase
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222 end
223endmodule
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