[firearm.git] / Decode.v

`include "ARM_Constants.v"

module Decode(
	input clk,
	input [31:0] insn,
	input [31:0] inpc,
	input [31:0] incpsr,
	output reg [31:0] op0,
	output reg [31:0] op1,
	output reg [31:0] op2,
	output reg carry,

	output reg [3:0] read_0,
	output reg [3:0] read_1,
	output reg [3:0] read_2,
	input [31:0] rdata_0,
	input [31:0] rdata_1,
	input [31:0] rdata_2
	);

	wire [31:0] regs0, regs1, regs2;
	reg [31:0] rpc;
	reg [31:0] op0_out, op1_out, op2_out;
	reg carry_out;

	/* shifter stuff */
	wire [31:0] shift_oper;
	wire [31:0] shift_res;
	wire shift_cflag_out;
	wire [31:0] rotate_res;

	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */

	IREALLYHATEARMSHIFT shift(.insn(insn),
	                          .operand(regs1),
	                          .reg_amt(regs2),
	                          .cflag_in(incpsr[`CPSR_C]),
	                          .res(shift_res),
	                          .cflag_out(shift_cflag_out));

	SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
	                      .amt(insn[11:8]),
	                      .res(rotate_res));

	always @(*)
		casez (insn)
		`DECODE_ALU_MULT,		/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
//		`DECODE_ALU_MUL_LONG,		/* Multiply long */
		`DECODE_ALU_MRS,		/* MRS (Transfer PSR to register) */
		`DECODE_ALU_MSR,		/* MSR (Transfer register to PSR) */
		`DECODE_ALU_MSR_FLAGS,		/* MSR (Transfer register or immediate to PSR, flag bits only) */
		`DECODE_ALU_SWP,		/* Atomic swap */
		`DECODE_ALU_BX,			/* Branch and exchange */
		`DECODE_ALU_HDATA_REG,		/* Halfword transfer - register offset */
		`DECODE_ALU_HDATA_IMM,		/* Halfword transfer - register offset */
		`DECODE_LDRSTR_UNDEFINED,	/* Undefined. I hate ARM */
		`DECODE_LDRSTR,			/* Single data transfer */
		`DECODE_LDMSTM,			/* Block data transfer */
		`DECODE_BRANCH,			/* Branch */
		`DECODE_LDCSTC,			/* Coprocessor data transfer */
		`DECODE_CDP,			/* Coprocessor data op */
		`DECODE_MRCMCR,			/* Coprocessor register transfer */
		`DECODE_SWI:			/* SWI */
			rpc = inpc - 8;
		`DECODE_ALU:			/* ALU */
			rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
		default:			/* X everything else out */
			rpc = 32'hxxxxxxxx;
		endcase
	
	always @(*) begin
		read_0 = 4'hx;
		read_1 = 4'hx;
		read_2 = 4'hx;
		
		op0_out = 32'hxxxxxxxx;
		op1_out = 32'hxxxxxxxx;
		op2_out = 32'hxxxxxxxx;
		carry_out = 1'bx;
		
		casez (insn)
		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			read_0 = insn[15:12]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs */
			
			op0_out = regs0;
			op1_out = regs1;
			op2_out = regs2;
		end
//		`DECODE_ALU_MUL_LONG:	/* Multiply long */
//		begin
//			read_0 = insn[11:8]; /* Rn */
//			read_1 = insn[3:0];   /* Rm */
//			read_2 = 4'b0;       /* anyus */
//
//			op1_res = regs1;
//		end
		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
		begin end
		`DECODE_ALU_MSR:	/* MSR (Transfer register to PSR) */
		begin
			read_0 = insn[3:0];	/* Rm */
			
			op0_out = regs0;
		end
		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		begin
			read_0 = insn[3:0];	/* Rm */
			
			if(insn[25]) begin     /* the constant case */
				op0_out = rotate_res;
			end else begin
				op0_out = regs0;
			end
		end
		`DECODE_ALU_SWP:	/* Atomic swap */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			
			op0_out = regs0;
			op1_out = regs1;
		end
		`DECODE_ALU_BX:		/* Branch and exchange */
		begin
			read_0 = insn[3:0];   /* Rn */
			
			op0_out = regs0;
		end
		`DECODE_ALU_HDATA_REG:	/* Halfword transfer - register offset */
		begin
			read_0 = insn[19:16];
			read_1 = insn[3:0];
			
			op0_out = regs0;
			op1_out = regs1;
		end
		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
		begin
			read_0 = insn[19:16];
			
			op0_out = regs0;
			op1_out = {24'b0, insn[11:8], insn[3:0]};
		end
		`DECODE_ALU:		/* ALU */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs for shift */
			
			op0_out = regs0;
			if(insn[25]) begin     /* the constant case */
				carry_out = incpsr[`CPSR_C];
				op1_out = rotate_res;
			end else begin
				carry_out = shift_cflag_out;
				op1_out = shift_res;
			end
		end
		`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
		begin
			/* eat shit */
		end
		`DECODE_LDRSTR:		/* Single data transfer */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			
			op0_out = regs0;
			if(insn[25]) begin
				op1_out = {20'b0, insn[11:0]};
				carry_out = incpsr[`CPSR_C];
			end else begin
				op1_out = shift_res;
				carry_out = shift_cflag_out;
			end
		end
		`DECODE_LDMSTM:		/* Block data transfer */
		begin
			read_0 = insn[19:16];
			
			op0_out = regs0;
			op1_out = {16'b0, insn[15:0]};
		end
		`DECODE_BRANCH:		/* Branch */
		begin
			op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
		end
		`DECODE_LDCSTC:		/* Coprocessor data transfer */
		begin
			read_0 = insn[19:16];
			
			op0_out = regs0;
			op1_out = {24'b0, insn[7:0]};
		end
		`DECODE_CDP:		/* Coprocessor data op */
		begin
		end
		`DECODE_MRCMCR:		/* Coprocessor register transfer */
		begin
			read_0 = insn[15:12];
			
			op0_out = regs0;
		end
		`DECODE_SWI:		/* SWI */
		begin
		end
		default:
			$display("Undecoded instruction");
		endcase
	end

	
	always @ (posedge clk) begin
		op0 <= op0_out;   /* Rn - always */
		op1 <= op1_out; /* 'operand 2' - Rm */
		op2 <= op2_out;   /* thirdedge - Rs */
		carry <= carry_out;
	end

endmodule

module IREALLYHATEARMSHIFT(
	input [31:0] insn,
	input [31:0] operand,
	input [31:0] reg_amt,
	input cflag_in,
	output reg [31:0] res,
	output reg cflag_out
);
	wire [5:0] shift_amt;
	reg is_arith, is_rot;
	wire rshift_cout;
	wire [31:0] rshift_res;

	assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
	                           : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */

	SuckLessShifter barrel(.oper(operand),
	                       .carryin(cflag_in),
	                       .amt(shift_amt),
	                       .is_arith(is_arith),
	                       .is_rot(is_rot),
	                       .res(rshift_res),
	                       .carryout(rshift_cout));

	always @(*)
		case (insn[6:5])
		`SHIFT_LSL: begin
			/* meaningless */
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_LSR: begin
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_ASR: begin
			is_rot = 1'b0;
			is_arith = 1'b1;
		end
		`SHIFT_ROR: begin
			is_rot = 1'b1;
			is_arith = 1'b0;
		end
		endcase

	always @(*)
		case (insn[6:5]) /* shift type */
		`SHIFT_LSL:
			{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
		`SHIFT_LSR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ASR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ROR: begin
			if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
				res = {cflag_in, operand[31:1]};
				cflag_out = operand[0];
			end else begin
				res = rshift_res;
				cflag_out = rshift_cout;
			end
		end
		endcase
endmodule

module SuckLessShifter(
	input [31:0] oper,
	input carryin,
	input [5:0] amt,
	input is_arith,
	input is_rot,
	output wire [31:0] res,
	output wire carryout
);

	wire [32:0] stage1, stage2, stage3, stage4, stage5;

	wire pushbits = is_arith & oper[31];

	/* do a barrel shift */
	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
	assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
	assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
	assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
	assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
	assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;

endmodule

module SuckLessRotator(
	input [31:0] oper,
	input [3:0] amt,
	output wire [31:0] res
);

	wire [31:0] stage1, stage2, stage3;
	assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
	assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
	assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
	assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;

endmodule
Commit	Line	Data
26049339 CL	1	`include "ARM_Constants.v"
26049339 CL	2
bae77231 CL	3	module Decode(
bae77231 CL	4	input clk,
be64a9df	5	input [31:0] insn,
bae77231	6	input [31:0] inpc,
821617bb	7	input [31:0] incpsr,
bae77231 CL	8	output reg [31:0] op0,
	9	output reg [31:0] op1,
	10	output reg [31:0] op2,
42c1e610	11	output reg carry,
bae77231	12
fbe84cc1 JW	13	output reg [3:0] read_0,
	14	output reg [3:0] read_1,
	15	output reg [3:0] read_2,
821617bb JW	16	input [31:0] rdata_0,
	17	input [31:0] rdata_1,
	18	input [31:0] rdata_2
bae77231 CL	19	);
bae77231 CL	20
fbe84cc1 JW	21	wire [31:0] regs0, regs1, regs2;
	22	reg [31:0] rpc;
	23	reg [31:0] op0_out, op1_out, op2_out;
	24	reg carry_out;
bae77231 CL	25
	26	/* shifter stuff */
	27	wire [31:0] shift_oper;
	28	wire [31:0] shift_res;
	29	wire shift_cflag_out;
a0c8a75c	30	wire [31:0] rotate_res;
bae77231	31
821617bb JW	32	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	33	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	34	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231	35
96f7e6e1 JW	36	IREALLYHATEARMSHIFT shift(.insn(insn),
	37	.operand(regs1),
	38	.reg_amt(regs2),
	39	.cflag_in(incpsr[`CPSR_C]),
	40	.res(shift_res),
	41	.cflag_out(shift_cflag_out));
e2c5d224	42
a0c8a75c CL	43	SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
	44	.amt(insn[11:8]),
	45	.res(rotate_res));
	46
be64a9df JW	47	always @(*)
be64a9df JW	48	casez (insn)
2c523f8a JW	49	`DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	50	// `DECODE_ALU_MUL_LONG, /* Multiply long */
	51	`DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
	52	`DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
	53	`DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
	54	`DECODE_ALU_SWP, /* Atomic swap */
	55	`DECODE_ALU_BX, /* Branch and exchange */
	56	`DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
	57	`DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
	58	`DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
	59	`DECODE_LDRSTR, /* Single data transfer */
	60	`DECODE_LDMSTM, /* Block data transfer */
	61	`DECODE_BRANCH, /* Branch */
	62	`DECODE_LDCSTC, /* Coprocessor data transfer */
	63	`DECODE_CDP, /* Coprocessor data op */
	64	`DECODE_MRCMCR, /* Coprocessor register transfer */
	65	`DECODE_SWI: /* SWI */
be64a9df	66	rpc = inpc - 8;
2c523f8a	67	`DECODE_ALU: /* ALU */
be64a9df	68	rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
2c523f8a	69	default: /* X everything else out */
be64a9df JW	70	rpc = 32'hxxxxxxxx;
be64a9df JW	71	endcase
96f7e6e1	72
326fd4c3 JW	73	always @(*) begin
	74	read_0 = 4'hx;
	75	read_1 = 4'hx;
	76	read_2 = 4'hx;
	77
96f7e6e1 JW	78	op0_out = 32'hxxxxxxxx;
	79	op1_out = 32'hxxxxxxxx;
	80	op2_out = 32'hxxxxxxxx;
	81	carry_out = 1'bx;
	82
0bc7ede9	83	casez (insn)
2c523f8a	84	`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3	85	begin
0bc7ede9	86	read_0 = insn[15:12]; /* Rn */
326fd4c3 JW	87	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	88	read_2 = insn[11:8]; /* Rs */
96f7e6e1 JW	89
	90	op0_out = regs0;
	91	op1_out = regs1;
	92	op2_out = regs2;
326fd4c3	93	end
2c523f8a	94	// `DECODE_ALU_MUL_LONG: /* Multiply long */
96f7e6e1	95	// begin
0bc7ede9	96	// read_0 = insn[11:8]; /* Rn */
326fd4c3 JW	97	// read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	98	// read_2 = 4'b0; /* anyus */
96f7e6e1 JW	99	//
	100	// op1_res = regs1;
	101	// end
2c523f8a	102	`DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
42c1e610	103	begin end
96f7e6e1 JW	104	`DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
	105	begin
	106	read_0 = insn[3:0]; /* Rm */
	107
	108	op0_out = regs0;
	109	end
2c523f8a	110	`DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
96f7e6e1	111	begin
42c1e610	112	read_0 = insn[3:0]; /* Rm */
96f7e6e1 JW	113
	114	if(insn[25]) begin /* the constant case */
	115	op0_out = rotate_res;
	116	end else begin
	117	op0_out = regs0;
	118	end
	119	end
2c523f8a	120	`DECODE_ALU_SWP: /* Atomic swap */
326fd4c3	121	begin
0bc7ede9	122	read_0 = insn[19:16]; /* Rn */
326fd4c3	123	read_1 = insn[3:0]; /* Rm */
96f7e6e1 JW	124
	125	op0_out = regs0;
	126	op1_out = regs1;
326fd4c3	127	end
2c523f8a	128	`DECODE_ALU_BX: /* Branch and exchange */
96f7e6e1	129	begin
0bc7ede9	130	read_0 = insn[3:0]; /* Rn */
96f7e6e1 JW	131
	132	op0_out = regs0;
	133	end
2c523f8a	134	`DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
326fd4c3	135	begin
0bc7ede9	136	read_0 = insn[19:16];
326fd4c3	137	read_1 = insn[3:0];
96f7e6e1 JW	138
	139	op0_out = regs0;
	140	op1_out = regs1;
326fd4c3	141	end
2c523f8a	142	`DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
326fd4c3	143	begin
0bc7ede9	144	read_0 = insn[19:16];
96f7e6e1 JW	145
	146	op0_out = regs0;
	147	op1_out = {24'b0, insn[11:8], insn[3:0]};
326fd4c3	148	end
2c523f8a JW	149	`DECODE_ALU: /* ALU */
	150	begin
	151	read_0 = insn[19:16]; /* Rn */
	152	read_1 = insn[3:0]; /* Rm */
	153	read_2 = insn[11:8]; /* Rs for shift */
96f7e6e1	154
2c523f8a JW	155	op0_out = regs0;
	156	if(insn[25]) begin /* the constant case */
	157	carry_out = incpsr[`CPSR_C];
	158	op1_out = rotate_res;
	159	end else begin
	160	carry_out = shift_cflag_out;
	161	op1_out = shift_res;
	162	end
	163	end
96f7e6e1 JW	164	`DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
96f7e6e1 JW	165	begin
bae77231 CL	166	/* eat shit */
bae77231 CL	167	end
96f7e6e1 JW	168	`DECODE_LDRSTR: /* Single data transfer */
	169	begin
	170	read_0 = insn[19:16]; /* Rn */
	171	read_1 = insn[3:0]; /* Rm */
	172
42c1e610	173	op0_out = regs0;
be64a9df	174	if(insn[25]) begin
42c1e610 JW	175	op1_out = {20'b0, insn[11:0]};
42c1e610 JW	176	carry_out = incpsr[`CPSR_C];
bae77231	177	end else begin
42c1e610 JW	178	op1_out = shift_res;
42c1e610 JW	179	carry_out = shift_cflag_out;
bae77231 CL	180	end
bae77231 CL	181	end
96f7e6e1 JW	182	`DECODE_LDMSTM: /* Block data transfer */
	183	begin
	184	read_0 = insn[19:16];
	185
42c1e610 JW	186	op0_out = regs0;
42c1e610 JW	187	op1_out = {16'b0, insn[15:0]};
bae77231	188	end
96f7e6e1 JW	189	`DECODE_BRANCH: /* Branch */
96f7e6e1 JW	190	begin
42c1e610	191	op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231	192	end
96f7e6e1 JW	193	`DECODE_LDCSTC: /* Coprocessor data transfer */
	194	begin
	195	read_0 = insn[19:16];
	196
42c1e610 JW	197	op0_out = regs0;
42c1e610 JW	198	op1_out = {24'b0, insn[7:0]};
bae77231	199	end
96f7e6e1 JW	200	`DECODE_CDP: /* Coprocessor data op */
96f7e6e1 JW	201	begin
bae77231	202	end
96f7e6e1 JW	203	`DECODE_MRCMCR: /* Coprocessor register transfer */
	204	begin
	205	read_0 = insn[15:12];
	206
42c1e610	207	op0_out = regs0;
bae77231	208	end
96f7e6e1 JW	209	`DECODE_SWI: /* SWI */
96f7e6e1 JW	210	begin
bae77231	211	end
96f7e6e1 JW	212	default:
96f7e6e1 JW	213	$display("Undecoded instruction");
bae77231 CL	214	endcase
	215	end
	216
96f7e6e1	217
bae77231	218	always @ (posedge clk) begin
42c1e610 JW	219	op0 <= op0_out; /* Rn - always */
	220	op1 <= op1_out; /* 'operand 2' - Rm */
	221	op2 <= op2_out; /* thirdedge - Rs */
	222	carry <= carry_out;
bae77231 CL	223	end
	224
	225	endmodule
	226
e2c5d224	227	module IREALLYHATEARMSHIFT(
bae77231 CL	228	input [31:0] insn,
	229	input [31:0] operand,
	230	input [31:0] reg_amt,
	231	input cflag_in,
fbe84cc1 JW	232	output reg [31:0] res,
fbe84cc1 JW	233	output reg cflag_out
bae77231	234	);
bae77231	235	wire [5:0] shift_amt;
f61f8d6f JW	236	reg is_arith, is_rot;
	237	wire rshift_cout;
	238	wire [31:0] rshift_res;
e2c5d224 CL	239
	240	assign shift_amt = insn[4] ? {\|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
	241	: {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231	242
96f7e6e1	243	SuckLessShifter barrel(.oper(operand),
e2c5d224 CL	244	.carryin(cflag_in),
	245	.amt(shift_amt),
	246	.is_arith(is_arith),
	247	.is_rot(is_rot),
	248	.res(rshift_res),
	249	.carryout(rshift_cout));
bae77231	250
821617bb	251	always @(*)
e2c5d224 CL	252	case (insn[6:5])
e2c5d224 CL	253	`SHIFT_LSL: begin
e5fb7d86	254	/* meaningless */
e2c5d224 CL	255	is_rot = 1'b0;
e2c5d224 CL	256	is_arith = 1'b0;
26049339	257	end
e2c5d224 CL	258	`SHIFT_LSR: begin
	259	is_rot = 1'b0;
	260	is_arith = 1'b0;
	261	end
	262	`SHIFT_ASR: begin
	263	is_rot = 1'b0;
	264	is_arith = 1'b1;
	265	end
	266	`SHIFT_ROR: begin
	267	is_rot = 1'b1;
	268	is_arith = 1'b0;
	269	end
	270	endcase
	271
821617bb	272	always @(*)
26049339	273	case (insn[6:5]) /* shift type */
e2c5d224 CL	274	`SHIFT_LSL:
e2c5d224 CL	275	{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231	276	`SHIFT_LSR: begin
e2c5d224 CL	277	res = rshift_res;
e2c5d224 CL	278	cflag_out = rshift_cout;
bae77231 CL	279	end
bae77231 CL	280	`SHIFT_ASR: begin
e2c5d224 CL	281	res = rshift_res;
e2c5d224 CL	282	cflag_out = rshift_cout;
bae77231 CL	283	end
bae77231 CL	284	`SHIFT_ROR: begin
e2c5d224	285	if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231 CL	286	res = {cflag_in, operand[31:1]};
bae77231 CL	287	cflag_out = operand[0];
e5fb7d86	288	end else begin
e2c5d224 CL	289	res = rshift_res;
e2c5d224 CL	290	cflag_out = rshift_cout;
bae77231 CL	291	end
bae77231 CL	292	end
26049339	293	endcase
bae77231	294	endmodule
e2c5d224 CL	295
	296	module SuckLessShifter(
	297	input [31:0] oper,
	298	input carryin,
	299	input [5:0] amt,
	300	input is_arith,
	301	input is_rot,
f61f8d6f JW	302	output wire [31:0] res,
f61f8d6f JW	303	output wire carryout
e2c5d224 CL	304	);
	305
	306	wire [32:0] stage1, stage2, stage3, stage4, stage5;
	307
e5fb7d86	308	wire pushbits = is_arith & oper[31];
e2c5d224 CL	309
	310	/* do a barrel shift */
	311	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
6c715b10 CL	312	assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
	313	assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
	314	assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
	315	assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
	316	assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
e2c5d224 CL	317
e2c5d224 CL	318	endmodule
a0c8a75c CL	319
	320	module SuckLessRotator(
	321	input [31:0] oper,
	322	input [3:0] amt,
f61f8d6f	323	output wire [31:0] res
a0c8a75c CL	324	);
	325
	326	wire [31:0] stage1, stage2, stage3;
	327	assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
	328	assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
	329	assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
	330	assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
	331
	332	endmodule
96f7e6e1	333