memory wea
[firearm.git] / Decode.v
CommitLineData
26049339
CL
1`include "ARM_Constants.v"
2
bae77231
CL
3module Decode(
4 input clk,
be64a9df 5 input [31:0] insn,
bae77231 6 input [31:0] inpc,
821617bb 7 input [31:0] incpsr,
cb0428b6 8 input [31:0] inspsr,
bae77231
CL
9 output reg [31:0] op0,
10 output reg [31:0] op1,
11 output reg [31:0] op2,
42c1e610 12 output reg carry,
cb0428b6 13 output reg [31:0] outspsr,
bae77231 14
fbe84cc1
JW
15 output reg [3:0] read_0,
16 output reg [3:0] read_1,
17 output reg [3:0] read_2,
821617bb
JW
18 input [31:0] rdata_0,
19 input [31:0] rdata_1,
20 input [31:0] rdata_2
bae77231
CL
21 );
22
fbe84cc1
JW
23 wire [31:0] regs0, regs1, regs2;
24 reg [31:0] rpc;
25 reg [31:0] op0_out, op1_out, op2_out;
26 reg carry_out;
bae77231
CL
27
28 /* shifter stuff */
29 wire [31:0] shift_oper;
30 wire [31:0] shift_res;
31 wire shift_cflag_out;
a0c8a75c 32 wire [31:0] rotate_res;
bae77231 33
821617bb
JW
34 assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
35 assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
36 assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231 37
96f7e6e1
JW
38 IREALLYHATEARMSHIFT shift(.insn(insn),
39 .operand(regs1),
40 .reg_amt(regs2),
41 .cflag_in(incpsr[`CPSR_C]),
42 .res(shift_res),
43 .cflag_out(shift_cflag_out));
e2c5d224 44
a0c8a75c
CL
45 SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
46 .amt(insn[11:8]),
47 .res(rotate_res));
48
be64a9df
JW
49 always @(*)
50 casez (insn)
2c523f8a
JW
51 `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
52// `DECODE_ALU_MUL_LONG, /* Multiply long */
53 `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
54 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
55 `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
56 `DECODE_ALU_SWP, /* Atomic swap */
57 `DECODE_ALU_BX, /* Branch and exchange */
58 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
59 `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
60 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
61 `DECODE_LDRSTR, /* Single data transfer */
62 `DECODE_LDMSTM, /* Block data transfer */
63 `DECODE_BRANCH, /* Branch */
64 `DECODE_LDCSTC, /* Coprocessor data transfer */
65 `DECODE_CDP, /* Coprocessor data op */
2c523f8a 66 `DECODE_SWI: /* SWI */
b3bb2fb8 67 rpc = inpc + 8;
04d95cf5
JW
68 `DECODE_MRCMCR: /* Coprocessor register transfer */
69 rpc = inpc + 12;
2c523f8a 70 `DECODE_ALU: /* ALU */
b3bb2fb8 71 rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
2c523f8a 72 default: /* X everything else out */
be64a9df
JW
73 rpc = 32'hxxxxxxxx;
74 endcase
96f7e6e1 75
326fd4c3
JW
76 always @(*) begin
77 read_0 = 4'hx;
78 read_1 = 4'hx;
79 read_2 = 4'hx;
80
96f7e6e1
JW
81 op0_out = 32'hxxxxxxxx;
82 op1_out = 32'hxxxxxxxx;
83 op2_out = 32'hxxxxxxxx;
84 carry_out = 1'bx;
85
0bc7ede9 86 casez (insn)
2c523f8a 87 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3 88 begin
0bc7ede9 89 read_0 = insn[15:12]; /* Rn */
326fd4c3
JW
90 read_1 = insn[3:0]; /* Rm */
91 read_2 = insn[11:8]; /* Rs */
96f7e6e1
JW
92
93 op0_out = regs0;
94 op1_out = regs1;
95 op2_out = regs2;
326fd4c3 96 end
2c523f8a 97// `DECODE_ALU_MUL_LONG: /* Multiply long */
96f7e6e1 98// begin
0bc7ede9 99// read_0 = insn[11:8]; /* Rn */
326fd4c3
JW
100// read_1 = insn[3:0]; /* Rm */
101// read_2 = 4'b0; /* anyus */
96f7e6e1
JW
102//
103// op1_res = regs1;
104// end
2c523f8a 105 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
42c1e610 106 begin end
96f7e6e1
JW
107 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
108 begin
109 read_0 = insn[3:0]; /* Rm */
110
111 op0_out = regs0;
112 end
2c523f8a 113 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
96f7e6e1 114 begin
42c1e610 115 read_0 = insn[3:0]; /* Rm */
96f7e6e1
JW
116
117 if(insn[25]) begin /* the constant case */
118 op0_out = rotate_res;
119 end else begin
120 op0_out = regs0;
121 end
122 end
2c523f8a 123 `DECODE_ALU_SWP: /* Atomic swap */
326fd4c3 124 begin
0bc7ede9 125 read_0 = insn[19:16]; /* Rn */
326fd4c3 126 read_1 = insn[3:0]; /* Rm */
96f7e6e1
JW
127
128 op0_out = regs0;
129 op1_out = regs1;
326fd4c3 130 end
2c523f8a 131 `DECODE_ALU_BX: /* Branch and exchange */
96f7e6e1 132 begin
0bc7ede9 133 read_0 = insn[3:0]; /* Rn */
96f7e6e1
JW
134
135 op0_out = regs0;
136 end
2c523f8a 137 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
326fd4c3 138 begin
0bc7ede9 139 read_0 = insn[19:16];
326fd4c3 140 read_1 = insn[3:0];
96f7e6e1
JW
141
142 op0_out = regs0;
143 op1_out = regs1;
326fd4c3 144 end
2c523f8a 145 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
326fd4c3 146 begin
0bc7ede9 147 read_0 = insn[19:16];
96f7e6e1
JW
148
149 op0_out = regs0;
150 op1_out = {24'b0, insn[11:8], insn[3:0]};
326fd4c3 151 end
2c523f8a
JW
152 `DECODE_ALU: /* ALU */
153 begin
154 read_0 = insn[19:16]; /* Rn */
155 read_1 = insn[3:0]; /* Rm */
156 read_2 = insn[11:8]; /* Rs for shift */
96f7e6e1 157
2c523f8a
JW
158 op0_out = regs0;
159 if(insn[25]) begin /* the constant case */
160 carry_out = incpsr[`CPSR_C];
161 op1_out = rotate_res;
162 end else begin
163 carry_out = shift_cflag_out;
164 op1_out = shift_res;
165 end
166 end
96f7e6e1
JW
167 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
168 begin
bae77231
CL
169 /* eat shit */
170 end
96f7e6e1
JW
171 `DECODE_LDRSTR: /* Single data transfer */
172 begin
173 read_0 = insn[19:16]; /* Rn */
174 read_1 = insn[3:0]; /* Rm */
6d0f9d82 175 read_2 = insn[15:12];
96f7e6e1 176
42c1e610 177 op0_out = regs0;
be64a9df 178 if(insn[25]) begin
42c1e610
JW
179 op1_out = {20'b0, insn[11:0]};
180 carry_out = incpsr[`CPSR_C];
bae77231 181 end else begin
42c1e610
JW
182 op1_out = shift_res;
183 carry_out = shift_cflag_out;
bae77231 184 end
6d0f9d82 185 op2_out = regs2;
bae77231 186 end
96f7e6e1
JW
187 `DECODE_LDMSTM: /* Block data transfer */
188 begin
189 read_0 = insn[19:16];
190
42c1e610
JW
191 op0_out = regs0;
192 op1_out = {16'b0, insn[15:0]};
bae77231 193 end
96f7e6e1
JW
194 `DECODE_BRANCH: /* Branch */
195 begin
42c1e610 196 op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231 197 end
96f7e6e1
JW
198 `DECODE_LDCSTC: /* Coprocessor data transfer */
199 begin
200 read_0 = insn[19:16];
201
42c1e610
JW
202 op0_out = regs0;
203 op1_out = {24'b0, insn[7:0]};
bae77231 204 end
96f7e6e1
JW
205 `DECODE_CDP: /* Coprocessor data op */
206 begin
bae77231 207 end
96f7e6e1
JW
208 `DECODE_MRCMCR: /* Coprocessor register transfer */
209 begin
210 read_0 = insn[15:12];
211
42c1e610 212 op0_out = regs0;
bae77231 213 end
96f7e6e1
JW
214 `DECODE_SWI: /* SWI */
215 begin
bae77231 216 end
96f7e6e1
JW
217 default:
218 $display("Undecoded instruction");
bae77231
CL
219 endcase
220 end
221
96f7e6e1 222
bae77231 223 always @ (posedge clk) begin
42c1e610
JW
224 op0 <= op0_out; /* Rn - always */
225 op1 <= op1_out; /* 'operand 2' - Rm */
226 op2 <= op2_out; /* thirdedge - Rs */
227 carry <= carry_out;
cb0428b6 228 outspsr <= inspsr;
bae77231
CL
229 end
230
231endmodule
232
e2c5d224 233module IREALLYHATEARMSHIFT(
bae77231
CL
234 input [31:0] insn,
235 input [31:0] operand,
236 input [31:0] reg_amt,
237 input cflag_in,
fbe84cc1
JW
238 output reg [31:0] res,
239 output reg cflag_out
bae77231 240);
bae77231 241 wire [5:0] shift_amt;
f61f8d6f
JW
242 reg is_arith, is_rot;
243 wire rshift_cout;
244 wire [31:0] rshift_res;
e2c5d224
CL
245
246 assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
247 : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231 248
96f7e6e1 249 SuckLessShifter barrel(.oper(operand),
e2c5d224
CL
250 .carryin(cflag_in),
251 .amt(shift_amt),
252 .is_arith(is_arith),
253 .is_rot(is_rot),
254 .res(rshift_res),
255 .carryout(rshift_cout));
bae77231 256
821617bb 257 always @(*)
e2c5d224
CL
258 case (insn[6:5])
259 `SHIFT_LSL: begin
e5fb7d86 260 /* meaningless */
e2c5d224
CL
261 is_rot = 1'b0;
262 is_arith = 1'b0;
26049339 263 end
e2c5d224
CL
264 `SHIFT_LSR: begin
265 is_rot = 1'b0;
266 is_arith = 1'b0;
267 end
268 `SHIFT_ASR: begin
269 is_rot = 1'b0;
270 is_arith = 1'b1;
271 end
272 `SHIFT_ROR: begin
273 is_rot = 1'b1;
274 is_arith = 1'b0;
275 end
276 endcase
277
821617bb 278 always @(*)
26049339 279 case (insn[6:5]) /* shift type */
e2c5d224
CL
280 `SHIFT_LSL:
281 {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231 282 `SHIFT_LSR: begin
e2c5d224
CL
283 res = rshift_res;
284 cflag_out = rshift_cout;
bae77231
CL
285 end
286 `SHIFT_ASR: begin
e2c5d224
CL
287 res = rshift_res;
288 cflag_out = rshift_cout;
bae77231
CL
289 end
290 `SHIFT_ROR: begin
e2c5d224 291 if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231
CL
292 res = {cflag_in, operand[31:1]};
293 cflag_out = operand[0];
e5fb7d86 294 end else begin
e2c5d224
CL
295 res = rshift_res;
296 cflag_out = rshift_cout;
bae77231
CL
297 end
298 end
26049339 299 endcase
bae77231 300endmodule
e2c5d224
CL
301
302module SuckLessShifter(
303 input [31:0] oper,
304 input carryin,
305 input [5:0] amt,
306 input is_arith,
307 input is_rot,
f61f8d6f
JW
308 output wire [31:0] res,
309 output wire carryout
e2c5d224
CL
310);
311
312 wire [32:0] stage1, stage2, stage3, stage4, stage5;
313
e5fb7d86 314 wire pushbits = is_arith & oper[31];
e2c5d224
CL
315
316 /* do a barrel shift */
317 assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
6c715b10
CL
318 assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
319 assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
320 assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
321 assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
322 assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
e2c5d224
CL
323
324endmodule
a0c8a75c
CL
325
326module SuckLessRotator(
327 input [31:0] oper,
328 input [3:0] amt,
f61f8d6f 329 output wire [31:0] res
a0c8a75c
CL
330);
331
332 wire [31:0] stage1, stage2, stage3;
333 assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
334 assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
335 assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
336 assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
337
338endmodule
96f7e6e1 339
This page took 0.067533 seconds and 4 git commands to generate.