Nicer dump information.
[firearm.git] / Decode.v
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26049339
CL
1`include "ARM_Constants.v"
2
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3module Decode(
4 input clk,
be64a9df 5 input [31:0] insn,
bae77231 6 input [31:0] inpc,
821617bb 7 input [31:0] incpsr,
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8 output reg [31:0] op0,
9 output reg [31:0] op1,
10 output reg [31:0] op2,
821617bb 11 output reg [31:0] outcpsr,
bae77231 12
821617bb
JW
13 output [3:0] read_0,
14 output [3:0] read_1,
15 output [3:0] read_2,
16 input [31:0] rdata_0,
17 input [31:0] rdata_1,
18 input [31:0] rdata_2
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19 );
20
21 wire [31:0] regs0, regs1, regs2, rpc;
821617bb 22 wire [31:0] op1_res, cpsr;
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23
24 /* shifter stuff */
25 wire [31:0] shift_oper;
26 wire [31:0] shift_res;
27 wire shift_cflag_out;
28
821617bb
JW
29 assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
30 assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
31 assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231 32
be64a9df 33 IHATEARMSHIFT blowme(.insn(insn),
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34 .operand(regs1),
35 .reg_amt(regs2),
821617bb 36 .cflag_in(incpsr[`CPSR_C]),
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37 .res(shift_res),
38 .cflag_out(shift_cflag_out));
be64a9df
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39
40 always @(*)
41 casez (insn)
42 32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
43// 32'b????00001???????????????1001????, /* Multiply long */
44 32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
45 32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
46 32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
47 32'b????00010?00????????00001001????, /* Atomic swap */
48 32'b????000100101111111111110001????, /* Branch */
49 32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
50 32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
51 32'b????011????????????????????1????, /* Undefined. I hate ARM */
52 32'b????01??????????????????????????, /* Single data transfer */
53 32'b????100?????????????????????????, /* Block data transfer */
54 32'b????101?????????????????????????, /* Branch */
55 32'b????110?????????????????????????, /* Coprocessor data transfer */
56 32'b????1110???????????????????0????, /* Coprocessor data op */
57 32'b????1110???????????????????1????, /* Coprocessor register transfer */
58 32'b????1111????????????????????????: /* SWI */
59 rpc = inpc - 8;
60 32'b????00??????????????????????????: /* ALU */
61 rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
62 default: /* X everything else out */
63 rpc = 32'hxxxxxxxx;
64 endcase
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65
66 always @ (*) begin
be64a9df 67 casez (insn)
bae77231 68 32'b????000000??????????????1001????: begin /* Multiply */
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JW
69 read_0 = insn[15:12]; /* Rn */
70 read_1 = insn[3:0]; /* Rm */
71 read_2 = insn[11:8]; /* Rs */
bae77231 72 op1_res = regs1;
821617bb 73 cpsr = incpsr;
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74 end
75/*
76 32'b????00001???????????????1001????: begin * Multiply long *
821617bb
JW
77 read_0 = insn[11:8]; * Rn *
78 read_1 = insn[3:0]; * Rm *
79 read_2 = 4'b0; * anyus *
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80 op1_res = regs1;
81 end
82*/
83 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
821617bb 84 cpsr = incpsr;
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85 end
86 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
821617bb 87 cpsr = incpsr;
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88 end
89 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
821617bb 90 cpsr = incpsr;
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91 end
92 32'b????00??????????????????????????: begin /* ALU */
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JW
93 read_0 = insn[19:16]; /* Rn */
94 read_1 = insn[3:0]; /* Rm */
95 read_2 = insn[11:8]; /* Rs for shift */
be64a9df 96 if(insn[25]) begin /* the constant case */
821617bb 97 cpsr = incpsr;
be64a9df 98 op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
bae77231 99 end else begin
821617bb 100 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
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101 op1_res = shift_res;
102 end
103 end
104 32'b????00010?00????????00001001????: begin /* Atomic swap */
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JW
105 read_0 = insn[19:16]; /* Rn */
106 read_1 = insn[3:0]; /* Rm */
107 read_2 = 4'b0; /* anyus */
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108 op1_res = regs1;
109 end
110 32'b????000100101111111111110001????: begin /* Branch and exchange */
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JW
111 read_0 = insn[3:0]; /* Rn */
112 cpsr = incpsr;
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113 end
114 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
821617bb
JW
115 read_0 = insn[19:16];
116 read_1 = insn[3:0];
117 read_2 = 4'b0;
bae77231 118 op1_res = regs1;
821617bb 119 cpsr = incpsr;
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120 end
121 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
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JW
122 read_0 = insn[19:16];
123 read_1 = insn[3:0];
be64a9df 124 op1_res = {24'b0, insn[11:8], insn[3:0]};
821617bb 125 cpsr = incpsr;
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126 end
127 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
128 /* eat shit */
129 end
130 32'b????01??????????????????????????: begin /* Single data transfer */
821617bb
JW
131 read_0 = insn[19:16]; /* Rn */
132 read_1 = insn[3:0]; /* Rm */
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133 if(insn[25]) begin
134 op1_res = {20'b0, insn[11:0]};
821617bb 135 cpsr = incpsr;
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136 end else begin
137 op1_res = shift_res;
821617bb 138 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
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139 end
140 end
141 32'b????100?????????????????????????: begin /* Block data transfer */
821617bb 142 read_0 = insn[19:16];
be64a9df 143 op1_res = {16'b0, insn[15:0]};
821617bb 144 cpsr = incpsr;
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145 end
146 32'b????101?????????????????????????: begin /* Branch */
be64a9df 147 op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
821617bb 148 cpsr = incpsr;
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149 end
150 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
821617bb 151 read_0 = insn[19:16];
be64a9df 152 op1_res = {24'b0, insn[7:0]};
821617bb 153 cpsr = incpsr;
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154 end
155 32'b????1110???????????????????0????: begin /* Coprocessor data op */
821617bb 156 cpsr = incpsr;
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157 end
158 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
821617bb 159 cpsr = incpsr;
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160 end
161 32'b????1111????????????????????????: begin /* SWI */
821617bb 162 cpsr = incpsr;
bae77231 163 end
26049339 164 default: begin end
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165 endcase
166 end
167
168 always @ (posedge clk) begin
169 op0 <= regs0; /* Rn - always */
170 op1 <= op1_res; /* 'operand 2' - Rm */
171 op2 <= regs2; /* thirdedge - Rs */
821617bb 172 outcpsr <= cpsr;
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173 end
174
175endmodule
176
177module IHATEARMSHIFT(
178 input [31:0] insn,
179 input [31:0] operand,
180 input [31:0] reg_amt,
181 input cflag_in,
182 output [31:0] res,
183 output cflag_out
184);
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185 wire [5:0] shift_amt;
186 wire elanus;
187
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188
189 /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
821617bb 190 always @(*)
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191 if(insn[4]) begin
192 shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
193 elanus = 1'b1;
194 end else begin
195 shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
196 elanus = 1'b0;
197 end
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JW
198
199 always @(*)
26049339 200 case (insn[6:5]) /* shift type */
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201 `SHIFT_LSL: begin
202 {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
203 end
204 `SHIFT_LSR: begin
205 {res, cflag_out} = {operand, cflag_in} >> shift_amt;
206 end
207 `SHIFT_ASR: begin
208 {res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
209 end
210 `SHIFT_ROR: begin
211 if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
212 res = {cflag_in, operand[31:1]};
213 cflag_out = operand[0];
26049339 214 end else if(shift_amt == 6'b0) begin
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215 res = operand;
216 cflag_out = cflag_in;
217 end else begin
218 res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]);
219 cflag_out = operand[shift_amt[4:0] - 5'b1];
220 end
221 end
26049339 222 endcase
bae77231 223endmodule
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