Merge nyus:/storage/git/firearm
[firearm.git] / Decode.v
CommitLineData
26049339
CL
1`include "ARM_Constants.v"
2
bae77231
CL
3module Decode(
4 input clk,
be64a9df 5 input [31:0] insn,
bae77231 6 input [31:0] inpc,
821617bb 7 input [31:0] incpsr,
cb0428b6 8 input [31:0] inspsr,
bae77231
CL
9 output reg [31:0] op0,
10 output reg [31:0] op1,
11 output reg [31:0] op2,
42c1e610 12 output reg carry,
ab7ee9fc 13 output reg [31:0] outcpsr,
cb0428b6 14 output reg [31:0] outspsr,
bae77231 15
fbe84cc1
JW
16 output reg [3:0] read_0,
17 output reg [3:0] read_1,
18 output reg [3:0] read_2,
821617bb
JW
19 input [31:0] rdata_0,
20 input [31:0] rdata_1,
21 input [31:0] rdata_2
bae77231
CL
22 );
23
fbe84cc1
JW
24 wire [31:0] regs0, regs1, regs2;
25 reg [31:0] rpc;
26 reg [31:0] op0_out, op1_out, op2_out;
27 reg carry_out;
bae77231
CL
28
29 /* shifter stuff */
30 wire [31:0] shift_oper;
31 wire [31:0] shift_res;
32 wire shift_cflag_out;
a0c8a75c 33 wire [31:0] rotate_res;
bae77231 34
821617bb
JW
35 assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
36 assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
37 assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231 38
96f7e6e1
JW
39 IREALLYHATEARMSHIFT shift(.insn(insn),
40 .operand(regs1),
41 .reg_amt(regs2),
42 .cflag_in(incpsr[`CPSR_C]),
43 .res(shift_res),
44 .cflag_out(shift_cflag_out));
e2c5d224 45
a0c8a75c
CL
46 SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
47 .amt(insn[11:8]),
48 .res(rotate_res));
49
be64a9df
JW
50 always @(*)
51 casez (insn)
2c523f8a
JW
52 `DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
53// `DECODE_ALU_MUL_LONG, /* Multiply long */
54 `DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
55 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
56 `DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
57 `DECODE_ALU_SWP, /* Atomic swap */
58 `DECODE_ALU_BX, /* Branch and exchange */
59 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
60 `DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
61 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
62 `DECODE_LDRSTR, /* Single data transfer */
63 `DECODE_LDMSTM, /* Block data transfer */
64 `DECODE_BRANCH, /* Branch */
65 `DECODE_LDCSTC, /* Coprocessor data transfer */
66 `DECODE_CDP, /* Coprocessor data op */
2c523f8a 67 `DECODE_SWI: /* SWI */
b3bb2fb8 68 rpc = inpc + 8;
04d95cf5
JW
69 `DECODE_MRCMCR: /* Coprocessor register transfer */
70 rpc = inpc + 12;
2c523f8a 71 `DECODE_ALU: /* ALU */
b3bb2fb8 72 rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
2c523f8a 73 default: /* X everything else out */
be64a9df
JW
74 rpc = 32'hxxxxxxxx;
75 endcase
96f7e6e1 76
326fd4c3
JW
77 always @(*) begin
78 read_0 = 4'hx;
79 read_1 = 4'hx;
80 read_2 = 4'hx;
81
96f7e6e1
JW
82 op0_out = 32'hxxxxxxxx;
83 op1_out = 32'hxxxxxxxx;
84 op2_out = 32'hxxxxxxxx;
85 carry_out = 1'bx;
86
0bc7ede9 87 casez (insn)
2c523f8a 88 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3 89 begin
0bc7ede9 90 read_0 = insn[15:12]; /* Rn */
326fd4c3
JW
91 read_1 = insn[3:0]; /* Rm */
92 read_2 = insn[11:8]; /* Rs */
96f7e6e1
JW
93
94 op0_out = regs0;
95 op1_out = regs1;
96 op2_out = regs2;
326fd4c3 97 end
2c523f8a 98// `DECODE_ALU_MUL_LONG: /* Multiply long */
96f7e6e1 99// begin
0bc7ede9 100// read_0 = insn[11:8]; /* Rn */
326fd4c3
JW
101// read_1 = insn[3:0]; /* Rm */
102// read_2 = 4'b0; /* anyus */
96f7e6e1
JW
103//
104// op1_res = regs1;
105// end
2c523f8a 106 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
42c1e610 107 begin end
96f7e6e1
JW
108 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
109 begin
110 read_0 = insn[3:0]; /* Rm */
111
112 op0_out = regs0;
113 end
2c523f8a 114 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
96f7e6e1 115 begin
42c1e610 116 read_0 = insn[3:0]; /* Rm */
96f7e6e1
JW
117
118 if(insn[25]) begin /* the constant case */
119 op0_out = rotate_res;
120 end else begin
121 op0_out = regs0;
122 end
123 end
2c523f8a 124 `DECODE_ALU_SWP: /* Atomic swap */
326fd4c3 125 begin
0bc7ede9 126 read_0 = insn[19:16]; /* Rn */
326fd4c3 127 read_1 = insn[3:0]; /* Rm */
96f7e6e1
JW
128
129 op0_out = regs0;
130 op1_out = regs1;
326fd4c3 131 end
2c523f8a 132 `DECODE_ALU_BX: /* Branch and exchange */
96f7e6e1 133 begin
0bc7ede9 134 read_0 = insn[3:0]; /* Rn */
96f7e6e1
JW
135
136 op0_out = regs0;
137 end
2c523f8a 138 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
326fd4c3 139 begin
0bc7ede9 140 read_0 = insn[19:16];
326fd4c3 141 read_1 = insn[3:0];
778ef14f
CL
142 read_2 = insn[15:12];
143
96f7e6e1
JW
144 op0_out = regs0;
145 op1_out = regs1;
778ef14f 146 op2_out = regs2;
326fd4c3 147 end
2c523f8a 148 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
326fd4c3 149 begin
0bc7ede9 150 read_0 = insn[19:16];
778ef14f 151 read_1 = insn[15:12];
96f7e6e1
JW
152
153 op0_out = regs0;
154 op1_out = {24'b0, insn[11:8], insn[3:0]};
778ef14f 155 op2_out = regs1;
326fd4c3 156 end
2c523f8a
JW
157 `DECODE_ALU: /* ALU */
158 begin
159 read_0 = insn[19:16]; /* Rn */
160 read_1 = insn[3:0]; /* Rm */
161 read_2 = insn[11:8]; /* Rs for shift */
96f7e6e1 162
2c523f8a
JW
163 op0_out = regs0;
164 if(insn[25]) begin /* the constant case */
165 carry_out = incpsr[`CPSR_C];
166 op1_out = rotate_res;
167 end else begin
168 carry_out = shift_cflag_out;
169 op1_out = shift_res;
170 end
171 end
96f7e6e1
JW
172 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
173 begin
bae77231
CL
174 /* eat shit */
175 end
96f7e6e1
JW
176 `DECODE_LDRSTR: /* Single data transfer */
177 begin
178 read_0 = insn[19:16]; /* Rn */
179 read_1 = insn[3:0]; /* Rm */
6d0f9d82 180 read_2 = insn[15:12];
96f7e6e1 181
42c1e610 182 op0_out = regs0;
be64a9df 183 if(insn[25]) begin
42c1e610
JW
184 op1_out = {20'b0, insn[11:0]};
185 carry_out = incpsr[`CPSR_C];
bae77231 186 end else begin
42c1e610
JW
187 op1_out = shift_res;
188 carry_out = shift_cflag_out;
bae77231 189 end
6d0f9d82 190 op2_out = regs2;
bae77231 191 end
96f7e6e1
JW
192 `DECODE_LDMSTM: /* Block data transfer */
193 begin
194 read_0 = insn[19:16];
195
42c1e610
JW
196 op0_out = regs0;
197 op1_out = {16'b0, insn[15:0]};
bae77231 198 end
96f7e6e1
JW
199 `DECODE_BRANCH: /* Branch */
200 begin
42c1e610 201 op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231 202 end
96f7e6e1
JW
203 `DECODE_LDCSTC: /* Coprocessor data transfer */
204 begin
205 read_0 = insn[19:16];
206
42c1e610
JW
207 op0_out = regs0;
208 op1_out = {24'b0, insn[7:0]};
bae77231 209 end
96f7e6e1
JW
210 `DECODE_CDP: /* Coprocessor data op */
211 begin
bae77231 212 end
96f7e6e1
JW
213 `DECODE_MRCMCR: /* Coprocessor register transfer */
214 begin
215 read_0 = insn[15:12];
216
42c1e610 217 op0_out = regs0;
bae77231 218 end
96f7e6e1
JW
219 `DECODE_SWI: /* SWI */
220 begin
bae77231 221 end
96f7e6e1
JW
222 default:
223 $display("Undecoded instruction");
bae77231
CL
224 endcase
225 end
226
96f7e6e1 227
bae77231 228 always @ (posedge clk) begin
42c1e610
JW
229 op0 <= op0_out; /* Rn - always */
230 op1 <= op1_out; /* 'operand 2' - Rm */
231 op2 <= op2_out; /* thirdedge - Rs */
232 carry <= carry_out;
ab7ee9fc 233 outcpsr <= incpsr;
cb0428b6 234 outspsr <= inspsr;
bae77231
CL
235 end
236
237endmodule
238
e2c5d224 239module IREALLYHATEARMSHIFT(
bae77231
CL
240 input [31:0] insn,
241 input [31:0] operand,
242 input [31:0] reg_amt,
243 input cflag_in,
fbe84cc1
JW
244 output reg [31:0] res,
245 output reg cflag_out
bae77231 246);
bae77231 247 wire [5:0] shift_amt;
f61f8d6f
JW
248 reg is_arith, is_rot;
249 wire rshift_cout;
250 wire [31:0] rshift_res;
e2c5d224
CL
251
252 assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
253 : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231 254
96f7e6e1 255 SuckLessShifter barrel(.oper(operand),
e2c5d224
CL
256 .carryin(cflag_in),
257 .amt(shift_amt),
258 .is_arith(is_arith),
259 .is_rot(is_rot),
260 .res(rshift_res),
261 .carryout(rshift_cout));
bae77231 262
821617bb 263 always @(*)
e2c5d224
CL
264 case (insn[6:5])
265 `SHIFT_LSL: begin
e5fb7d86 266 /* meaningless */
e2c5d224
CL
267 is_rot = 1'b0;
268 is_arith = 1'b0;
26049339 269 end
e2c5d224
CL
270 `SHIFT_LSR: begin
271 is_rot = 1'b0;
272 is_arith = 1'b0;
273 end
274 `SHIFT_ASR: begin
275 is_rot = 1'b0;
276 is_arith = 1'b1;
277 end
278 `SHIFT_ROR: begin
279 is_rot = 1'b1;
280 is_arith = 1'b0;
281 end
282 endcase
283
821617bb 284 always @(*)
26049339 285 case (insn[6:5]) /* shift type */
e2c5d224
CL
286 `SHIFT_LSL:
287 {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231 288 `SHIFT_LSR: begin
e2c5d224
CL
289 res = rshift_res;
290 cflag_out = rshift_cout;
bae77231
CL
291 end
292 `SHIFT_ASR: begin
e2c5d224
CL
293 res = rshift_res;
294 cflag_out = rshift_cout;
bae77231
CL
295 end
296 `SHIFT_ROR: begin
e2c5d224 297 if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231
CL
298 res = {cflag_in, operand[31:1]};
299 cflag_out = operand[0];
e5fb7d86 300 end else begin
e2c5d224
CL
301 res = rshift_res;
302 cflag_out = rshift_cout;
bae77231
CL
303 end
304 end
26049339 305 endcase
bae77231 306endmodule
e2c5d224
CL
307
308module SuckLessShifter(
309 input [31:0] oper,
310 input carryin,
311 input [5:0] amt,
312 input is_arith,
313 input is_rot,
f61f8d6f
JW
314 output wire [31:0] res,
315 output wire carryout
e2c5d224
CL
316);
317
318 wire [32:0] stage1, stage2, stage3, stage4, stage5;
319
e5fb7d86 320 wire pushbits = is_arith & oper[31];
e2c5d224
CL
321
322 /* do a barrel shift */
323 assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
6c715b10
CL
324 assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
325 assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
326 assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
327 assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
328 assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
e2c5d224
CL
329
330endmodule
a0c8a75c
CL
331
332module SuckLessRotator(
333 input [31:0] oper,
334 input [3:0] amt,
f61f8d6f 335 output wire [31:0] res
a0c8a75c
CL
336);
337
338 wire [31:0] stage1, stage2, stage3;
339 assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
340 assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
341 assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
342 assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
343
344endmodule
96f7e6e1 345
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