[firearm.git] / Decode.v

`include "ARM_Constants.v"

module Decode(
	input clk,
	input [31:0] insn,
	input [31:0] inpc,
	input [31:0] incpsr,
	output reg [31:0] op0,
	output reg [31:0] op1,
	output reg [31:0] op2,
	output reg [31:0] outcpsr,

	output [3:0] read_0,
	output [3:0] read_1,
	output [3:0] read_2,
	input [31:0] rdata_0,
	input [31:0] rdata_1,
	input [31:0] rdata_2
	);

	wire [31:0] regs0, regs1, regs2, rpc;
	wire [31:0] op1_res, cpsr;

	/* shifter stuff */
	wire [31:0] shift_oper;
	wire [31:0] shift_res;
	wire shift_cflag_out;

	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */

	IHATEARMSHIFT blowme(.insn(insn),
	                     .operand(regs1),
	                     .reg_amt(regs2),
	                     .cflag_in(incpsr[`CPSR_C]),
	                     .res(shift_res),
	                     .cflag_out(shift_cflag_out));
	
	always @(*)
		casez (insn)
		32'b????000000??????????????1001????,	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
//		32'b????00001???????????????1001????,	/* Multiply long */
		32'b????00010?001111????000000000000,	/* MRS (Transfer PSR to register) */
		32'b????00010?101001111100000000????,	/* MSR (Transfer register to PSR) */
		32'b????00?10?1010001111????????????,	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		32'b????00010?00????????00001001????,	/* Atomic swap */
		32'b????000100101111111111110001????,	/* Branch and exchange */
		32'b????000??0??????????00001??1????,	/* Halfword transfer - register offset */
		32'b????000??1??????????00001??1????,	/* Halfword transfer - register offset */
		32'b????011????????????????????1????,	/* Undefined. I hate ARM */
		32'b????01??????????????????????????,	/* Single data transfer */
		32'b????100?????????????????????????,	/* Block data transfer */
		32'b????101?????????????????????????,	/* Branch */
		32'b????110?????????????????????????,	/* Coprocessor data transfer */
		32'b????1110???????????????????0????,	/* Coprocessor data op */
		32'b????1110???????????????????1????,	/* Coprocessor register transfer */
		32'b????1111????????????????????????:	/* SWI */
			rpc = inpc - 8;
		32'b????00??????????????????????????:	/* ALU */
			rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
		default:				/* X everything else out */
			rpc = 32'hxxxxxxxx;
		endcase

	always @(*) begin
		read_0 = 4'hx;
		read_1 = 4'hx;
		read_2 = 4'hx;
		
		casez (insn)
		32'b????000000??????????????1001????:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			read_0 = insn[15:12]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs */
		end
//		32'b????00001???????????????1001????,	/* Multiply long */
//			read_0 = insn[11:8]; /* Rn */
//			read_1 = insn[3:0];   /* Rm */
//			read_2 = 4'b0;       /* anyus */
		32'b????00010?001111????000000000000,	/* MRS (Transfer PSR to register) */
		32'b????00010?101001111100000000????,	/* MSR (Transfer register to PSR) */
		32'b????00?10?1010001111????????????:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		begin end	/* Everything stays x'ed out. */
		32'b????00??????????????????????????:	/* ALU */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs for shift */
		end
		32'b????00010?00????????00001001????:	/* Atomic swap */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
		end
		32'b????000100101111111111110001????:	/* Branch and exchange */
			read_0 = insn[3:0];   /* Rn */
		32'b????000??0??????????00001??1????:	/* Halfword transfer - register offset */
		begin
			read_0 = insn[19:16];
			read_1 = insn[3:0];
		end
		32'b????000??1??????????00001??1????:	/* Halfword transfer - immediate offset */
		begin
			read_0 = insn[19:16];
			read_1 = insn[3:0];
		end
		32'b????011????????????????????1????:	/* Undefined. I hate ARM */
		begin end
		32'b????01??????????????????????????:	/* Single data transfer */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
		end
		32'b????100?????????????????????????:	/* Block data transfer */
			read_0 = insn[19:16];
		32'b????101?????????????????????????:	/* Branch */
		begin end
		32'b????110?????????????????????????:	/* Coprocessor data transfer */
			read_0 = insn[19:16];
		32'b????1110???????????????????0????,	/* Coprocessor data op */
		32'b????1110???????????????????1????,	/* Coprocessor register transfer */
		32'b????1111????????????????????????:	/* SWI */
		begin end
		default:
			$display("Undecoded instruction");
		endcase
	end
	
	always @(*) begin
		op1_res = 32'hxxxxxxxx;
		cpsr = 32'hxxxxxxxx;
		casez (insn)
		32'b????000000??????????????1001????: begin /* Multiply */
			op1_res = regs1;
			cpsr = incpsr;
		end
//		32'b????00001???????????????1001????: begin /* Multiply long */
//			op1_res = regs1;
//		end
		32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
			cpsr = incpsr;
		end
        	32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
			cpsr = incpsr;
        	end
                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
			cpsr = incpsr;
                end
		32'b????00??????????????????????????: begin /* ALU */
			if(insn[25]) begin     /* the constant case */
				cpsr = incpsr;
				op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
			end else begin
				cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
				op1_res = shift_res;
			end
		end
		32'b????00010?00????????00001001????: begin /* Atomic swap */
			op1_res = regs1;
		end
		32'b????000100101111111111110001????: begin /* Branch and exchange */
			cpsr = incpsr;
		end
		32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
			op1_res = regs1;
			cpsr = incpsr;
		end
		32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
			op1_res = {24'b0, insn[11:8], insn[3:0]};
			cpsr = incpsr;
		end
		32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
			/* eat shit */
		end
		32'b????01??????????????????????????: begin /* Single data transfer */
			if(insn[25]) begin
				op1_res = {20'b0, insn[11:0]};
				cpsr = incpsr;
			end else begin
				op1_res = shift_res;
				cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
			end
		end
		32'b????100?????????????????????????: begin /* Block data transfer */
			op1_res = {16'b0, insn[15:0]};
			cpsr = incpsr;
		end
		32'b????101?????????????????????????: begin /* Branch */
			op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
			cpsr = incpsr;
		end
		32'b????110?????????????????????????: begin /* Coprocessor data transfer */
			op1_res = {24'b0, insn[7:0]};
			cpsr = incpsr;
		end
		32'b????1110???????????????????0????: begin /* Coprocessor data op */
			cpsr = incpsr;
		end
		32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
			cpsr = incpsr;
		end
		32'b????1111????????????????????????: begin /* SWI */
			cpsr = incpsr;
		end
		default: begin end
		endcase
	end

	always @ (posedge clk) begin
		op0 <= regs0;   /* Rn - always */
		op1 <= op1_res; /* 'operand 2' - Rm */
		op2 <= regs2;   /* thirdedge - Rs */
		outcpsr <= cpsr;
	end

endmodule

module IHATEARMSHIFT(
	input [31:0] insn,
	input [31:0] operand,
	input [31:0] reg_amt,
	input cflag_in,
	output [31:0] res,
	output cflag_out
);
	wire [5:0] shift_amt;
	wire elanus;


	/* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
	always @(*)
		if(insn[4]) begin
			shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
			elanus = 1'b1;
		end else begin
			shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
			elanus = 1'b0;
		end
	
	always @(*)
		case (insn[6:5]) /* shift type */
		`SHIFT_LSL: begin
			{cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
		end
		`SHIFT_LSR: begin
			{res, cflag_out} = {operand, cflag_in} >> shift_amt;
		end
		`SHIFT_ASR: begin
			{res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
		end
		`SHIFT_ROR: begin
			if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
				res = {cflag_in, operand[31:1]};
				cflag_out = operand[0];
			end else if(shift_amt == 6'b0) begin
				res = operand;
				cflag_out = cflag_in;
			end else begin
				res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]);
				cflag_out = operand[shift_amt[4:0] - 5'b1];
			end
		end
		endcase
endmodule
Commit	Line	Data
26049339 CL	1	`include "ARM_Constants.v"
26049339 CL	2
bae77231 CL	3	module Decode(
bae77231 CL	4	input clk,
be64a9df	5	input [31:0] insn,
bae77231	6	input [31:0] inpc,
821617bb	7	input [31:0] incpsr,
bae77231 CL	8	output reg [31:0] op0,
	9	output reg [31:0] op1,
	10	output reg [31:0] op2,
821617bb	11	output reg [31:0] outcpsr,
bae77231	12
821617bb JW	13	output [3:0] read_0,
	14	output [3:0] read_1,
	15	output [3:0] read_2,
	16	input [31:0] rdata_0,
	17	input [31:0] rdata_1,
	18	input [31:0] rdata_2
bae77231 CL	19	);
	20
	21	wire [31:0] regs0, regs1, regs2, rpc;
821617bb	22	wire [31:0] op1_res, cpsr;
bae77231 CL	23
	24	/* shifter stuff */
	25	wire [31:0] shift_oper;
	26	wire [31:0] shift_res;
	27	wire shift_cflag_out;
	28
821617bb JW	29	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	30	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	31	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231	32
be64a9df	33	IHATEARMSHIFT blowme(.insn(insn),
26049339 CL	34	.operand(regs1),
26049339 CL	35	.reg_amt(regs2),
821617bb	36	.cflag_in(incpsr[`CPSR_C]),
26049339 CL	37	.res(shift_res),
26049339 CL	38	.cflag_out(shift_cflag_out));
be64a9df JW	39
	40	always @(*)
	41	casez (insn)
	42	32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	43	// 32'b????00001???????????????1001????, /* Multiply long */
	44	32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
	45	32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
	46	32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
	47	32'b????00010?00????????00001001????, /* Atomic swap */
0bc7ede9	48	32'b????000100101111111111110001????, /* Branch and exchange */
be64a9df JW	49	32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
	50	32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
	51	32'b????011????????????????????1????, /* Undefined. I hate ARM */
	52	32'b????01??????????????????????????, /* Single data transfer */
	53	32'b????100?????????????????????????, /* Block data transfer */
	54	32'b????101?????????????????????????, /* Branch */
	55	32'b????110?????????????????????????, /* Coprocessor data transfer */
	56	32'b????1110???????????????????0????, /* Coprocessor data op */
	57	32'b????1110???????????????????1????, /* Coprocessor register transfer */
	58	32'b????1111????????????????????????: /* SWI */
	59	rpc = inpc - 8;
	60	32'b????00??????????????????????????: /* ALU */
	61	rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
	62	default: /* X everything else out */
	63	rpc = 32'hxxxxxxxx;
	64	endcase
bae77231	65
326fd4c3 JW	66	always @(*) begin
	67	read_0 = 4'hx;
	68	read_1 = 4'hx;
	69	read_2 = 4'hx;
	70
0bc7ede9 JW	71	casez (insn)
0bc7ede9 JW	72	32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3	73	begin
0bc7ede9	74	read_0 = insn[15:12]; /* Rn */
326fd4c3 JW	75	read_1 = insn[3:0]; /* Rm */
	76	read_2 = insn[11:8]; /* Rs */
	77	end
0bc7ede9 JW	78	// 32'b????00001???????????????1001????, /* Multiply long */
0bc7ede9 JW	79	// read_0 = insn[11:8]; /* Rn */
326fd4c3 JW	80	// read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	81	// read_2 = 4'b0; /* anyus */
0bc7ede9 JW	82	32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
	83	32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
	84	32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
326fd4c3	85	begin end /* Everything stays x'ed out. */
0bc7ede9	86	32'b????00??????????????????????????: /* ALU */
326fd4c3	87	begin
0bc7ede9	88	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	89	read_1 = insn[3:0]; /* Rm */
	90	read_2 = insn[11:8]; /* Rs for shift */
	91	end
0bc7ede9	92	32'b????00010?00????????00001001????: /* Atomic swap */
326fd4c3	93	begin
0bc7ede9	94	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	95	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	96	end
0bc7ede9 JW	97	32'b????000100101111111111110001????: /* Branch and exchange */
	98	read_0 = insn[3:0]; /* Rn */
	99	32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
326fd4c3	100	begin
0bc7ede9	101	read_0 = insn[19:16];
326fd4c3 JW	102	read_1 = insn[3:0];
	103	end
	104	32'b????000??1??????????00001??1????: /* Halfword transfer - immediate offset */
	105	begin
0bc7ede9	106	read_0 = insn[19:16];
326fd4c3 JW	107	read_1 = insn[3:0];
326fd4c3 JW	108	end
0bc7ede9	109	32'b????011????????????????????1????: /* Undefined. I hate ARM */
326fd4c3	110	begin end
0bc7ede9	111	32'b????01??????????????????????????: /* Single data transfer */
326fd4c3	112	begin
0bc7ede9	113	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	114	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	115	end
0bc7ede9 JW	116	32'b????100?????????????????????????: /* Block data transfer */
	117	read_0 = insn[19:16];
	118	32'b????101?????????????????????????: /* Branch */
326fd4c3	119	begin end
0bc7ede9 JW	120	32'b????110?????????????????????????: /* Coprocessor data transfer */
	121	read_0 = insn[19:16];
	122	32'b????1110???????????????????0????, /* Coprocessor data op */
	123	32'b????1110???????????????????1????, /* Coprocessor register transfer */
	124	32'b????1111????????????????????????: /* SWI */
326fd4c3	125	begin end
b215c5ff	126	default:
326fd4c3	127	$display("Undecoded instruction");
b215c5ff	128	endcase
326fd4c3	129	end
b215c5ff	130
326fd4c3	131	always @(*) begin
b215c5ff JW	132	op1_res = 32'hxxxxxxxx;
b215c5ff JW	133	cpsr = 32'hxxxxxxxx;
be64a9df	134	casez (insn)
bae77231	135	32'b????000000??????????????1001????: begin /* Multiply */
bae77231	136	op1_res = regs1;
821617bb	137	cpsr = incpsr;
bae77231	138	end
b215c5ff JW	139	// 32'b????00001???????????????1001????: begin /* Multiply long */
	140	// op1_res = regs1;
	141	// end
bae77231	142	32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
821617bb	143	cpsr = incpsr;
bae77231 CL	144	end
bae77231 CL	145	32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
821617bb	146	cpsr = incpsr;
bae77231 CL	147	end
bae77231 CL	148	32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
821617bb	149	cpsr = incpsr;
bae77231 CL	150	end
bae77231 CL	151	32'b????00??????????????????????????: begin /* ALU */
be64a9df	152	if(insn[25]) begin /* the constant case */
821617bb	153	cpsr = incpsr;
be64a9df	154	op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) \| ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
bae77231	155	end else begin
821617bb	156	cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
bae77231 CL	157	op1_res = shift_res;
	158	end
	159	end
	160	32'b????00010?00????????00001001????: begin /* Atomic swap */
bae77231 CL	161	op1_res = regs1;
	162	end
	163	32'b????000100101111111111110001????: begin /* Branch and exchange */
821617bb	164	cpsr = incpsr;
bae77231 CL	165	end
bae77231 CL	166	32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
bae77231	167	op1_res = regs1;
821617bb	168	cpsr = incpsr;
bae77231 CL	169	end
bae77231 CL	170	32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
be64a9df	171	op1_res = {24'b0, insn[11:8], insn[3:0]};
821617bb	172	cpsr = incpsr;
bae77231 CL	173	end
	174	32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
	175	/* eat shit */
	176	end
	177	32'b????01??????????????????????????: begin /* Single data transfer */
be64a9df JW	178	if(insn[25]) begin
be64a9df JW	179	op1_res = {20'b0, insn[11:0]};
821617bb	180	cpsr = incpsr;
bae77231 CL	181	end else begin
bae77231 CL	182	op1_res = shift_res;
821617bb	183	cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
bae77231 CL	184	end
	185	end
	186	32'b????100?????????????????????????: begin /* Block data transfer */
be64a9df	187	op1_res = {16'b0, insn[15:0]};
821617bb	188	cpsr = incpsr;
bae77231 CL	189	end
bae77231 CL	190	32'b????101?????????????????????????: begin /* Branch */
be64a9df	191	op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
821617bb	192	cpsr = incpsr;
bae77231 CL	193	end
bae77231 CL	194	32'b????110?????????????????????????: begin /* Coprocessor data transfer */
be64a9df	195	op1_res = {24'b0, insn[7:0]};
821617bb	196	cpsr = incpsr;
bae77231 CL	197	end
bae77231 CL	198	32'b????1110???????????????????0????: begin /* Coprocessor data op */
821617bb	199	cpsr = incpsr;
bae77231 CL	200	end
bae77231 CL	201	32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
821617bb	202	cpsr = incpsr;
bae77231 CL	203	end
bae77231 CL	204	32'b????1111????????????????????????: begin /* SWI */
821617bb	205	cpsr = incpsr;
bae77231	206	end
26049339	207	default: begin end
bae77231 CL	208	endcase
	209	end
	210
	211	always @ (posedge clk) begin
	212	op0 <= regs0; /* Rn - always */
	213	op1 <= op1_res; /* 'operand 2' - Rm */
	214	op2 <= regs2; /* thirdedge - Rs */
821617bb	215	outcpsr <= cpsr;
bae77231 CL	216	end
	217
	218	endmodule
	219
	220	module IHATEARMSHIFT(
	221	input [31:0] insn,
	222	input [31:0] operand,
	223	input [31:0] reg_amt,
	224	input cflag_in,
	225	output [31:0] res,
	226	output cflag_out
	227	);
bae77231 CL	228	wire [5:0] shift_amt;
	229	wire elanus;
	230
bae77231 CL	231
bae77231 CL	232	/* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
821617bb	233	always @(*)
26049339 CL	234	if(insn[4]) begin
	235	shift_amt = {\|reg_amt[7:5], reg_amt[4:0]};
	236	elanus = 1'b1;
	237	end else begin
	238	shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
	239	elanus = 1'b0;
	240	end
821617bb JW	241
821617bb JW	242	always @(*)
26049339	243	case (insn[6:5]) /* shift type */
bae77231 CL	244	`SHIFT_LSL: begin
	245	{cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
	246	end
	247	`SHIFT_LSR: begin
	248	{res, cflag_out} = {operand, cflag_in} >> shift_amt;
	249	end
	250	`SHIFT_ASR: begin
	251	{res, cflag_out} = {operand, cflag_in} >> shift_amt \| (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
	252	end
	253	`SHIFT_ROR: begin
	254	if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
	255	res = {cflag_in, operand[31:1]};
	256	cflag_out = operand[0];
26049339	257	end else if(shift_amt == 6'b0) begin
bae77231 CL	258	res = operand;
	259	cflag_out = cflag_in;
	260	end else begin
	261	res = operand >> shift_amt[4:0] \| operand << (5'b0 - shift_amt[4:0]);
	262	cflag_out = operand[shift_amt[4:0] - 5'b1];
	263	end
	264	end
26049339	265	endcase
bae77231	266	endmodule