2008-07-08 |
Joshua Wise | bring in the make buildsystem for MandelFPGA |
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2008-06-19 |
Joshua Wise | Add support for Verilator |
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2008-03-28 |
Joshua Wise | Holy crap, dropped lut count to 7640, and slice count... |
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2008-03-28 |
Joshua Wise | Prod/cons-ify readout so it can do realtime |
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2008-03-28 |
Joshua Wise | Add readout |
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2008-03-28 |
Joshua Wise | Something that works |
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2008-03-28 |
Joshua Wise | new ctoreadmemb |
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2008-03-28 |
Joshua Wise | poke the clock with a stick |
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2008-03-28 |
Joshua Wise | Use the new shnasto PRE_ROLLBACK |
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2008-03-28 |
Joshua Wise | Fix the lame on the multiplier's indentation |
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2008-03-28 |
Joshua Wise | Fix the lame on the multiplier's indentation |
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2008-03-20 |
Joshua Wise | A define for MAKE_UNIT. And there was much rejoicing. |
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2008-03-20 |
Joshua Wise | what the fuck, this was supposed to get the slice count... |
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2008-03-20 |
Joshua Wise | Clean up and turn the iout and rout into twos comp... |
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2008-03-19 |
Joshua Wise | Reg the init variables -- takes us to 83.842MHz! 8678... |
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2008-03-19 |
Joshua Wise | Drop a bit from the overflow. Rewrite the assigns. |
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2008-03-18 |
Joshua Wise | 76.025MHz, ship it |
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2008-03-18 |
Joshua Wise | Remove the DCM cascade unit -- makes it faster to synth... |
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2008-03-18 |
Joshua Wise | Fixed statekick once and for all, hopefully. |
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2008-03-18 |
Joshua Wise | Use a single DCM unit. |
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2008-03-18 |
Joshua Wise | Potentially fixed triplepump: 75.028MHz, 4596 slices... |
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2008-03-18 |
Joshua Wise | Cut 1 at triple pumping the pipeline |
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2008-03-17 |
Joshua Wise | Optimization baseline, 77.788MHz, 4894 Slices, 1849... |
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2008-03-17 |
Joshua Wise | Optimization baseline, 70.493MHz, 4913 Slices, 1843... |
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2008-03-16 |
Joshua Wise | Correct whirrrrr |
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2008-03-16 |
Joshua Wise | Bugfix extend init*. |
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2008-03-16 |
Joshua Wise | Working 13 bit. |
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2008-03-15 |
Joshua Wise | Initial revision -- unknown as to whether it works... |
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