Joshua Wise's Git repositories - mandelfpga.git/search

]> Joshua Wise's Git repositories - mandelfpga.git/search

2008-03-20	Joshua Wise	Clean up and turn the iout and rout into twos comp...	commit \| commitdiff \| tree
2008-03-19	Joshua Wise	Reg the init variables -- takes us to 83.842MHz! 8678...	commit \| commitdiff \| tree
2008-03-19	Joshua Wise	Drop a bit from the overflow. Rewrite the assigns.	commit \| commitdiff \| tree
2008-03-18	Joshua Wise	76.025MHz, ship it	commit \| commitdiff \| tree
2008-03-18	Joshua Wise	Remove the DCM cascade unit -- makes it faster to synthesize	commit \| commitdiff \| tree
2008-03-18	Joshua Wise	Fixed statekick once and for all, hopefully.	commit \| commitdiff \| tree
2008-03-18	Joshua Wise	Use a single DCM unit.	commit \| commitdiff \| tree
2008-03-18	Joshua Wise	Potentially fixed triplepump: 75.028MHz, 4596 slices...	commit \| commitdiff \| tree
2008-03-18	Joshua Wise	Cut 1 at triple pumping the pipeline	commit \| commitdiff \| tree
2008-03-17	Joshua Wise	Optimization baseline, 77.788MHz, 4894 Slices, 1849...	commit \| commitdiff \| tree
2008-03-17	Joshua Wise	Optimization baseline, 70.493MHz, 4913 Slices, 1843...	commit \| commitdiff \| tree
2008-03-16	Joshua Wise	Correct whirrrrr	commit \| commitdiff \| tree
2008-03-16	Joshua Wise	Bugfix extend init*.	commit \| commitdiff \| tree
2008-03-16	Joshua Wise	Working 13 bit.	commit \| commitdiff \| tree
2008-03-15	Joshua Wise	Initial revision -- unknown as to whether it works...	commit \| commitdiff \| tree

Pipelined realtime renderer of the Mandelbrot set on a Xilinx FPGA

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