Move the core to core/
[fpgaboy.git] / core / GBZ80Core.v
CommitLineData
df770340
JW
1`define REG_A 0
2`define REG_B 1
3`define REG_C 2
4`define REG_D 3
5`define REG_E 4
6`define REG_F 5
7`define REG_H 6
8`define REG_L 7
9`define REG_SPH 8
10`define REG_SPL 9
11`define REG_PCH 10
12`define REG_PCL 11
2f55f809 13
5509558d
JW
14`define _A registers[`REG_A]
15`define _B registers[`REG_B]
16`define _C registers[`REG_C]
17`define _D registers[`REG_D]
18`define _E registers[`REG_E]
19`define _F registers[`REG_F]
20`define _H registers[`REG_H]
21`define _L registers[`REG_L]
22`define _SPH registers[`REG_SPH]
23`define _SPL registers[`REG_SPL]
24`define _PCH registers[`REG_PCH]
25`define _PCL registers[`REG_PCL]
26`define _AF {`_A, `_F}
27`define _BC {`_B, `_C}
28`define _DE {`_D, `_E}
29`define _HL {`_H, `_L}
30`define _SP {`_SPH, `_SPL}
31`define _PC {`_PCH, `_PCL}
32
df770340
JW
33`define FLAG_Z 8'b10000000
34`define FLAG_N 8'b01000000
35`define FLAG_H 8'b00100000
36`define FLAG_C 8'b00010000
2f55f809 37
df770340
JW
38`define STATE_FETCH 2'h0
39`define STATE_DECODE 2'h1
2f55f809
JW
40`define STATE_EXECUTE 2'h2
41`define STATE_WRITEBACK 2'h3
42
decafd62
JW
43`define INSN_LD_reg_imm8 9'b000xxx110
44`define INSN_HALT 9'b001110110
45`define INSN_LD_HL_reg 9'b001110xxx
46`define INSN_LD_reg_HL 9'b001xxx110
47`define INSN_LD_reg_reg 9'b001xxxxxx
48`define INSN_LD_reg_imm16 9'b000xx0001
49`define INSN_LD_SP_HL 9'b011111001
50`define INSN_PUSH_reg 9'b011xx0101
51`define INSN_POP_reg 9'b011xx0001
52`define INSN_LDH_AC 9'b0111x0010 // Either LDH A,(C) or LDH (C),A
53`define INSN_LDx_AHL 9'b0001xx010 // LDD/LDI A,(HL) / (HL),A
54`define INSN_ALU8 9'b010xxxxxx // 10 xxx yyy
55`define INSN_ALU8IMM 9'b011xxx110
56`define INSN_NOP 9'b000000000
57`define INSN_RST 9'b011xxx111
58`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET
59`define INSN_RETCC 9'b0110xx000
60`define INSN_CALL 9'b011001101
61`define INSN_CALLCC 9'b0110xx100 // Not that call/cc.
62`define INSN_JP_imm 9'b011000011
63`define INSN_JPCC_imm 9'b0110xx010
64`define INSN_ALU_A 9'b000xxx111
65`define INSN_JP_HL 9'b011101001
66`define INSN_JR_imm 9'b000011000
67`define INSN_JRCC_imm 9'b0001xx000
68`define INSN_INCDEC16 9'b000xxx011
69`define INSN_VOP_INTR 9'b011111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
70`define INSN_DI 9'b011110011
71`define INSN_EI 9'b011111011
72`define INSN_INCDEC_HL 9'b00011010x
73`define INSN_INCDEC_reg8 9'b000xxx10x
74`define INSN_LD8M_A 9'b0111x0000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
75`define INSN_LD16M_A 9'b0111x1010 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
76`define INSN_LDBCDE_A 9'b0000xx010
77`define INSN_TWO_BYTE 9'b011001011 // prefix for two-byte opqodes
78`define INSN_ALU_EXT 9'b100xxxxxx
79`define INSN_BIT 9'b101xxxxxx
80`define INSN_RES 9'b110xxxxxx
81`define INSN_SET 9'b111xxxxxx
00a4c19f 82`define INSN_ADD_HL 9'b000xx1001
a85b19a7 83
df770340
JW
84`define INSN_cc_NZ 2'b00
85`define INSN_cc_Z 2'b01
86`define INSN_cc_NC 2'b10
87`define INSN_cc_C 2'b11
fa136d63 88
b85870e0
JW
89`define INSN_reg_A 3'b111
90`define INSN_reg_B 3'b000
91`define INSN_reg_C 3'b001
92`define INSN_reg_D 3'b010
93`define INSN_reg_E 3'b011
94`define INSN_reg_H 3'b100
95`define INSN_reg_L 3'b101
df770340
JW
96`define INSN_reg_dHL 3'b110
97`define INSN_reg16_BC 2'b00
98`define INSN_reg16_DE 2'b01
99`define INSN_reg16_HL 2'b10
100`define INSN_reg16_SP 2'b11
101`define INSN_stack_AF 2'b11
102`define INSN_stack_BC 2'b00
103`define INSN_stack_DE 2'b01
104`define INSN_stack_HL 2'b10
94522011
JW
105`define INSN_alu_ADD 3'b000
106`define INSN_alu_ADC 3'b001
107`define INSN_alu_SUB 3'b010
108`define INSN_alu_SBC 3'b011
109`define INSN_alu_AND 3'b100
110`define INSN_alu_XOR 3'b101
111`define INSN_alu_OR 3'b110
112`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
a00483d0
JW
113`define INSN_alu_RLCA 3'b000
114`define INSN_alu_RRCA 3'b001
115`define INSN_alu_RLA 3'b010
116`define INSN_alu_RRA 3'b011
117`define INSN_alu_DAA 3'b100
118`define INSN_alu_CPL 3'b101
119`define INSN_alu_SCF 3'b110
120`define INSN_alu_CCF 3'b111
decafd62
JW
121`define INSN_alu_RLC 3'b000
122`define INSN_alu_RRC 3'b001
123`define INSN_alu_RL 3'b010
124`define INSN_alu_RR 3'b011
125`define INSN_alu_DA_SLA 3'b100
126`define INSN_alu_CPL_SRA 3'b101
127`define INSN_alu_SCF_SWAP 3'b110
128`define INSN_alu_CCF_SRL 3'b111
94522011 129
5c33c5c0
JW
130`define EXEC_INC_PC `_PC <= `_PC + 1;
131`define EXEC_NEXTADDR_PCINC address <= `_PC + 1;
132`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end
decafd62 133`define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
e7fb589a
JW
134`ifdef verilator
135 `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end
136 `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end
137`else
138 `ifdef isim
139 `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end
140 `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end
141 `else
142/* Work around XST's retarded bugs :\ */
143 `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
144 `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
145 `endif
146`endif
5509558d 147
2f55f809
JW
148module GBZ80Core(
149 input clk,
91c74a3f
JW
150 inout [15:0] bus0address, /* BUS_* is latched on STATE_FETCH. */
151 inout [7:0] bus0data,
152 inout bus0wr, bus0rd,
153 inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */
154 inout [7:0] bus1data,
155 inout bus1wr, bus1rd,
d1b40456 156 input irq, output reg irqack, input [7:0] jaddr,
6c46357c 157 output reg [1:0] state);
decafd62 158
6c46357c 159// reg [1:0] state; /* State within this bus cycle (see STATE_*). */
9c834ff2 160 reg [2:0] cycle; /* Cycle for instructions. */
2f55f809
JW
161
162 reg [7:0] registers[11:0];
163
164 reg [15:0] address; /* Address for the next bus operation. */
165
decafd62
JW
166 reg [8:0] opcode; /* Opcode from the current machine cycle. */
167
2f55f809 168 reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
decafd62 169 reg rd, wr, newcycle, twobyte;
2f55f809 170
ef6fbe31 171 reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0 172
2f55f809 173 reg [7:0] buswdata;
91c74a3f
JW
174 wire [7:0] busdata;
175
176 reg [15:0] busaddress;
177 reg buswr, busrd;
178
179 reg bootstrap_enb;
180
e29171aa
JW
181 wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)) /* 0 or 1 depending on which bus */
182 `ifdef isim
183 || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
184 `endif
185 ;
91c74a3f
JW
186
187 assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
188 assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
189 assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
190 assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
191 assign busdata = (bus == 0) ? bus0data : bus1data;
e29171aa
JW
192 assign bus0rd = (bus == 0) ? busrd : 1'b0;
193 assign bus1rd = (bus == 1) ? busrd : 1'b0;
194 assign bus0wr = (bus == 0) ? buswr : 1'b0;
195 assign bus1wr = (bus == 1) ? buswr : 1'b0;
decafd62 196
eb0f2fe1 197 reg ie, iedelay;
decafd62
JW
198
199 wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
200 wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
201 wire [7:0] alu_res;
202 wire [3:0] f_res;
203
204 assign rlc = {tmp[6:0],tmp[7]};
205 assign rlcf = {(tmp == 0 ? 1'b1 : 1'b0)
206 ,2'b0,
207 tmp[7]};
208
209 assign rrc = {tmp[0],tmp[7:1]};
210 assign rrcf = {(tmp == 0 ? 1'b1 : 1'b0),
211 2'b0,
212 tmp[0]};
213
214 assign rl = {tmp[6:0],`_F[4]};
215 assign rlf = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
216 2'b0,
217 tmp[7]};
218
219 assign rr = {`_F[4],tmp[7:1]};
220 assign rrf = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
221 2'b0,
222 tmp[0]};
223
e7fb589a 224 assign sla = {tmp[6:0],1'b0};
decafd62
JW
225 assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
226 2'b0,
227 tmp[7]};
228
229 assign sra = {tmp[7],tmp[7:1]};
230// assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf =
231
232 assign swap = {tmp[3:0],tmp[7:4]};
e7fb589a 233 assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),
decafd62
JW
234 3'b0};
235
e7fb589a 236 assign srl = {1'b0,tmp[7:1]};
decafd62
JW
237 assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
238 2'b0,
239 tmp[0]};
240 assign sraf = srlf;
241
242 /* Y U Q */
243 assign {alu_res,f_res} =
244 opcode[5] ? (
245 opcode[4] ? (
246 opcode[3] ? {srl,srlf} : {swap,swapf}
247 ) : (
248 opcode[3] ? {sra,sraf} : {sla,slaf}
249 )
250 ) : (
251 opcode[4] ? (
252 opcode[3] ? {rr,rrf} : {rl,rlf}
253 ) : (
254 opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
255 )
256 );
257
2f55f809 258 initial begin
b4f3ac35
JW
259 `_A <= 0;
260 `_B <= 0;
261 `_C <= 0;
262 `_D <= 0;
263 `_E <= 0;
264 `_F <= 0;
265 `_H <= 0;
266 `_L <= 0;
267 `_PCH <= 0;
268 `_PCL <= 0;
269 `_SPH <= 0;
270 `_SPL <= 0;
2e642f1f
JW
271 rd <= 1;
272 wr <= 0;
273 newcycle <= 1;
274 state <= 0;
275 cycle <= 0;
f8db6448
JW
276 busrd <= 0;
277 buswr <= 0;
278 busaddress <= 0;
9c834ff2 279 ie <= 0;
f8db6448 280 iedelay <= 0;
9c834ff2
JW
281 opcode <= 0;
282 state <= `STATE_WRITEBACK;
283 cycle <= 0;
decafd62 284 twobyte <= 0;
91c74a3f 285 bootstrap_enb <= 1;
d1b40456 286 irqack <= 0;
2f55f809
JW
287 end
288
b338a0b6 289 always @(negedge clk) /* Set things up at the negedge to prepare for the posedge. */
2f55f809
JW
290 case (state)
291 `STATE_FETCH: begin
2e642f1f 292 if (newcycle) begin
decafd62 293 busaddress <= `_PC;
2e642f1f
JW
294 buswr <= 0;
295 busrd <= 1;
296 end else begin
2f55f809 297 busaddress <= address;
2e642f1f
JW
298 buswr <= wr;
299 busrd <= rd;
1eefdc8e 300 if (wr) begin
2e642f1f 301 buswdata <= wdata;
1eefdc8e
JW
302 if (address == 16'hFF50)
303 bootstrap_enb <= 0;
304 end
2e642f1f 305 end
b338a0b6
JW
306 end
307 `STATE_DECODE: begin /* Make sure this only happens for one clock. */
e29171aa
JW
308 buswr <= 0;
309 busrd <= 0;
b338a0b6
JW
310 end
311 endcase
312
313 always @(posedge clk)
314 case (state)
315 `STATE_FETCH: begin
316 /* Things are set up in negedge so that something looking on posedge will get his shit. */
2f55f809
JW
317 state <= `STATE_DECODE;
318 end
319 `STATE_DECODE: begin
320 if (newcycle) begin
decafd62 321 if (twobyte) begin
e7fb589a 322 opcode <= {1'b1,busdata};
decafd62
JW
323 twobyte <= 0;
324 end else if (ie && irq)
f8db6448
JW
325 opcode <= `INSN_VOP_INTR;
326 else
e7fb589a 327 opcode <= {1'b0,busdata};
b85870e0 328 newcycle <= 0;
2854e399 329 rdata <= busdata;
2f55f809 330 cycle <= 0;
2e642f1f 331 end else begin
e29171aa 332 if (rd) rdata <= busdata; /* Still valid because peripherals are now expected to keep it held valid. */
2e642f1f
JW
333 cycle <= cycle + 1;
334 end
f8db6448
JW
335 if (iedelay) begin
336 ie <= 1;
337 iedelay <= 0;
338 end
97649fed
JW
339 wr <= 0;
340 rd <= 0;
341 address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
342 wdata <= 8'bxxxxxxxx;
2f55f809
JW
343 state <= `STATE_EXECUTE;
344 end
345 `STATE_EXECUTE: begin
d1b40456 346 `ifdef isim
e29171aa
JW
347 if (opcode[7:0] === 8'bxxxxxxxx)
348 $stop;
d1b40456 349 `endif
2f55f809 350 casex (opcode)
81358c71
JW
351 `define EXECUTE
352 `include "allinsns.v"
353 `undef EXECUTE
634ce02c
JW
354 default:
355 $stop;
2f55f809
JW
356 endcase
357 state <= `STATE_WRITEBACK;
358 end
359 `STATE_WRITEBACK: begin
360 casex (opcode)
81358c71
JW
361 `define WRITEBACK
362 `include "allinsns.v"
363 `undef WRITEBACK
ef6fbe31
JW
364 default:
365 $stop;
2f55f809
JW
366 endcase
367 state <= `STATE_FETCH;
368 end
369 endcase
370endmodule
This page took 0.09681 seconds and 4 git commands to generate.