New generation makefile. Code that will reliably break the machine.
[fpgaboy.git] / GBZ80Core.v
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1`define REG_A 0
2`define REG_B 1
3`define REG_C 2
4`define REG_D 3
5`define REG_E 4
6`define REG_F 5
7`define REG_H 6
8`define REG_L 7
9`define REG_SPH 8
10`define REG_SPL 9
11`define REG_PCH 10
12`define REG_PCL 11
2f55f809 13
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14`define _A registers[`REG_A]
15`define _B registers[`REG_B]
16`define _C registers[`REG_C]
17`define _D registers[`REG_D]
18`define _E registers[`REG_E]
19`define _F registers[`REG_F]
20`define _H registers[`REG_H]
21`define _L registers[`REG_L]
22`define _SPH registers[`REG_SPH]
23`define _SPL registers[`REG_SPL]
24`define _PCH registers[`REG_PCH]
25`define _PCL registers[`REG_PCL]
26`define _AF {`_A, `_F}
27`define _BC {`_B, `_C}
28`define _DE {`_D, `_E}
29`define _HL {`_H, `_L}
30`define _SP {`_SPH, `_SPL}
31`define _PC {`_PCH, `_PCL}
32
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33`define FLAG_Z 8'b10000000
34`define FLAG_N 8'b01000000
35`define FLAG_H 8'b00100000
36`define FLAG_C 8'b00010000
2f55f809 37
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38`define STATE_FETCH 2'h0
39`define STATE_DECODE 2'h1
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40`define STATE_EXECUTE 2'h2
41`define STATE_WRITEBACK 2'h3
42
43`define INSN_LD_reg_imm8 8'b00xxx110
df770340 44`define INSN_HALT 8'b01110110
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45`define INSN_LD_HL_reg 8'b01110xxx
46`define INSN_LD_reg_HL 8'b01xxx110
47`define INSN_LD_reg_reg 8'b01xxxxxx
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48`define INSN_LD_reg_imm16 8'b00xx0001
49`define INSN_LD_SP_HL 8'b11111001
97649fed 50`define INSN_PUSH_reg 8'b11xx0101
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51`define INSN_POP_reg 8'b11xx0001
52`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A
53`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A
54`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy
55`define INSN_NOP 8'b00000000
56`define INSN_RST 8'b11xxx111
57`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
58`define INSN_RETCC 8'b110xx000
59`define INSN_CALL 8'b11001101
60`define INSN_CALLCC 8'b110xx100 // Not that call/cc.
61`define INSN_JP_imm 8'b11000011
a85b19a7 62`define INSN_JPCC_imm 8'b110xx010
a00483d0 63`define INSN_ALU_A 8'b00xxx111
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64`define INSN_JP_HL 8'b11101001
65`define INSN_JR_imm 8'b00011000
722e486a 66`define INSN_JRCC_imm 8'b001xx000
dadf7990 67`define INSN_INCDEC16 8'b00xxx011
f8db6448 68`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
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69`define INSN_DI 8'b11110011
70`define INSN_EI 8'b11111011
a85b19a7 71
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72`define INSN_cc_NZ 2'b00
73`define INSN_cc_Z 2'b01
74`define INSN_cc_NC 2'b10
75`define INSN_cc_C 2'b11
fa136d63 76
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77`define INSN_reg_A 3'b111
78`define INSN_reg_B 3'b000
79`define INSN_reg_C 3'b001
80`define INSN_reg_D 3'b010
81`define INSN_reg_E 3'b011
82`define INSN_reg_H 3'b100
83`define INSN_reg_L 3'b101
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84`define INSN_reg_dHL 3'b110
85`define INSN_reg16_BC 2'b00
86`define INSN_reg16_DE 2'b01
87`define INSN_reg16_HL 2'b10
88`define INSN_reg16_SP 2'b11
89`define INSN_stack_AF 2'b11
90`define INSN_stack_BC 2'b00
91`define INSN_stack_DE 2'b01
92`define INSN_stack_HL 2'b10
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93`define INSN_alu_ADD 3'b000
94`define INSN_alu_ADC 3'b001
95`define INSN_alu_SUB 3'b010
96`define INSN_alu_SBC 3'b011
97`define INSN_alu_AND 3'b100
98`define INSN_alu_XOR 3'b101
99`define INSN_alu_OR 3'b110
100`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
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101`define INSN_alu_RLCA 3'b000
102`define INSN_alu_RRCA 3'b001
103`define INSN_alu_RLA 3'b010
104`define INSN_alu_RRA 3'b011
105`define INSN_alu_DAA 3'b100
106`define INSN_alu_CPL 3'b101
107`define INSN_alu_SCF 3'b110
108`define INSN_alu_CCF 3'b111
94522011 109
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110`define EXEC_INC_PC `_PC <= `_PC + 1;
111`define EXEC_NEXTADDR_PCINC address <= `_PC + 1;
112`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end
113`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
114`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
5509558d 115
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116module GBZ80Core(
117 input clk,
eb0f2fe1 118 output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
2f55f809 119 inout [7:0] busdata,
eb0f2fe1 120 output reg buswr, output reg busrd,
f8db6448 121 input irq, input [7:0] jaddr);
2f55f809 122
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123 reg [1:0] state; /* State within this bus cycle (see STATE_*). */
124 reg [2:0] cycle; /* Cycle for instructions. */
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125
126 reg [7:0] registers[11:0];
127
128 reg [15:0] address; /* Address for the next bus operation. */
129
130 reg [7:0] opcode; /* Opcode from the current machine cycle. */
131
132 reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
9c834ff2 133 reg rd, wr, newcycle;
2f55f809 134
ef6fbe31 135 reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0 136
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137 reg [7:0] buswdata;
138 assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
139
eb0f2fe1 140 reg ie, iedelay;
abae5818 141
2f55f809 142 initial begin
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143 registers[ 0] <= 0;
144 registers[ 1] <= 0;
145 registers[ 2] <= 0;
146 registers[ 3] <= 0;
147 registers[ 4] <= 0;
148 registers[ 5] <= 0;
149 registers[ 6] <= 0;
150 registers[ 7] <= 0;
151 registers[ 8] <= 0;
152 registers[ 9] <= 0;
153 registers[10] <= 0;
154 registers[11] <= 0;
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155 rd <= 1;
156 wr <= 0;
157 newcycle <= 1;
158 state <= 0;
159 cycle <= 0;
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160 busrd <= 0;
161 buswr <= 0;
162 busaddress <= 0;
9c834ff2 163 ie <= 0;
f8db6448 164 iedelay <= 0;
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165 opcode <= 0;
166 state <= `STATE_WRITEBACK;
167 cycle <= 0;
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168 end
169
170 always @(posedge clk)
171 case (state)
172 `STATE_FETCH: begin
2e642f1f 173 if (newcycle) begin
2f55f809 174 busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
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175 buswr <= 0;
176 busrd <= 1;
177 end else begin
2f55f809 178 busaddress <= address;
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179 buswr <= wr;
180 busrd <= rd;
181 if (wr)
182 buswdata <= wdata;
183 end
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184 state <= `STATE_DECODE;
185 end
186 `STATE_DECODE: begin
187 if (newcycle) begin
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188 if (ie && irq)
189 opcode <= `INSN_VOP_INTR;
190 else
191 opcode <= busdata;
2f55f809 192 rdata <= busdata;
b85870e0 193 newcycle <= 0;
2f55f809 194 cycle <= 0;
2e642f1f 195 end else begin
2f55f809 196 if (rd) rdata <= busdata;
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197 cycle <= cycle + 1;
198 end
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199 if (iedelay) begin
200 ie <= 1;
201 iedelay <= 0;
202 end
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203 buswr <= 0;
204 busrd <= 0;
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205 wr <= 0;
206 rd <= 0;
207 address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
208 wdata <= 8'bxxxxxxxx;
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209 state <= `STATE_EXECUTE;
210 end
211 `STATE_EXECUTE: begin
2f55f809 212 casex (opcode)
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213 `define EXECUTE
214 `include "allinsns.v"
215 `undef EXECUTE
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216 default:
217 $stop;
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218 endcase
219 state <= `STATE_WRITEBACK;
220 end
221 `STATE_WRITEBACK: begin
222 casex (opcode)
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223 `define WRITEBACK
224 `include "allinsns.v"
225 `undef WRITEBACK
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226 default:
227 $stop;
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228 endcase
229 state <= `STATE_FETCH;
230 end
231 endcase
232endmodule
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