[fpgaboy.git] / GBZ80Core.v

`define REG_A 0
`define REG_B 1
`define REG_C 2
`define REG_D 3
`define REG_E 4
`define REG_F 5
`define REG_H 6
`define REG_L 7
`define REG_SPH 8
`define REG_SPL 9
`define REG_PCH 10
`define REG_PCL 11

`define FLAG_Z 8'b10000000
`define FLAG_N 8'b01000000
`define FLAG_H 8'b00100000
`define FLAG_C 8'b00010000

`define STATE_FETCH			2'h0
`define STATE_DECODE			2'h1
`define STATE_EXECUTE		2'h2
`define STATE_WRITEBACK		2'h3

`define INSN_LD_reg_imm8	8'b00xxx110
`define INSN_HALT				8'b01110110
`define INSN_LD_HL_reg		8'b01110xxx
`define INSN_LD_reg_HL		8'b01xxx110
`define INSN_LD_reg_reg		8'b01xxxxxx
`define INSN_LD_reg_imm16	8'b00xx0001
`define INSN_LD_SP_HL		8'b11111001
`define INSN_PUSH_reg		8'b11xx0101
`define INSN_POP_reg			8'b11xx0001
`define INSN_LDH_AC			8'b111x0010	// Either LDH A,(C) or LDH (C),A
`define INSN_LDx_AHL			8'b001xx010	// LDD/LDI A,(HL) / (HL),A
`define INSN_ALU8				8'b10xxxxxx	// 10 xxx yyy
`define INSN_NOP				8'b00000000
`define INSN_RST				8'b11xxx111
`define INSN_RET				8'b110x1001	// 1 = RETI, 0 = RET
`define INSN_RETCC			8'b110xx000
`define INSN_CALL				8'b11001101
`define INSN_CALLCC			8'b110xx100	// Not that call/cc.
`define INSN_JP_imm			8'b11000011
`define INSN_JPCC_imm		8'b110xx010
`define INSN_ALU_A		8'b00xxx111
`define INSN_JP_HL			8'b11101001
`define INSN_JR_imm			8'b00011000
`define INSN_JRCC_imm		8'b001xx000
`define INSN_INCDEC16		8'b00xxx011
`define INSN_VOP_INTR		8'b11111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
`define INSN_DI				8'b11110011
`define INSN_EI				8'b11111011

`define INSN_cc_NZ			2'b00
`define INSN_cc_Z				2'b01
`define INSN_cc_NC			2'b10
`define INSN_cc_C				2'b11

`define INSN_reg_A		3'b111
`define INSN_reg_B		3'b000
`define INSN_reg_C		3'b001
`define INSN_reg_D		3'b010
`define INSN_reg_E		3'b011
`define INSN_reg_H		3'b100
`define INSN_reg_L		3'b101
`define INSN_reg_dHL	3'b110
`define INSN_reg16_BC	2'b00
`define INSN_reg16_DE	2'b01
`define INSN_reg16_HL	2'b10
`define INSN_reg16_SP	2'b11
`define INSN_stack_AF	2'b11
`define INSN_stack_BC	2'b00
`define INSN_stack_DE	2'b01
`define INSN_stack_HL	2'b10
`define INSN_alu_ADD		3'b000
`define INSN_alu_ADC		3'b001
`define INSN_alu_SUB		3'b010
`define INSN_alu_SBC		3'b011
`define INSN_alu_AND		3'b100
`define INSN_alu_XOR		3'b101
`define INSN_alu_OR		3'b110
`define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
`define INSN_alu_RLCA		3'b000
`define INSN_alu_RRCA		3'b001
`define INSN_alu_RLA		3'b010
`define INSN_alu_RRA		3'b011
`define INSN_alu_DAA		3'b100
`define INSN_alu_CPL		3'b101
`define INSN_alu_SCF		3'b110
`define INSN_alu_CCF		3'b111

module GBZ80Core(
	input clk,
	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
	inout [7:0] busdata,
	output reg buswr, output reg busrd,
	input irq, input [7:0] jaddr);
	
	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
	reg [2:0] cycle;					/* Cycle for instructions. */
	
	reg [7:0] registers[11:0];
	
	reg [15:0] address;				/* Address for the next bus operation. */
	
	reg [7:0] opcode;				/* Opcode from the current machine cycle. */
	
	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
	reg rd, wr, newcycle;
	
	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
	
	reg [7:0] buswdata;
	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
	
	reg ie, iedelay;
	
	initial begin
		registers[ 0] <= 0;
		registers[ 1] <= 0;
		registers[ 2] <= 0;
		registers[ 3] <= 0;
		registers[ 4] <= 0;
		registers[ 5] <= 0;
		registers[ 6] <= 0;
		registers[ 7] <= 0;
		registers[ 8] <= 0;
		registers[ 9] <= 0;
		registers[10] <= 0;
		registers[11] <= 0;
		rd <= 1;
		wr <= 0;
		newcycle <= 1;
		state <= 0;
		cycle <= 0;
		busrd <= 0;
		buswr <= 0;
		busaddress <= 0;
		ie <= 0;
		iedelay <= 0;
		opcode <= 0;
		state <= `STATE_WRITEBACK;
		cycle <= 0;
	end

	always @(posedge clk)
		case (state)
		`STATE_FETCH: begin
			if (newcycle) begin
				busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
				buswr <= 0;
				busrd <= 1;
			end else begin
				busaddress <= address;
				buswr <= wr;
				busrd <= rd;
				if (wr)
					buswdata <= wdata;
			end
			state <= `STATE_DECODE;
		end
		`STATE_DECODE: begin
			if (newcycle) begin
				if (ie && irq)
					opcode <= `INSN_VOP_INTR;
				else
					opcode <= busdata;
				rdata <= busdata;
				newcycle <= 0;
				cycle <= 0;
			end else begin
				if (rd) rdata <= busdata;
				cycle <= cycle + 1;
			end
			if (iedelay) begin
				ie <= 1;
				iedelay <= 0;
			end
			buswr <= 0;
			busrd <= 0;
			wr <= 0;
			rd <= 0;
			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
			wdata <= 8'bxxxxxxxx;
			state <= `STATE_EXECUTE;
		end
		`STATE_EXECUTE: begin
`define EXEC_INC_PC \
	{registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
`define EXEC_NEXTADDR_PCINC \
	address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
`define EXEC_NEWCYCLE \
	newcycle <= 1; rd <= 1; wr <= 0
			casex (opcode)
			`define EXECUTE
			`include "allinsns.v"
			`undef EXECUTE
			`INSN_RST: begin
				case (cycle)
				0:	begin
						`EXEC_INC_PC;		// This goes FIRST in RST
					end
				1:	begin
						wr <= 1;
						address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
						wdata <= registers[`REG_PCH];
					end
				2:	begin
						wr <= 1;
						address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
						wdata <= registers[`REG_PCL];
					end
				3:	begin
						`EXEC_NEWCYCLE;
						{registers[`REG_PCH],registers[`REG_PCL]} <=
							{10'b0,opcode[5:3],3'b0};
					end
				endcase
			end
			`INSN_RET,`INSN_RETCC: begin
				case (cycle)
				0:	begin
						rd <= 1;
						address <= {registers[`REG_SPH],registers[`REG_SPL]};
					end
				1:	begin	// SPECIAL CASE: cycle does NOT increase linearly with ret!
						`EXEC_INC_PC;	// cycle 1 is skipped if we are not retcc
						case (opcode[4:3])
						`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
						`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
						`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
						`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
						endcase
						rd <= 1;
						address <= {registers[`REG_SPH],registers[`REG_SPL]};
					end
				2:	begin
						rd <= 1;
						address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
					end
				3:	begin /* twiddle thumbs */ end
				4:	begin
						`EXEC_NEWCYCLE;
						// do NOT increment PC!
					end
				endcase
			end
			`INSN_CALL,`INSN_CALLCC: begin
				case (cycle)
				0:	begin
						`EXEC_INC_PC;
						`EXEC_NEXTADDR_PCINC;
						rd <= 1;
					end
				1:	begin
						`EXEC_INC_PC;
						`EXEC_NEXTADDR_PCINC;
						rd <= 1;
					end
				2:	begin
						`EXEC_INC_PC;
						if (!opcode[0])	// i.e., is callcc
							/* We need to check the condition code to bail out. */
							case (opcode[4:3])
							`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
							endcase
					end
				3:	begin
						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
						wdata <= registers[`REG_PCH];
						wr <= 1;
					end
				4:	begin
						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
						wdata <= registers[`REG_PCL];
						wr <= 1;
					end
				5:	begin
						`EXEC_NEWCYCLE;	/* do NOT increment the PC */
					end
				endcase
			end
			`INSN_JP_imm,`INSN_JPCC_imm: begin
				case (cycle)
				0:	begin
						`EXEC_INC_PC;
						`EXEC_NEXTADDR_PCINC;
						rd <= 1;
					end
				1:	begin
						`EXEC_INC_PC;
						`EXEC_NEXTADDR_PCINC;
						rd <= 1;
					end
				2:	begin
						`EXEC_INC_PC;
						if (!opcode[0]) begin	// i.e., JP cc,nn
							/* We need to check the condition code to bail out. */
							case (opcode[4:3])
							`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
							endcase
						end
					end
				3:	begin
						`EXEC_NEWCYCLE;
					end
				endcase
			end
			`INSN_JP_HL: begin
				`EXEC_NEWCYCLE;
			end
			`INSN_JR_imm,`INSN_JRCC_imm: begin
				case (cycle)
				0:	begin
						`EXEC_INC_PC;
						`EXEC_NEXTADDR_PCINC;
						rd <= 1;
					end
				1: begin
						`EXEC_INC_PC;
						if (opcode[5]) begin	// i.e., JP cc,nn
							/* We need to check the condition code to bail out. */
							case (opcode[4:3])
							`INSN_cc_NZ:	if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_Z:		if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_NC:	if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
							`INSN_cc_C:		if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
							endcase
						end
					end
				2:	begin
						`EXEC_NEWCYCLE;
					end
				endcase
			end
			`INSN_INCDEC16: begin
				case (cycle)
				0: begin
						case (opcode[5:4])
						`INSN_reg16_BC:	begin
							tmp <= registers[`REG_B];
							tmp2 <= registers[`REG_C];
						end
						`INSN_reg16_DE:	begin
							tmp <= registers[`REG_D];
							tmp2 <= registers[`REG_E];
						end
						`INSN_reg16_HL:	begin
							tmp <= registers[`REG_H];
							tmp2 <= registers[`REG_L];
						end
						`INSN_reg16_SP:	begin
							tmp <= registers[`REG_SPH];
							tmp2 <= registers[`REG_SPL];
						end
						endcase
					end
				1: begin
						`EXEC_INC_PC;
						`EXEC_NEWCYCLE;
					end
				endcase
			end
			`INSN_VOP_INTR: begin
				case (cycle)
				0:	begin
						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
						wdata <= registers[`REG_PCH];
						wr <= 1;
					end
				1:	begin
						address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
						wdata <= registers[`REG_PCL];
						wr <= 1;
					end
				2:	begin
						`EXEC_NEWCYCLE;
					end
				endcase
			end
			`INSN_DI: begin
				`EXEC_NEWCYCLE;
				`EXEC_INC_PC;
			end
			`INSN_EI: begin
				`EXEC_NEWCYCLE;
				`EXEC_INC_PC;
			end
			default:
				$stop;
			endcase
			state <= `STATE_WRITEBACK;
		end
		`STATE_WRITEBACK: begin
			casex (opcode)
			`define WRITEBACK
			`include "allinsns.v"
			`undef WRITEBACK
			`INSN_RST: begin
				case (cycle)
				0:	begin /* type F */ end
				1:	begin /* type F */ end
				2:	begin /* type F */ end
				3:	{registers[`REG_SPH],registers[`REG_SPL]} <=
						{registers[`REG_SPH],registers[`REG_SPL]}-2;
				endcase
			end
			`INSN_RET,`INSN_RETCC: begin
				case (cycle)
				0:	if (opcode[0])	// i.e., not RETCC
						cycle <= 1;	// Skip cycle 1; it gets incremented on the next round.
				1: begin /* Nothing need happen here. */ end
				2:	registers[`REG_PCL] <= rdata;
				3:	registers[`REG_PCH] <= rdata;
				4:	begin
						{registers[`REG_SPH],registers[`REG_SPL]} <=
							{registers[`REG_SPH],registers[`REG_SPL]} + 2;
						if (opcode[4] && opcode[0])	/* RETI */
							ie <= 1;
					end
				endcase
			end
			`INSN_CALL,`INSN_CALLCC: begin
				case (cycle)
				0:	begin /* type F */ end
				1:	tmp <= rdata;	// tmp contains newpcl
				2:	tmp2 <= rdata;	// tmp2 contains newpch
				3:	begin /* type F */ end
				4:	registers[`REG_PCH] <= tmp2;
				5: begin
						{registers[`REG_SPH],registers[`REG_SPL]} <=
							{registers[`REG_SPH],registers[`REG_SPL]} - 2;
						registers[`REG_PCL] <= tmp;
					end
				endcase
			end
			`INSN_JP_imm,`INSN_JPCC_imm: begin
				case (cycle)
				0:	begin /* type F */ end
				1:	tmp <= rdata;	// tmp contains newpcl
				2:	tmp2 <= rdata;	// tmp2 contains newpch
				3:	{registers[`REG_PCH],registers[`REG_PCL]} <=
						{tmp2,tmp};
				endcase
			end
			`INSN_JP_HL: begin
				{registers[`REG_PCH],registers[`REG_PCL]} <=
					{registers[`REG_H],registers[`REG_L]};
			end
			`INSN_JR_imm,`INSN_JRCC_imm: begin
				case (cycle)
				0:	begin /* type F */ end
				1:	tmp <= rdata;
				2: {registers[`REG_PCH],registers[`REG_PCL]} <=
						{registers[`REG_PCH],registers[`REG_PCL]} +
						{tmp[7]?8'hFF:8'h00,tmp};
				endcase
			end
			`INSN_INCDEC16: begin
				case (cycle)
				0:	{tmp,tmp2} <= {tmp,tmp2} +
						(opcode[3] ? 16'hFFFF : 16'h0001);
				1: begin
						case (opcode[5:4])
						`INSN_reg16_BC:	begin
							registers[`REG_B] <= tmp;
							registers[`REG_C] <= tmp2;
						end
						`INSN_reg16_DE:	begin
							registers[`REG_D] <= tmp;
							registers[`REG_E] <= tmp2;
						end
						`INSN_reg16_HL:	begin
							registers[`REG_H] <= tmp;
							registers[`REG_L] <= tmp2;
						end
						`INSN_reg16_SP:	begin
							registers[`REG_SPH] <= tmp;
							registers[`REG_SPL] <= tmp2;
						end
						endcase
					end
				endcase
			end
			`INSN_VOP_INTR: begin
				case (cycle)
				0:	begin end
				1:	begin end
				2:	begin
						ie <= 0;
						{registers[`REG_PCH],registers[`REG_PCL]} <=
							{8'b0,jaddr};
						{registers[`REG_SPH],registers[`REG_SPL]} <=
							{registers[`REG_SPH],registers[`REG_SPL]} - 2;
					end
				endcase
			end
			`INSN_DI: ie <= 0;
			`INSN_EI: iedelay <= 1;
			default:
				$stop;
			endcase
			state <= `STATE_FETCH;
		end
		endcase
endmodule
Commit	Line	Data
2f55f809 JW	1	`define REG_A 0
	2	`define REG_B 1
	3	`define REG_C 2
	4	`define REG_D 3
	5	`define REG_E 4
	6	`define REG_F 5
	7	`define REG_H 6
	8	`define REG_L 7
	9	`define REG_SPH 8
	10	`define REG_SPL 9
	11	`define REG_PCH 10
	12	`define REG_PCL 11
	13
	14	`define FLAG_Z 8'b10000000
	15	`define FLAG_N 8'b01000000
	16	`define FLAG_H 8'b00100000
	17	`define FLAG_C 8'b00010000
	18
	19	`define STATE_FETCH 2'h0
	20	`define STATE_DECODE 2'h1
	21	`define STATE_EXECUTE 2'h2
	22	`define STATE_WRITEBACK 2'h3
	23
	24	`define INSN_LD_reg_imm8 8'b00xxx110
b85870e0 JW	25	`define INSN_HALT 8'b01110110
	26	`define INSN_LD_HL_reg 8'b01110xxx
	27	`define INSN_LD_reg_HL 8'b01xxx110
	28	`define INSN_LD_reg_reg 8'b01xxxxxx
634ce02c JW	29	`define INSN_LD_reg_imm16 8'b00xx0001
634ce02c JW	30	`define INSN_LD_SP_HL 8'b11111001
97649fed	31	`define INSN_PUSH_reg 8'b11xx0101
00e30b4d JW	32	`define INSN_POP_reg 8'b11xx0001
00e30b4d JW	33	`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A
fa136d63	34	`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A
94522011	35	`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy
d3938806	36	`define INSN_NOP 8'b00000000
1e03e021	37	`define INSN_RST 8'b11xxx111
abae5818	38	`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
611e4a90	39	`define INSN_RETCC 8'b110xx000
ef6fbe31	40	`define INSN_CALL 8'b11001101
6b4e2828	41	`define INSN_CALLCC 8'b110xx100 // Not that call/cc.
a85b19a7 JW	42	`define INSN_JP_imm 8'b11000011
a85b19a7 JW	43	`define INSN_JPCC_imm 8'b110xx010
a00483d0	44	`define INSN_ALU_A 8'b00xxx111
6b4e2828	45	`define INSN_JP_HL 8'b11101001
722e486a JW	46	`define INSN_JR_imm 8'b00011000
722e486a JW	47	`define INSN_JRCC_imm 8'b001xx000
dadf7990	48	`define INSN_INCDEC16 8'b00xxx011
f8db6448 JW	49	`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
	50	`define INSN_DI 8'b11110011
	51	`define INSN_EI 8'b11111011
a85b19a7 JW	52
	53	`define INSN_cc_NZ 2'b00
	54	`define INSN_cc_Z 2'b01
	55	`define INSN_cc_NC 2'b10
	56	`define INSN_cc_C 2'b11
fa136d63	57
b85870e0 JW	58	`define INSN_reg_A 3'b111
	59	`define INSN_reg_B 3'b000
	60	`define INSN_reg_C 3'b001
	61	`define INSN_reg_D 3'b010
	62	`define INSN_reg_E 3'b011
	63	`define INSN_reg_H 3'b100
	64	`define INSN_reg_L 3'b101
	65	`define INSN_reg_dHL 3'b110
634ce02c JW	66	`define INSN_reg16_BC 2'b00
	67	`define INSN_reg16_DE 2'b01
	68	`define INSN_reg16_HL 2'b10
	69	`define INSN_reg16_SP 2'b11
97649fed JW	70	`define INSN_stack_AF 2'b11
	71	`define INSN_stack_BC 2'b00
	72	`define INSN_stack_DE 2'b01
	73	`define INSN_stack_HL 2'b10
94522011 JW	74	`define INSN_alu_ADD 3'b000
	75	`define INSN_alu_ADC 3'b001
	76	`define INSN_alu_SUB 3'b010
	77	`define INSN_alu_SBC 3'b011
	78	`define INSN_alu_AND 3'b100
	79	`define INSN_alu_XOR 3'b101
	80	`define INSN_alu_OR 3'b110
	81	`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
a00483d0 JW	82	`define INSN_alu_RLCA 3'b000
	83	`define INSN_alu_RRCA 3'b001
	84	`define INSN_alu_RLA 3'b010
	85	`define INSN_alu_RRA 3'b011
	86	`define INSN_alu_DAA 3'b100
	87	`define INSN_alu_CPL 3'b101
	88	`define INSN_alu_SCF 3'b110
	89	`define INSN_alu_CCF 3'b111
94522011	90
2f55f809 JW	91	module GBZ80Core(
2f55f809 JW	92	input clk,
eb0f2fe1	93	output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
2f55f809	94	inout [7:0] busdata,
eb0f2fe1	95	output reg buswr, output reg busrd,
f8db6448	96	input irq, input [7:0] jaddr);
2f55f809	97
9c834ff2 JW	98	reg [1:0] state; /* State within this bus cycle (see STATE_). /
9c834ff2 JW	99	reg [2:0] cycle; /* Cycle for instructions. */
2f55f809 JW	100
	101	reg [7:0] registers[11:0];
	102
	103	reg [15:0] address; /* Address for the next bus operation. */
	104
	105	reg [7:0] opcode; /* Opcode from the current machine cycle. */
	106
	107	reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
9c834ff2	108	reg rd, wr, newcycle;
2f55f809	109
ef6fbe31	110	reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0	111
2f55f809 JW	112	reg [7:0] buswdata;
	113	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
	114
eb0f2fe1	115	reg ie, iedelay;
abae5818	116
2f55f809	117	initial begin
241c995c JW	118	registers[ 0] <= 0;
	119	registers[ 1] <= 0;
	120	registers[ 2] <= 0;
	121	registers[ 3] <= 0;
	122	registers[ 4] <= 0;
	123	registers[ 5] <= 0;
	124	registers[ 6] <= 0;
	125	registers[ 7] <= 0;
	126	registers[ 8] <= 0;
	127	registers[ 9] <= 0;
	128	registers[10] <= 0;
	129	registers[11] <= 0;
2e642f1f JW	130	rd <= 1;
	131	wr <= 0;
	132	newcycle <= 1;
	133	state <= 0;
	134	cycle <= 0;
f8db6448 JW	135	busrd <= 0;
	136	buswr <= 0;
	137	busaddress <= 0;
9c834ff2	138	ie <= 0;
f8db6448	139	iedelay <= 0;
9c834ff2 JW	140	opcode <= 0;
	141	state <= `STATE_WRITEBACK;
	142	cycle <= 0;
2f55f809 JW	143	end
	144
	145	always @(posedge clk)
	146	case (state)
	147	`STATE_FETCH: begin
2e642f1f	148	if (newcycle) begin
2f55f809	149	busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
2e642f1f JW	150	buswr <= 0;
	151	busrd <= 1;
	152	end else begin
2f55f809	153	busaddress <= address;
2e642f1f JW	154	buswr <= wr;
	155	busrd <= rd;
	156	if (wr)
	157	buswdata <= wdata;
	158	end
2f55f809 JW	159	state <= `STATE_DECODE;
	160	end
	161	`STATE_DECODE: begin
	162	if (newcycle) begin
f8db6448 JW	163	if (ie && irq)
	164	opcode <= `INSN_VOP_INTR;
	165	else
	166	opcode <= busdata;
2f55f809	167	rdata <= busdata;
b85870e0	168	newcycle <= 0;
2f55f809	169	cycle <= 0;
2e642f1f	170	end else begin
2f55f809	171	if (rd) rdata <= busdata;
2e642f1f JW	172	cycle <= cycle + 1;
2e642f1f JW	173	end
f8db6448 JW	174	if (iedelay) begin
	175	ie <= 1;
	176	iedelay <= 0;
	177	end
2f55f809 JW	178	buswr <= 0;
2f55f809 JW	179	busrd <= 0;
97649fed JW	180	wr <= 0;
	181	rd <= 0;
	182	address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
	183	wdata <= 8'bxxxxxxxx;
2f55f809 JW	184	state <= `STATE_EXECUTE;
	185	end
	186	`STATE_EXECUTE: begin
	187	`define EXEC_INC_PC \
	188	{registers[`REG_PCH], registers[`REG_PCL]} <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
	189	`define EXEC_NEXTADDR_PCINC \
	190	address <= {registers[`REG_PCH], registers[`REG_PCL]} + 1
	191	`define EXEC_NEWCYCLE \
	192	newcycle <= 1; rd <= 1; wr <= 0
	193	casex (opcode)
81358c71 JW	194	`define EXECUTE
	195	`include "allinsns.v"
	196	`undef EXECUTE
1e03e021 JW	197	`INSN_RST: begin
1e03e021 JW	198	case (cycle)
abae5818	199	0: begin
69ca9b5f	200	`EXEC_INC_PC; // This goes FIRST in RST
abae5818	201	end
69ca9b5f	202	1: begin
1e03e021 JW	203	wr <= 1;
	204	address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
	205	wdata <= registers[`REG_PCH];
	206	end
69ca9b5f	207	2: begin
1e03e021 JW	208	wr <= 1;
	209	address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
	210	wdata <= registers[`REG_PCL];
	211	end
69ca9b5f	212	3: begin
1e03e021 JW	213	`EXEC_NEWCYCLE;
	214	{registers[`REG_PCH],registers[`REG_PCL]} <=
	215	{10'b0,opcode[5:3],3'b0};
	216	end
	217	endcase
	218	end
f26748f7	219	`INSN_RET,`INSN_RETCC: begin
abae5818 JW	220	case (cycle)
	221	0: begin
	222	rd <= 1;
	223	address <= {registers[`REG_SPH],registers[`REG_SPL]};
	224	end
611e4a90	225	1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret!
dadf7990 JW	226	`EXEC_INC_PC; // cycle 1 is skipped if we are not retcc
dadf7990 JW	227	case (opcode[4:3])
611e4a90 JW	228	`INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	229	`INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	230	`INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	231	`INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	232	endcase
	233	rd <= 1;
	234	address <= {registers[`REG_SPH],registers[`REG_SPL]};
	235	end
	236	2: begin
abae5818 JW	237	rd <= 1;
	238	address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
	239	end
611e4a90 JW	240	3: begin /* twiddle thumbs */ end
611e4a90 JW	241	4: begin
abae5818 JW	242	`EXEC_NEWCYCLE;
	243	// do NOT increment PC!
	244	end
	245	endcase
	246	end
6b4e2828	247	`INSN_CALL,`INSN_CALLCC: begin
ef6fbe31 JW	248	case (cycle)
	249	0: begin
	250	`EXEC_INC_PC;
	251	`EXEC_NEXTADDR_PCINC;
	252	rd <= 1;
	253	end
	254	1: begin
	255	`EXEC_INC_PC;
	256	`EXEC_NEXTADDR_PCINC;
	257	rd <= 1;
	258	end
	259	2: begin
4f9c2edf	260	`EXEC_INC_PC;
6b4e2828 JW	261	if (!opcode[0]) // i.e., is callcc
	262	/* We need to check the condition code to bail out. */
	263	case (opcode[4:3])
	264	`INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	265	`INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	266	`INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	267	`INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	268	endcase
4f9c2edf JW	269	end
4f9c2edf JW	270	3: begin
ef6fbe31 JW	271	address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
	272	wdata <= registers[`REG_PCH];
	273	wr <= 1;
	274	end
4f9c2edf	275	4: begin
ef6fbe31 JW	276	address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
	277	wdata <= registers[`REG_PCL];
	278	wr <= 1;
	279	end
ef6fbe31 JW	280	5: begin
	281	`EXEC_NEWCYCLE; /* do NOT increment the PC */
	282	end
	283	endcase
	284	end
a85b19a7 JW	285	`INSN_JP_imm,`INSN_JPCC_imm: begin
	286	case (cycle)
	287	0: begin
	288	`EXEC_INC_PC;
	289	`EXEC_NEXTADDR_PCINC;
	290	rd <= 1;
	291	end
	292	1: begin
	293	`EXEC_INC_PC;
	294	`EXEC_NEXTADDR_PCINC;
	295	rd <= 1;
	296	end
	297	2: begin
a00483d0	298	`EXEC_INC_PC;
a85b19a7 JW	299	if (!opcode[0]) begin // i.e., JP cc,nn
	300	/* We need to check the condition code to bail out. */
	301	case (opcode[4:3])
	302	`INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
a00483d0	303	`INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
a85b19a7	304	`INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
a00483d0	305	`INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
a85b19a7 JW	306	endcase
	307	end
	308	end
	309	3: begin
	310	`EXEC_NEWCYCLE;
	311	end
	312	endcase
	313	end
6b4e2828 JW	314	`INSN_JP_HL: begin
	315	`EXEC_NEWCYCLE;
	316	end
722e486a JW	317	`INSN_JR_imm,`INSN_JRCC_imm: begin
	318	case (cycle)
	319	0: begin
	320	`EXEC_INC_PC;
	321	`EXEC_NEXTADDR_PCINC;
	322	rd <= 1;
	323	end
	324	1: begin
	325	`EXEC_INC_PC;
	326	if (opcode[5]) begin // i.e., JP cc,nn
	327	/* We need to check the condition code to bail out. */
	328	case (opcode[4:3])
	329	`INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	330	`INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
	331	`INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	332	`INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
	333	endcase
	334	end
	335	end
	336	2: begin
	337	`EXEC_NEWCYCLE;
	338	end
	339	endcase
	340	end
dadf7990 JW	341	`INSN_INCDEC16: begin
	342	case (cycle)
	343	0: begin
	344	case (opcode[5:4])
	345	`INSN_reg16_BC: begin
	346	tmp <= registers[`REG_B];
	347	tmp2 <= registers[`REG_C];
	348	end
	349	`INSN_reg16_DE: begin
	350	tmp <= registers[`REG_D];
	351	tmp2 <= registers[`REG_E];
	352	end
	353	`INSN_reg16_HL: begin
	354	tmp <= registers[`REG_H];
	355	tmp2 <= registers[`REG_L];
	356	end
	357	`INSN_reg16_SP: begin
	358	tmp <= registers[`REG_SPH];
	359	tmp2 <= registers[`REG_SPL];
	360	end
	361	endcase
	362	end
	363	1: begin
	364	`EXEC_INC_PC;
	365	`EXEC_NEWCYCLE;
	366	end
	367	endcase
	368	end
f8db6448 JW	369	`INSN_VOP_INTR: begin
	370	case (cycle)
	371	0: begin
	372	address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
	373	wdata <= registers[`REG_PCH];
	374	wr <= 1;
	375	end
	376	1: begin
	377	address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
	378	wdata <= registers[`REG_PCL];
	379	wr <= 1;
	380	end
	381	2: begin
	382	`EXEC_NEWCYCLE;
	383	end
	384	endcase
	385	end
	386	`INSN_DI: begin
	387	`EXEC_NEWCYCLE;
	388	`EXEC_INC_PC;
	389	end
	390	`INSN_EI: begin
	391	`EXEC_NEWCYCLE;
	392	`EXEC_INC_PC;
	393	end
634ce02c JW	394	default:
634ce02c JW	395	$stop;
2f55f809 JW	396	endcase
	397	state <= `STATE_WRITEBACK;
	398	end
	399	`STATE_WRITEBACK: begin
	400	casex (opcode)
81358c71 JW	401	`define WRITEBACK
	402	`include "allinsns.v"
	403	`undef WRITEBACK
1e03e021 JW	404	`INSN_RST: begin
1e03e021 JW	405	case (cycle)
2e642f1f JW	406	0: begin /* type F */ end
	407	1: begin /* type F */ end
	408	2: begin /* type F */ end
	409	3: {registers[`REG_SPH],registers[`REG_SPL]} <=
	410	{registers[`REG_SPH],registers[`REG_SPL]}-2;
1e03e021 JW	411	endcase
1e03e021 JW	412	end
611e4a90	413	`INSN_RET,`INSN_RETCC: begin
abae5818	414	case (cycle)
f26748f7	415	0: if (opcode[0]) // i.e., not RETCC
611e4a90 JW	416	cycle <= 1; // Skip cycle 1; it gets incremented on the next round.
	417	1: begin /* Nothing need happen here. */ end
	418	2: registers[`REG_PCL] <= rdata;
	419	3: registers[`REG_PCH] <= rdata;
	420	4: begin
abae5818 JW	421	{registers[`REG_SPH],registers[`REG_SPL]} <=
abae5818 JW	422	{registers[`REG_SPH],registers[`REG_SPL]} + 2;
dadf7990	423	if (opcode[4] && opcode[0]) /* RETI */
abae5818 JW	424	ie <= 1;
	425	end
	426	endcase
	427	end
6b4e2828	428	`INSN_CALL,`INSN_CALLCC: begin
ef6fbe31	429	case (cycle)
2e642f1f JW	430	0: begin /* type F */ end
	431	1: tmp <= rdata; // tmp contains newpcl
	432	2: tmp2 <= rdata; // tmp2 contains newpch
	433	3: begin /* type F */ end
	434	4: registers[`REG_PCH] <= tmp2;
ef6fbe31 JW	435	5: begin
	436	{registers[`REG_SPH],registers[`REG_SPL]} <=
	437	{registers[`REG_SPH],registers[`REG_SPL]} - 2;
4f9c2edf	438	registers[`REG_PCL] <= tmp;
ef6fbe31 JW	439	end
	440	endcase
	441	end
a85b19a7 JW	442	`INSN_JP_imm,`INSN_JPCC_imm: begin
	443	case (cycle)
	444	0: begin /* type F */ end
	445	1: tmp <= rdata; // tmp contains newpcl
	446	2: tmp2 <= rdata; // tmp2 contains newpch
	447	3: {registers[`REG_PCH],registers[`REG_PCL]} <=
	448	{tmp2,tmp};
	449	endcase
	450	end
6b4e2828 JW	451	`INSN_JP_HL: begin
	452	{registers[`REG_PCH],registers[`REG_PCL]} <=
	453	{registers[`REG_H],registers[`REG_L]};
	454	end
722e486a JW	455	`INSN_JR_imm,`INSN_JRCC_imm: begin
	456	case (cycle)
	457	0: begin /* type F */ end
	458	1: tmp <= rdata;
	459	2: {registers[`REG_PCH],registers[`REG_PCL]} <=
	460	{registers[`REG_PCH],registers[`REG_PCL]} +
	461	{tmp[7]?8'hFF:8'h00,tmp};
	462	endcase
	463	end
dadf7990 JW	464	`INSN_INCDEC16: begin
	465	case (cycle)
	466	0: {tmp,tmp2} <= {tmp,tmp2} +
	467	(opcode[3] ? 16'hFFFF : 16'h0001);
	468	1: begin
	469	case (opcode[5:4])
	470	`INSN_reg16_BC: begin
	471	registers[`REG_B] <= tmp;
	472	registers[`REG_C] <= tmp2;
	473	end
	474	`INSN_reg16_DE: begin
	475	registers[`REG_D] <= tmp;
	476	registers[`REG_E] <= tmp2;
	477	end
	478	`INSN_reg16_HL: begin
	479	registers[`REG_H] <= tmp;
	480	registers[`REG_L] <= tmp2;
	481	end
	482	`INSN_reg16_SP: begin
	483	registers[`REG_SPH] <= tmp;
	484	registers[`REG_SPL] <= tmp2;
	485	end
	486	endcase
	487	end
	488	endcase
	489	end
f8db6448 JW	490	`INSN_VOP_INTR: begin
	491	case (cycle)
	492	0: begin end
9c834ff2	493	1: begin end
f8db6448 JW	494	2: begin
	495	ie <= 0;
	496	{registers[`REG_PCH],registers[`REG_PCL]} <=
	497	{8'b0,jaddr};
9c834ff2 JW	498	{registers[`REG_SPH],registers[`REG_SPL]} <=
9c834ff2 JW	499	{registers[`REG_SPH],registers[`REG_SPL]} - 2;
f8db6448 JW	500	end
	501	endcase
	502	end
	503	`INSN_DI: ie <= 0;
	504	`INSN_EI: iedelay <= 1;
ef6fbe31 JW	505	default:
ef6fbe31 JW	506	$stop;
2f55f809 JW	507	endcase
	508	state <= `STATE_FETCH;
	509	end
	510	endcase
	511	endmodule