[fpgaboy.git] / GBZ80Core.v

`define REG_A	0
`define REG_B	1
`define REG_C	2
`define REG_D	3
`define REG_E	4
`define REG_F	5
`define REG_H	6
`define REG_L	7
`define REG_SPH	8
`define REG_SPL	9
`define REG_PCH	10
`define REG_PCL	11

`define _A	registers[`REG_A]
`define _B	registers[`REG_B]
`define _C	registers[`REG_C]
`define _D	registers[`REG_D]
`define _E	registers[`REG_E]
`define _F	registers[`REG_F]
`define _H	registers[`REG_H]
`define _L	registers[`REG_L]
`define _SPH	registers[`REG_SPH]
`define _SPL	registers[`REG_SPL]
`define _PCH	registers[`REG_PCH]
`define _PCL	registers[`REG_PCL]
`define _AF	{`_A, `_F}
`define _BC	{`_B, `_C}
`define _DE	{`_D, `_E}
`define _HL	{`_H, `_L}
`define _SP	{`_SPH, `_SPL}
`define _PC	{`_PCH, `_PCL}

`define FLAG_Z	8'b10000000
`define FLAG_N	8'b01000000
`define FLAG_H	8'b00100000
`define FLAG_C	8'b00010000

`define STATE_FETCH		2'h0
`define STATE_DECODE		2'h1
`define STATE_EXECUTE		2'h2
`define STATE_WRITEBACK		2'h3

`define INSN_LD_reg_imm8	9'b000xxx110
`define INSN_HALT		9'b001110110
`define INSN_LD_HL_reg		9'b001110xxx
`define INSN_LD_reg_HL		9'b001xxx110
`define INSN_LD_reg_reg		9'b001xxxxxx
`define INSN_LD_reg_imm16	9'b000xx0001
`define INSN_LD_SP_HL		9'b011111001
`define INSN_PUSH_reg		9'b011xx0101
`define INSN_POP_reg		9'b011xx0001
`define INSN_LDH_AC		9'b0111x0010	// Either LDH A,(C) or LDH (C),A
`define INSN_LDx_AHL		9'b0001xx010	// LDD/LDI A,(HL) / (HL),A
`define INSN_ALU8		9'b010xxxxxx	// 10 xxx yyy
`define INSN_ALU8IMM		9'b011xxx110
`define INSN_NOP		9'b000000000
`define INSN_RST		9'b011xxx111
`define INSN_RET		9'b0110x1001	// 1 = RETI, 0 = RET
`define INSN_RETCC		9'b0110xx000
`define INSN_CALL		9'b011001101
`define INSN_CALLCC		9'b0110xx100	// Not that call/cc.
`define INSN_JP_imm		9'b011000011
`define INSN_JPCC_imm		9'b0110xx010
`define INSN_ALU_A		9'b000xxx111
`define INSN_JP_HL		9'b011101001
`define INSN_JR_imm		9'b000011000
`define INSN_JRCC_imm		9'b0001xx000
`define INSN_INCDEC16		9'b000xxx011
`define INSN_VOP_INTR		9'b011111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
`define INSN_DI			9'b011110011
`define INSN_EI			9'b011111011
`define INSN_INCDEC_HL		9'b00011010x
`define INSN_INCDEC_reg8	9'b000xxx10x
`define INSN_LD8M_A		9'b0111x0000	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
`define INSN_LD16M_A		9'b0111x1010	// 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
`define INSN_LDBCDE_A		9'b0000xx010
`define INSN_TWO_BYTE		9'b011001011    // prefix for two-byte opqodes
`define INSN_ALU_EXT		9'b100xxxxxx
`define INSN_BIT		9'b101xxxxxx
`define INSN_RES		9'b110xxxxxx
`define INSN_SET		9'b111xxxxxx

`define INSN_cc_NZ		2'b00
`define INSN_cc_Z		2'b01
`define INSN_cc_NC		2'b10
`define INSN_cc_C		2'b11

`define INSN_reg_A		3'b111
`define INSN_reg_B		3'b000
`define INSN_reg_C		3'b001
`define INSN_reg_D		3'b010
`define INSN_reg_E		3'b011
`define INSN_reg_H		3'b100
`define INSN_reg_L		3'b101
`define INSN_reg_dHL		3'b110
`define INSN_reg16_BC		2'b00
`define INSN_reg16_DE		2'b01
`define INSN_reg16_HL		2'b10
`define INSN_reg16_SP		2'b11
`define INSN_stack_AF		2'b11
`define INSN_stack_BC		2'b00
`define INSN_stack_DE		2'b01
`define INSN_stack_HL		2'b10
`define INSN_alu_ADD		3'b000
`define INSN_alu_ADC		3'b001
`define INSN_alu_SUB		3'b010
`define INSN_alu_SBC		3'b011
`define INSN_alu_AND		3'b100
`define INSN_alu_XOR		3'b101
`define INSN_alu_OR		3'b110
`define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
`define INSN_alu_RLCA		3'b000
`define INSN_alu_RRCA		3'b001
`define INSN_alu_RLA		3'b010
`define INSN_alu_RRA		3'b011
`define INSN_alu_DAA		3'b100
`define INSN_alu_CPL		3'b101
`define INSN_alu_SCF		3'b110
`define INSN_alu_CCF		3'b111
`define INSN_alu_RLC		3'b000
`define INSN_alu_RRC		3'b001
`define INSN_alu_RL		3'b010
`define INSN_alu_RR		3'b011
`define INSN_alu_DA_SLA		3'b100
`define INSN_alu_CPL_SRA	3'b101
`define INSN_alu_SCF_SWAP	3'b110
`define INSN_alu_CCF_SRL	3'b111

`define EXEC_INC_PC 		`_PC <= `_PC + 1;
`define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
`define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
`define EXEC_NEWCYCLE_TWOBYTE	begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end

module GBZ80Core(
	input clk,
	output reg [15:0] busaddress,	/* BUS_* is latched on STATE_FETCH. */
	inout [7:0] busdata,
	output reg buswr, output reg busrd,
	input irq, input [7:0] jaddr,
	output reg [1:0] state);

//	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
	reg [2:0] cycle;					/* Cycle for instructions. */
	
	reg [7:0] registers[11:0];
	
	reg [15:0] address;				/* Address for the next bus operation. */
	
	reg [8:0] opcode;				/* Opcode from the current machine cycle. */

	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
	reg rd, wr, newcycle, twobyte;
	
	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
	
	reg [7:0] buswdata;
	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;

	reg ie, iedelay;

	wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
	wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
	wire [7:0] alu_res;
	wire [3:0] f_res;

	assign rlc   = {tmp[6:0],tmp[7]};
	assign rlcf  = {(tmp == 0 ? 1'b1 : 1'b0)
			,2'b0,
			tmp[7]};

	assign rrc   = {tmp[0],tmp[7:1]};
	assign rrcf  = {(tmp == 0 ? 1'b1 : 1'b0),
			2'b0,
			tmp[0]};

	assign rl    = {tmp[6:0],`_F[4]};
	assign rlf   = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
			2'b0,
			tmp[7]};

	assign rr    = {`_F[4],tmp[7:1]};
	assign rrf   = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
			2'b0,
			tmp[0]};

	assign sla   = {tmp[6:0],0};
	assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
			2'b0,
			tmp[7]};

	assign sra   = {tmp[7],tmp[7:1]};
//	assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =

	assign swap  = {tmp[3:0],tmp[7:4]};
	assign swapf = {(tmp == 0 ? 1'b1 : 1'b0),
			3'b0};

	assign srl   = {0,tmp[7:1]};
	assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
			2'b0,
			tmp[0]};
	assign sraf  = srlf;

	/*  Y U Q  */
	assign {alu_res,f_res} =
		opcode[5] ? (
			opcode[4] ? (
				opcode[3] ? {srl,srlf} : {swap,swapf}
			) : (
				opcode[3] ? {sra,sraf} : {sla,slaf}
			)
		) : (
			opcode[4] ? (
				opcode[3] ? {rr,rrf} : {rl,rlf}
			) : (
				opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
			)
		);

	initial begin
		registers[ 0] <= 0;
		registers[ 1] <= 0;
		registers[ 2] <= 0;
		registers[ 3] <= 0;
		registers[ 4] <= 0;
		registers[ 5] <= 0;
		registers[ 6] <= 0;
		registers[ 7] <= 0;
		registers[ 8] <= 0;
		registers[ 9] <= 0;
		registers[10] <= 0;
		registers[11] <= 0;
		rd <= 1;
		wr <= 0;
		newcycle <= 1;
		state <= 0;
		cycle <= 0;
		busrd <= 0;
		buswr <= 0;
		busaddress <= 0;
		ie <= 0;
		iedelay <= 0;
		opcode <= 0;
		state <= `STATE_WRITEBACK;
		cycle <= 0;
		twobyte <= 0;
	end

	always @(posedge clk)
		case (state)
		`STATE_FETCH: begin
			if (newcycle) begin
				busaddress <= `_PC;
				buswr <= 0;
				busrd <= 1;
			end else begin
				busaddress <= address;
				buswr <= wr;
				busrd <= rd;
				if (wr)
					buswdata <= wdata;
			end
			state <= `STATE_DECODE;
		end
		`STATE_DECODE: begin
			if (newcycle) begin
				if (twobyte) begin
					opcode <= {1,busdata};
					twobyte <= 0;
				end else if (ie && irq)
					opcode <= `INSN_VOP_INTR;
				else
					opcode <= {0,busdata};
				rdata <= busdata;
				newcycle <= 0;
				cycle <= 0;
			end else begin
				if (rd) rdata <= busdata;
				cycle <= cycle + 1;
			end
			if (iedelay) begin
				ie <= 1;
				iedelay <= 0;
			end
			buswr <= 0;
			busrd <= 0;
			wr <= 0;
			rd <= 0;
			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
			wdata <= 8'bxxxxxxxx;
			state <= `STATE_EXECUTE;
		end
		`STATE_EXECUTE: begin
			casex (opcode)
			`define EXECUTE
			`include "allinsns.v"
			`undef EXECUTE
			default:
				$stop;
			endcase
			state <= `STATE_WRITEBACK;
		end
		`STATE_WRITEBACK: begin
			casex (opcode)
			`define WRITEBACK
			`include "allinsns.v"
			`undef WRITEBACK
			default:
				$stop;
			endcase
			state <= `STATE_FETCH;
		end
		endcase
endmodule
Commit	Line	Data
df770340 JW	1	`define REG_A 0
	2	`define REG_B 1
	3	`define REG_C 2
	4	`define REG_D 3
	5	`define REG_E 4
	6	`define REG_F 5
	7	`define REG_H 6
	8	`define REG_L 7
	9	`define REG_SPH 8
	10	`define REG_SPL 9
	11	`define REG_PCH 10
	12	`define REG_PCL 11
2f55f809	13
5509558d JW	14	`define _A registers[`REG_A]
	15	`define _B registers[`REG_B]
	16	`define _C registers[`REG_C]
	17	`define _D registers[`REG_D]
	18	`define _E registers[`REG_E]
	19	`define _F registers[`REG_F]
	20	`define _H registers[`REG_H]
	21	`define _L registers[`REG_L]
	22	`define _SPH registers[`REG_SPH]
	23	`define _SPL registers[`REG_SPL]
	24	`define _PCH registers[`REG_PCH]
	25	`define _PCL registers[`REG_PCL]
	26	`define _AF {`_A, `_F}
	27	`define _BC {`_B, `_C}
	28	`define _DE {`_D, `_E}
	29	`define _HL {`_H, `_L}
	30	`define _SP {`_SPH, `_SPL}
	31	`define _PC {`_PCH, `_PCL}
	32
df770340 JW	33	`define FLAG_Z 8'b10000000
	34	`define FLAG_N 8'b01000000
	35	`define FLAG_H 8'b00100000
	36	`define FLAG_C 8'b00010000
2f55f809	37
df770340 JW	38	`define STATE_FETCH 2'h0
df770340 JW	39	`define STATE_DECODE 2'h1
2f55f809 JW	40	`define STATE_EXECUTE 2'h2
	41	`define STATE_WRITEBACK 2'h3
	42
decafd62 JW	43	`define INSN_LD_reg_imm8 9'b000xxx110
	44	`define INSN_HALT 9'b001110110
	45	`define INSN_LD_HL_reg 9'b001110xxx
	46	`define INSN_LD_reg_HL 9'b001xxx110
	47	`define INSN_LD_reg_reg 9'b001xxxxxx
	48	`define INSN_LD_reg_imm16 9'b000xx0001
	49	`define INSN_LD_SP_HL 9'b011111001
	50	`define INSN_PUSH_reg 9'b011xx0101
	51	`define INSN_POP_reg 9'b011xx0001
	52	`define INSN_LDH_AC 9'b0111x0010 // Either LDH A,(C) or LDH (C),A
	53	`define INSN_LDx_AHL 9'b0001xx010 // LDD/LDI A,(HL) / (HL),A
	54	`define INSN_ALU8 9'b010xxxxxx // 10 xxx yyy
	55	`define INSN_ALU8IMM 9'b011xxx110
	56	`define INSN_NOP 9'b000000000
	57	`define INSN_RST 9'b011xxx111
	58	`define INSN_RET 9'b0110x1001 // 1 = RETI, 0 = RET
	59	`define INSN_RETCC 9'b0110xx000
	60	`define INSN_CALL 9'b011001101
	61	`define INSN_CALLCC 9'b0110xx100 // Not that call/cc.
	62	`define INSN_JP_imm 9'b011000011
	63	`define INSN_JPCC_imm 9'b0110xx010
	64	`define INSN_ALU_A 9'b000xxx111
	65	`define INSN_JP_HL 9'b011101001
	66	`define INSN_JR_imm 9'b000011000
	67	`define INSN_JRCC_imm 9'b0001xx000
	68	`define INSN_INCDEC16 9'b000xxx011
	69	`define INSN_VOP_INTR 9'b011111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
	70	`define INSN_DI 9'b011110011
	71	`define INSN_EI 9'b011111011
	72	`define INSN_INCDEC_HL 9'b00011010x
	73	`define INSN_INCDEC_reg8 9'b000xxx10x
	74	`define INSN_LD8M_A 9'b0111x0000 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
	75	`define INSN_LD16M_A 9'b0111x1010 // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
	76	`define INSN_LDBCDE_A 9'b0000xx010
	77	`define INSN_TWO_BYTE 9'b011001011 // prefix for two-byte opqodes
	78	`define INSN_ALU_EXT 9'b100xxxxxx
	79	`define INSN_BIT 9'b101xxxxxx
	80	`define INSN_RES 9'b110xxxxxx
	81	`define INSN_SET 9'b111xxxxxx
a85b19a7	82
df770340 JW	83	`define INSN_cc_NZ 2'b00
	84	`define INSN_cc_Z 2'b01
	85	`define INSN_cc_NC 2'b10
	86	`define INSN_cc_C 2'b11
fa136d63	87
b85870e0 JW	88	`define INSN_reg_A 3'b111
	89	`define INSN_reg_B 3'b000
	90	`define INSN_reg_C 3'b001
	91	`define INSN_reg_D 3'b010
	92	`define INSN_reg_E 3'b011
	93	`define INSN_reg_H 3'b100
	94	`define INSN_reg_L 3'b101
df770340 JW	95	`define INSN_reg_dHL 3'b110
	96	`define INSN_reg16_BC 2'b00
	97	`define INSN_reg16_DE 2'b01
	98	`define INSN_reg16_HL 2'b10
	99	`define INSN_reg16_SP 2'b11
	100	`define INSN_stack_AF 2'b11
	101	`define INSN_stack_BC 2'b00
	102	`define INSN_stack_DE 2'b01
	103	`define INSN_stack_HL 2'b10
94522011 JW	104	`define INSN_alu_ADD 3'b000
	105	`define INSN_alu_ADC 3'b001
	106	`define INSN_alu_SUB 3'b010
	107	`define INSN_alu_SBC 3'b011
	108	`define INSN_alu_AND 3'b100
	109	`define INSN_alu_XOR 3'b101
	110	`define INSN_alu_OR 3'b110
	111	`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
a00483d0 JW	112	`define INSN_alu_RLCA 3'b000
	113	`define INSN_alu_RRCA 3'b001
	114	`define INSN_alu_RLA 3'b010
	115	`define INSN_alu_RRA 3'b011
	116	`define INSN_alu_DAA 3'b100
	117	`define INSN_alu_CPL 3'b101
	118	`define INSN_alu_SCF 3'b110
	119	`define INSN_alu_CCF 3'b111
decafd62 JW	120	`define INSN_alu_RLC 3'b000
	121	`define INSN_alu_RRC 3'b001
	122	`define INSN_alu_RL 3'b010
	123	`define INSN_alu_RR 3'b011
	124	`define INSN_alu_DA_SLA 3'b100
	125	`define INSN_alu_CPL_SRA 3'b101
	126	`define INSN_alu_SCF_SWAP 3'b110
	127	`define INSN_alu_CCF_SRL 3'b111
94522011	128
5c33c5c0 JW	129	`define EXEC_INC_PC `_PC <= `_PC + 1;
	130	`define EXEC_NEXTADDR_PCINC address <= `_PC + 1;
	131	`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end
decafd62	132	`define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
5c33c5c0 JW	133	`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
5c33c5c0 JW	134	`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
5509558d	135
2f55f809 JW	136	module GBZ80Core(
2f55f809 JW	137	input clk,
eb0f2fe1	138	output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
2f55f809	139	inout [7:0] busdata,
eb0f2fe1	140	output reg buswr, output reg busrd,
6c46357c JW	141	input irq, input [7:0] jaddr,
6c46357c JW	142	output reg [1:0] state);
decafd62	143
6c46357c	144	// reg [1:0] state; /* State within this bus cycle (see STATE_). /
9c834ff2	145	reg [2:0] cycle; /* Cycle for instructions. */
2f55f809 JW	146
	147	reg [7:0] registers[11:0];
	148
	149	reg [15:0] address; /* Address for the next bus operation. */
	150
decafd62 JW	151	reg [8:0] opcode; /* Opcode from the current machine cycle. */
decafd62 JW	152
2f55f809	153	reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
decafd62	154	reg rd, wr, newcycle, twobyte;
2f55f809	155
ef6fbe31	156	reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0	157
2f55f809 JW	158	reg [7:0] buswdata;
2f55f809 JW	159	assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
decafd62	160
eb0f2fe1	161	reg ie, iedelay;
decafd62 JW	162
	163	wire [7:0] rlc,rrc,rl,rr,sla,sra,swap,srl;
	164	wire [3:0] rlcf,rrcf,rlf,rrf,slaf,sraf,swapf,srlf;
	165	wire [7:0] alu_res;
	166	wire [3:0] f_res;
	167
	168	assign rlc = {tmp[6:0],tmp[7]};
	169	assign rlcf = {(tmp == 0 ? 1'b1 : 1'b0)
	170	,2'b0,
	171	tmp[7]};
	172
	173	assign rrc = {tmp[0],tmp[7:1]};
	174	assign rrcf = {(tmp == 0 ? 1'b1 : 1'b0),
	175	2'b0,
	176	tmp[0]};
	177
	178	assign rl = {tmp[6:0],`_F[4]};
	179	assign rlf = {({tmp[6:0],`_F[4]} == 0 ? 1'b1 : 1'b0),
	180	2'b0,
	181	tmp[7]};
	182
	183	assign rr = {`_F[4],tmp[7:1]};
	184	assign rrf = {({tmp[4],tmp[7:1]} == 0 ? 1'b1 : 1'b0),
	185	2'b0,
	186	tmp[0]};
	187
	188	assign sla = {tmp[6:0],0};
	189	assign slaf = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
	190	2'b0,
	191	tmp[7]};
	192
	193	assign sra = {tmp[7],tmp[7:1]};
	194	// assign sraf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]}; now in assign srlf =
	195
	196	assign swap = {tmp[3:0],tmp[7:4]};
	197	assign swapf = {(tmp == 0 ? 1'b1 : 1'b0),
	198	3'b0};
	199
	200	assign srl = {0,tmp[7:1]};
	201	assign srlf = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
	202	2'b0,
	203	tmp[0]};
	204	assign sraf = srlf;
	205
	206	/* Y U Q */
	207	assign {alu_res,f_res} =
	208	opcode[5] ? (
	209	opcode[4] ? (
	210	opcode[3] ? {srl,srlf} : {swap,swapf}
	211	) : (
	212	opcode[3] ? {sra,sraf} : {sla,slaf}
	213	)
	214	) : (
	215	opcode[4] ? (
	216	opcode[3] ? {rr,rrf} : {rl,rlf}
	217	) : (
	218	opcode[3] ? {rrc,rrcf} : {rlc,rlcf}
	219	)
	220	);
	221
2f55f809	222	initial begin
241c995c JW	223	registers[ 0] <= 0;
	224	registers[ 1] <= 0;
	225	registers[ 2] <= 0;
	226	registers[ 3] <= 0;
	227	registers[ 4] <= 0;
	228	registers[ 5] <= 0;
	229	registers[ 6] <= 0;
	230	registers[ 7] <= 0;
	231	registers[ 8] <= 0;
	232	registers[ 9] <= 0;
	233	registers[10] <= 0;
	234	registers[11] <= 0;
2e642f1f JW	235	rd <= 1;
	236	wr <= 0;
	237	newcycle <= 1;
	238	state <= 0;
	239	cycle <= 0;
f8db6448 JW	240	busrd <= 0;
	241	buswr <= 0;
	242	busaddress <= 0;
9c834ff2	243	ie <= 0;
f8db6448	244	iedelay <= 0;
9c834ff2 JW	245	opcode <= 0;
	246	state <= `STATE_WRITEBACK;
	247	cycle <= 0;
decafd62	248	twobyte <= 0;
2f55f809 JW	249	end
	250
	251	always @(posedge clk)
	252	case (state)
	253	`STATE_FETCH: begin
2e642f1f	254	if (newcycle) begin
decafd62	255	busaddress <= `_PC;
2e642f1f JW	256	buswr <= 0;
	257	busrd <= 1;
	258	end else begin
2f55f809	259	busaddress <= address;
2e642f1f JW	260	buswr <= wr;
	261	busrd <= rd;
	262	if (wr)
	263	buswdata <= wdata;
	264	end
2f55f809 JW	265	state <= `STATE_DECODE;
	266	end
	267	`STATE_DECODE: begin
	268	if (newcycle) begin
decafd62 JW	269	if (twobyte) begin
	270	opcode <= {1,busdata};
	271	twobyte <= 0;
	272	end else if (ie && irq)
f8db6448 JW	273	opcode <= `INSN_VOP_INTR;
f8db6448 JW	274	else
decafd62	275	opcode <= {0,busdata};
2f55f809	276	rdata <= busdata;
b85870e0	277	newcycle <= 0;
2f55f809	278	cycle <= 0;
2e642f1f	279	end else begin
2f55f809	280	if (rd) rdata <= busdata;
2e642f1f JW	281	cycle <= cycle + 1;
2e642f1f JW	282	end
f8db6448 JW	283	if (iedelay) begin
	284	ie <= 1;
	285	iedelay <= 0;
	286	end
2f55f809 JW	287	buswr <= 0;
2f55f809 JW	288	busrd <= 0;
97649fed JW	289	wr <= 0;
	290	rd <= 0;
	291	address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
	292	wdata <= 8'bxxxxxxxx;
2f55f809 JW	293	state <= `STATE_EXECUTE;
	294	end
	295	`STATE_EXECUTE: begin
2f55f809	296	casex (opcode)
81358c71 JW	297	`define EXECUTE
	298	`include "allinsns.v"
	299	`undef EXECUTE
634ce02c JW	300	default:
634ce02c JW	301	$stop;
2f55f809 JW	302	endcase
	303	state <= `STATE_WRITEBACK;
	304	end
	305	`STATE_WRITEBACK: begin
	306	casex (opcode)
81358c71 JW	307	`define WRITEBACK
	308	`include "allinsns.v"
	309	`undef WRITEBACK
ef6fbe31 JW	310	default:
ef6fbe31 JW	311	$stop;
2f55f809 JW	312	endcase
	313	state <= `STATE_FETCH;
	314	end
	315	endcase
	316	endmodule