Cleanups to make code nicer looking. ALU subtraction fixes.
[fpgaboy.git] / GBZ80Core.v
CommitLineData
df770340
JW
1`define REG_A 0
2`define REG_B 1
3`define REG_C 2
4`define REG_D 3
5`define REG_E 4
6`define REG_F 5
7`define REG_H 6
8`define REG_L 7
9`define REG_SPH 8
10`define REG_SPL 9
11`define REG_PCH 10
12`define REG_PCL 11
2f55f809 13
5509558d
JW
14`define _A registers[`REG_A]
15`define _B registers[`REG_B]
16`define _C registers[`REG_C]
17`define _D registers[`REG_D]
18`define _E registers[`REG_E]
19`define _F registers[`REG_F]
20`define _H registers[`REG_H]
21`define _L registers[`REG_L]
22`define _SPH registers[`REG_SPH]
23`define _SPL registers[`REG_SPL]
24`define _PCH registers[`REG_PCH]
25`define _PCL registers[`REG_PCL]
26`define _AF {`_A, `_F}
27`define _BC {`_B, `_C}
28`define _DE {`_D, `_E}
29`define _HL {`_H, `_L}
30`define _SP {`_SPH, `_SPL}
31`define _PC {`_PCH, `_PCL}
32
df770340
JW
33`define FLAG_Z 8'b10000000
34`define FLAG_N 8'b01000000
35`define FLAG_H 8'b00100000
36`define FLAG_C 8'b00010000
2f55f809 37
df770340
JW
38`define STATE_FETCH 2'h0
39`define STATE_DECODE 2'h1
2f55f809
JW
40`define STATE_EXECUTE 2'h2
41`define STATE_WRITEBACK 2'h3
42
43`define INSN_LD_reg_imm8 8'b00xxx110
df770340 44`define INSN_HALT 8'b01110110
b85870e0
JW
45`define INSN_LD_HL_reg 8'b01110xxx
46`define INSN_LD_reg_HL 8'b01xxx110
47`define INSN_LD_reg_reg 8'b01xxxxxx
634ce02c
JW
48`define INSN_LD_reg_imm16 8'b00xx0001
49`define INSN_LD_SP_HL 8'b11111001
97649fed 50`define INSN_PUSH_reg 8'b11xx0101
df770340
JW
51`define INSN_POP_reg 8'b11xx0001
52`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A
53`define INSN_LDx_AHL 8'b001xx010 // LDD/LDI A,(HL) / (HL),A
54`define INSN_ALU8 8'b10xxxxxx // 10 xxx yyy
55`define INSN_NOP 8'b00000000
56`define INSN_RST 8'b11xxx111
57`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
58`define INSN_RETCC 8'b110xx000
59`define INSN_CALL 8'b11001101
60`define INSN_CALLCC 8'b110xx100 // Not that call/cc.
61`define INSN_JP_imm 8'b11000011
a85b19a7 62`define INSN_JPCC_imm 8'b110xx010
a00483d0 63`define INSN_ALU_A 8'b00xxx111
df770340
JW
64`define INSN_JP_HL 8'b11101001
65`define INSN_JR_imm 8'b00011000
722e486a 66`define INSN_JRCC_imm 8'b001xx000
dadf7990 67`define INSN_INCDEC16 8'b00xxx011
f8db6448 68`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
df770340
JW
69`define INSN_DI 8'b11110011
70`define INSN_EI 8'b11111011
a85b19a7 71
df770340
JW
72`define INSN_cc_NZ 2'b00
73`define INSN_cc_Z 2'b01
74`define INSN_cc_NC 2'b10
75`define INSN_cc_C 2'b11
fa136d63 76
b85870e0
JW
77`define INSN_reg_A 3'b111
78`define INSN_reg_B 3'b000
79`define INSN_reg_C 3'b001
80`define INSN_reg_D 3'b010
81`define INSN_reg_E 3'b011
82`define INSN_reg_H 3'b100
83`define INSN_reg_L 3'b101
df770340
JW
84`define INSN_reg_dHL 3'b110
85`define INSN_reg16_BC 2'b00
86`define INSN_reg16_DE 2'b01
87`define INSN_reg16_HL 2'b10
88`define INSN_reg16_SP 2'b11
89`define INSN_stack_AF 2'b11
90`define INSN_stack_BC 2'b00
91`define INSN_stack_DE 2'b01
92`define INSN_stack_HL 2'b10
94522011
JW
93`define INSN_alu_ADD 3'b000
94`define INSN_alu_ADC 3'b001
95`define INSN_alu_SUB 3'b010
96`define INSN_alu_SBC 3'b011
97`define INSN_alu_AND 3'b100
98`define INSN_alu_XOR 3'b101
99`define INSN_alu_OR 3'b110
100`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
a00483d0
JW
101`define INSN_alu_RLCA 3'b000
102`define INSN_alu_RRCA 3'b001
103`define INSN_alu_RLA 3'b010
104`define INSN_alu_RRA 3'b011
105`define INSN_alu_DAA 3'b100
106`define INSN_alu_CPL 3'b101
107`define INSN_alu_SCF 3'b110
108`define INSN_alu_CCF 3'b111
94522011 109
5509558d
JW
110`define EXEC_INC_PC \
111 `_PC <= `_PC + 1
112`define EXEC_NEXTADDR_PCINC \
113 address <= `_PC + 1
114`define EXEC_NEWCYCLE \
115 begin newcycle <= 1; rd <= 1; wr <= 0; end
116`define EXEC_WRITE(ad, da) \
117 begin address <= (ad); \
118 wdata <= (da); \
119 wr <= 1; end
120`define EXEC_READ(ad) \
121 begin address <= (ad); \
122 rd <= 1; end
123
2f55f809
JW
124module GBZ80Core(
125 input clk,
eb0f2fe1 126 output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
2f55f809 127 inout [7:0] busdata,
eb0f2fe1 128 output reg buswr, output reg busrd,
f8db6448 129 input irq, input [7:0] jaddr);
2f55f809 130
9c834ff2
JW
131 reg [1:0] state; /* State within this bus cycle (see STATE_*). */
132 reg [2:0] cycle; /* Cycle for instructions. */
2f55f809
JW
133
134 reg [7:0] registers[11:0];
135
136 reg [15:0] address; /* Address for the next bus operation. */
137
138 reg [7:0] opcode; /* Opcode from the current machine cycle. */
139
140 reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
9c834ff2 141 reg rd, wr, newcycle;
2f55f809 142
ef6fbe31 143 reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0 144
2f55f809
JW
145 reg [7:0] buswdata;
146 assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
147
eb0f2fe1 148 reg ie, iedelay;
abae5818 149
2f55f809 150 initial begin
241c995c
JW
151 registers[ 0] <= 0;
152 registers[ 1] <= 0;
153 registers[ 2] <= 0;
154 registers[ 3] <= 0;
155 registers[ 4] <= 0;
156 registers[ 5] <= 0;
157 registers[ 6] <= 0;
158 registers[ 7] <= 0;
159 registers[ 8] <= 0;
160 registers[ 9] <= 0;
161 registers[10] <= 0;
162 registers[11] <= 0;
2e642f1f
JW
163 rd <= 1;
164 wr <= 0;
165 newcycle <= 1;
166 state <= 0;
167 cycle <= 0;
f8db6448
JW
168 busrd <= 0;
169 buswr <= 0;
170 busaddress <= 0;
9c834ff2 171 ie <= 0;
f8db6448 172 iedelay <= 0;
9c834ff2
JW
173 opcode <= 0;
174 state <= `STATE_WRITEBACK;
175 cycle <= 0;
2f55f809
JW
176 end
177
178 always @(posedge clk)
179 case (state)
180 `STATE_FETCH: begin
2e642f1f 181 if (newcycle) begin
2f55f809 182 busaddress <= {registers[`REG_PCH], registers[`REG_PCL]};
2e642f1f
JW
183 buswr <= 0;
184 busrd <= 1;
185 end else begin
2f55f809 186 busaddress <= address;
2e642f1f
JW
187 buswr <= wr;
188 busrd <= rd;
189 if (wr)
190 buswdata <= wdata;
191 end
2f55f809
JW
192 state <= `STATE_DECODE;
193 end
194 `STATE_DECODE: begin
195 if (newcycle) begin
f8db6448
JW
196 if (ie && irq)
197 opcode <= `INSN_VOP_INTR;
198 else
199 opcode <= busdata;
2f55f809 200 rdata <= busdata;
b85870e0 201 newcycle <= 0;
2f55f809 202 cycle <= 0;
2e642f1f 203 end else begin
2f55f809 204 if (rd) rdata <= busdata;
2e642f1f
JW
205 cycle <= cycle + 1;
206 end
f8db6448
JW
207 if (iedelay) begin
208 ie <= 1;
209 iedelay <= 0;
210 end
2f55f809
JW
211 buswr <= 0;
212 busrd <= 0;
97649fed
JW
213 wr <= 0;
214 rd <= 0;
215 address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
216 wdata <= 8'bxxxxxxxx;
2f55f809
JW
217 state <= `STATE_EXECUTE;
218 end
219 `STATE_EXECUTE: begin
5509558d 220
2f55f809 221 casex (opcode)
81358c71
JW
222 `define EXECUTE
223 `include "allinsns.v"
224 `undef EXECUTE
f8db6448
JW
225 `INSN_DI: begin
226 `EXEC_NEWCYCLE;
227 `EXEC_INC_PC;
228 end
229 `INSN_EI: begin
230 `EXEC_NEWCYCLE;
231 `EXEC_INC_PC;
232 end
634ce02c
JW
233 default:
234 $stop;
2f55f809
JW
235 endcase
236 state <= `STATE_WRITEBACK;
237 end
238 `STATE_WRITEBACK: begin
239 casex (opcode)
81358c71
JW
240 `define WRITEBACK
241 `include "allinsns.v"
242 `undef WRITEBACK
ef6fbe31
JW
243 default:
244 $stop;
2f55f809
JW
245 endcase
246 state <= `STATE_FETCH;
247 end
248 endcase
249endmodule
This page took 0.058762 seconds and 4 git commands to generate.