[fpgaboy.git] / core / GBZ80Core.v

`define REG_A	0
`define REG_B	1
`define REG_C	2
`define REG_D	3
`define REG_E	4
`define REG_F	5
`define REG_H	6
`define REG_L	7
`define REG_SPH	8
`define REG_SPL	9
`define REG_PCH	10
`define REG_PCL	11

`define _A	registers[`REG_A]
`define _B	registers[`REG_B]
`define _C	registers[`REG_C]
`define _D	registers[`REG_D]
`define _E	registers[`REG_E]
`define _F	registers[`REG_F]
`define _H	registers[`REG_H]
`define _L	registers[`REG_L]
`define _SPH	registers[`REG_SPH]
`define _SPL	registers[`REG_SPL]
`define _PCH	registers[`REG_PCH]
`define _PCL	registers[`REG_PCL]
`define _AF	{`_A, `_F}
`define _BC	{`_B, `_C}
`define _DE	{`_D, `_E}
`define _HL	{`_H, `_L}
`define _SP	{`_SPH, `_SPL}
`define _PC	{`_PCH, `_PCL}

`define FLAG_Z	8'b10000000
`define FLAG_N	8'b01000000
`define FLAG_H	8'b00100000
`define FLAG_C	8'b00010000

`define STATE_FETCH		2'h0
`define STATE_DECODE		2'h1
`define STATE_EXECUTE		2'h2
`define STATE_WRITEBACK		2'h3

`define INSN_VOP_INTR		9'b011111100	// 0xFC is grabbed by the fetch if there is an interrupt pending.
`define INSN_RES		9'b110xxxxxx
`define INSN_SET		9'b111xxxxxx

`define INSN_cc_NZ		2'b00
`define INSN_cc_Z		2'b01
`define INSN_cc_NC		2'b10
`define INSN_cc_C		2'b11

`define INSN_reg_A		3'b111
`define INSN_reg_B		3'b000
`define INSN_reg_C		3'b001
`define INSN_reg_D		3'b010
`define INSN_reg_E		3'b011
`define INSN_reg_H		3'b100
`define INSN_reg_L		3'b101
`define INSN_reg_dHL		3'b110
`define INSN_reg16_BC		2'b00
`define INSN_reg16_DE		2'b01
`define INSN_reg16_HL		2'b10
`define INSN_reg16_SP		2'b11
`define INSN_stack_AF		2'b11
`define INSN_stack_BC		2'b00
`define INSN_stack_DE		2'b01
`define INSN_stack_HL		2'b10
`define INSN_alu_ADD		3'b000
`define INSN_alu_ADC		3'b001
`define INSN_alu_SUB		3'b010
`define INSN_alu_SBC		3'b011
`define INSN_alu_AND		3'b100
`define INSN_alu_XOR		3'b101
`define INSN_alu_OR		3'b110
`define INSN_alu_CP		3'b111		// Oh lawd, is dat some CP?
`define INSN_alu_RLC		3'b000
`define INSN_alu_RRC		3'b001
`define INSN_alu_RL		3'b010
`define INSN_alu_RR		3'b011
`define INSN_alu_DA_SLA		3'b100
`define INSN_alu_CPL_SRA	3'b101
`define INSN_alu_SCF_SWAP	3'b110
`define INSN_alu_CCF_SRL	3'b111

`define EXEC_INC_PC 		`_PC <= `_PC + 1;
`define EXEC_NEXTADDR_PCINC	address <= `_PC + 1;
`define EXEC_NEWCYCLE		begin newcycle <= 1; rd <= 1; wr <= 0; end
`define EXEC_NEWCYCLE_TWOBYTE	begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
`ifdef isim
	`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end
	`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end
`else
	/* Work around XST's retarded bugs :\ */
	`define EXEC_WRITE(ad, da)	begin address <= (ad); wdata <= (da); wr <= 1; end end
	`define EXEC_READ(ad)		begin address <= (ad); rd <= 1; end end
`endif

module GBZ80Core(
	input clk,
	inout [15:0] bus0address,	/* BUS_* is latched on STATE_FETCH. */
	inout [7:0] bus0data,
	inout bus0wr, bus0rd,
	inout [15:0] bus1address,	/* BUS_* is latched on STATE_FETCH. */
	inout [7:0] bus1data,
	inout bus1wr, bus1rd,
	input irq, output reg irqack, input [7:0] jaddr,
	output reg [1:0] state);

//	reg [1:0] state;					/* State within this bus cycle (see STATE_*). */
	reg [2:0] cycle;					/* Cycle for instructions. */
	
	reg [7:0] registers[11:0];
	
	reg [15:0] address;				/* Address for the next bus operation. */
	
	reg [8:0] opcode;				/* Opcode from the current machine cycle. */

	reg [7:0] rdata, wdata;		/* Read data from this bus cycle, or write data for the next. */
	reg rd, wr, newcycle, twobyte;
	
	reg [7:0] tmp, tmp2;			/* Generic temporary regs. */
	
	reg [7:0] buswdata;
	wire [7:0] busdata;
	
	reg [15:0] busaddress;
	reg buswr, busrd;
	
	reg bootstrap_enb;
	
	wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF))	/* 0 or 1 depending on which bus */
		`ifdef isim
			|| (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
		`endif
			;
		
	assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
	assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
	assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
	assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
	assign busdata = (bus == 0) ? bus0data : bus1data;
	assign bus0rd = (bus == 0) ? busrd : 1'b0;
	assign bus1rd = (bus == 1) ? busrd : 1'b0;
	assign bus0wr = (bus == 0) ? buswr : 1'b0;
	assign bus1wr = (bus == 1) ? buswr : 1'b0;

	reg ie, iedelay;

`define LOCALWIRES
`include "allinsns.v"
`undef LOCALWIRES

	initial begin
		`_A <= 0;
		`_B <= 0;
		`_C <= 0;
		`_D <= 0;
		`_E <= 0;
		`_F <= 0;
		`_H <= 0;
		`_L <= 0;
		`_PCH <= 0;
		`_PCL <= 0;
		`_SPH <= 0;
		`_SPL <= 0;
		rd <= 1;
		wr <= 0;
		newcycle <= 1;
		state <= 0;
		cycle <= 0;
		busrd <= 0;
		buswr <= 0;
		busaddress <= 0;
		ie <= 0;
		iedelay <= 0;
		opcode <= 0;
		state <= `STATE_WRITEBACK;
		cycle <= 0;
		twobyte <= 0;
		bootstrap_enb <= 1;
		irqack <= 0;
	end

	always @(negedge clk)	/* Set things up at the negedge to prepare for the posedge. */
		case (state)
		`STATE_FETCH: begin
			if (newcycle) begin
				busaddress <= `_PC;
				buswr <= 0;
				busrd <= 1;
			end else begin
				busaddress <= address;
				buswr <= wr;
				busrd <= rd;
				if (wr) begin
					buswdata <= wdata;
					if (address == 16'hFF50)
						bootstrap_enb <= 0;
				end
			end
		end
		`STATE_DECODE: begin	/* Make sure this only happens for one clock. */
			buswr <= 0;
			busrd <= 0;
		end
		endcase
	
	always @(posedge clk)
		case (state)
		`STATE_FETCH: begin
			/* Things are set up in negedge so that something looking on posedge will get his shit. */
			state <= `STATE_DECODE;
		end
		`STATE_DECODE: begin
			if (newcycle) begin
				if (twobyte) begin
					opcode <= {1'b1,busdata};
					twobyte <= 0;
				end else if (ie && irq)
					opcode <= `INSN_VOP_INTR;
				else
					opcode <= {1'b0,busdata};
				newcycle <= 0;
				rdata <= busdata;
				cycle <= 0;
			end else begin
				if (rd) rdata <= busdata;	/* Still valid because peripherals are now expected to keep it held valid. */
				cycle <= cycle + 1;
			end
			if (iedelay) begin
				ie <= 1;
				iedelay <= 0;
			end
			wr <= 0;
			rd <= 0;
`ifdef isim
			address <= 16'bxxxxxxxxxxxxxxxx;	// Make it obvious if something of type has happened.
			wdata <= 8'bxxxxxxxx;
`endif
			state <= `STATE_EXECUTE;
		end
		`STATE_EXECUTE: begin
		`ifdef isim
			if (opcode[7:0] === 8'bxxxxxxxx)
				$stop;
		`endif
			casex (opcode)
			`define EXECUTE
			`include "allinsns.v"
			`undef EXECUTE
			default:
			begin
				address <= {7'h78,opcode};	// Have the CPU tell you F0xx if something's gone wrong.
				$stop;
			end
			endcase
			state <= `STATE_WRITEBACK;
		end
		`STATE_WRITEBACK: begin
			casex (opcode)
			`define WRITEBACK
			`include "allinsns.v"
			`undef WRITEBACK
			default:
				$stop;
			endcase
			state <= `STATE_FETCH;
		end
		endcase
endmodule
Commit	Line	Data
df770340 JW	1	`define REG_A 0
	2	`define REG_B 1
	3	`define REG_C 2
	4	`define REG_D 3
	5	`define REG_E 4
	6	`define REG_F 5
	7	`define REG_H 6
	8	`define REG_L 7
	9	`define REG_SPH 8
	10	`define REG_SPL 9
	11	`define REG_PCH 10
	12	`define REG_PCL 11
2f55f809	13
5509558d JW	14	`define _A registers[`REG_A]
	15	`define _B registers[`REG_B]
	16	`define _C registers[`REG_C]
	17	`define _D registers[`REG_D]
	18	`define _E registers[`REG_E]
	19	`define _F registers[`REG_F]
	20	`define _H registers[`REG_H]
	21	`define _L registers[`REG_L]
	22	`define _SPH registers[`REG_SPH]
	23	`define _SPL registers[`REG_SPL]
	24	`define _PCH registers[`REG_PCH]
	25	`define _PCL registers[`REG_PCL]
	26	`define _AF {`_A, `_F}
	27	`define _BC {`_B, `_C}
	28	`define _DE {`_D, `_E}
	29	`define _HL {`_H, `_L}
	30	`define _SP {`_SPH, `_SPL}
	31	`define _PC {`_PCH, `_PCL}
	32
df770340 JW	33	`define FLAG_Z 8'b10000000
	34	`define FLAG_N 8'b01000000
	35	`define FLAG_H 8'b00100000
	36	`define FLAG_C 8'b00010000
2f55f809	37
df770340 JW	38	`define STATE_FETCH 2'h0
df770340 JW	39	`define STATE_DECODE 2'h1
2f55f809 JW	40	`define STATE_EXECUTE 2'h2
	41	`define STATE_WRITEBACK 2'h3
	42
decafd62	43	`define INSN_VOP_INTR 9'b011111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
decafd62 JW	44	`define INSN_RES 9'b110xxxxxx
decafd62 JW	45	`define INSN_SET 9'b111xxxxxx
a85b19a7	46
df770340 JW	47	`define INSN_cc_NZ 2'b00
	48	`define INSN_cc_Z 2'b01
	49	`define INSN_cc_NC 2'b10
	50	`define INSN_cc_C 2'b11
fa136d63	51
b85870e0 JW	52	`define INSN_reg_A 3'b111
	53	`define INSN_reg_B 3'b000
	54	`define INSN_reg_C 3'b001
	55	`define INSN_reg_D 3'b010
	56	`define INSN_reg_E 3'b011
	57	`define INSN_reg_H 3'b100
	58	`define INSN_reg_L 3'b101
df770340 JW	59	`define INSN_reg_dHL 3'b110
	60	`define INSN_reg16_BC 2'b00
	61	`define INSN_reg16_DE 2'b01
	62	`define INSN_reg16_HL 2'b10
	63	`define INSN_reg16_SP 2'b11
	64	`define INSN_stack_AF 2'b11
	65	`define INSN_stack_BC 2'b00
	66	`define INSN_stack_DE 2'b01
	67	`define INSN_stack_HL 2'b10
94522011 JW	68	`define INSN_alu_ADD 3'b000
	69	`define INSN_alu_ADC 3'b001
	70	`define INSN_alu_SUB 3'b010
	71	`define INSN_alu_SBC 3'b011
	72	`define INSN_alu_AND 3'b100
	73	`define INSN_alu_XOR 3'b101
	74	`define INSN_alu_OR 3'b110
	75	`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
decafd62 JW	76	`define INSN_alu_RLC 3'b000
	77	`define INSN_alu_RRC 3'b001
	78	`define INSN_alu_RL 3'b010
	79	`define INSN_alu_RR 3'b011
	80	`define INSN_alu_DA_SLA 3'b100
	81	`define INSN_alu_CPL_SRA 3'b101
	82	`define INSN_alu_SCF_SWAP 3'b110
	83	`define INSN_alu_CCF_SRL 3'b111
94522011	84
5c33c5c0 JW	85	`define EXEC_INC_PC `_PC <= `_PC + 1;
	86	`define EXEC_NEXTADDR_PCINC address <= `_PC + 1;
	87	`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end
decafd62	88	`define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
e7fe9dc2	89	`ifdef isim
e7fb589a JW	90	`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end
	91	`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end
	92	`else
e7fe9dc2 JW	93	/* Work around XST's retarded bugs :\ */
	94	`define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
	95	`define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
e7fb589a	96	`endif
5509558d	97
2f55f809 JW	98	module GBZ80Core(
2f55f809 JW	99	input clk,
91c74a3f JW	100	inout [15:0] bus0address, /* BUS_* is latched on STATE_FETCH. */
	101	inout [7:0] bus0data,
	102	inout bus0wr, bus0rd,
	103	inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */
	104	inout [7:0] bus1data,
	105	inout bus1wr, bus1rd,
d1b40456	106	input irq, output reg irqack, input [7:0] jaddr,
6c46357c	107	output reg [1:0] state);
decafd62	108
6c46357c	109	// reg [1:0] state; /* State within this bus cycle (see STATE_). /
9c834ff2	110	reg [2:0] cycle; /* Cycle for instructions. */
2f55f809 JW	111
	112	reg [7:0] registers[11:0];
	113
	114	reg [15:0] address; /* Address for the next bus operation. */
	115
decafd62 JW	116	reg [8:0] opcode; /* Opcode from the current machine cycle. */
decafd62 JW	117
2f55f809	118	reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
decafd62	119	reg rd, wr, newcycle, twobyte;
2f55f809	120
ef6fbe31	121	reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0	122
2f55f809	123	reg [7:0] buswdata;
91c74a3f JW	124	wire [7:0] busdata;
	125
	126	reg [15:0] busaddress;
	127	reg buswr, busrd;
	128
	129	reg bootstrap_enb;
	130
e29171aa JW	131	wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) \|\| ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)) /* 0 or 1 depending on which bus */
	132	`ifdef isim
	133	\|\| (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
	134	`endif
	135	;
91c74a3f JW	136
	137	assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
	138	assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
	139	assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
	140	assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
	141	assign busdata = (bus == 0) ? bus0data : bus1data;
e29171aa JW	142	assign bus0rd = (bus == 0) ? busrd : 1'b0;
	143	assign bus1rd = (bus == 1) ? busrd : 1'b0;
	144	assign bus0wr = (bus == 0) ? buswr : 1'b0;
	145	assign bus1wr = (bus == 1) ? buswr : 1'b0;
decafd62	146
eb0f2fe1	147	reg ie, iedelay;
decafd62	148
5c834537 JW	149	`define LOCALWIRES
	150	`include "allinsns.v"
	151	`undef LOCALWIRES
	152
2f55f809	153	initial begin
b4f3ac35 JW	154	`_A <= 0;
	155	`_B <= 0;
	156	`_C <= 0;
	157	`_D <= 0;
	158	`_E <= 0;
	159	`_F <= 0;
	160	`_H <= 0;
	161	`_L <= 0;
	162	`_PCH <= 0;
	163	`_PCL <= 0;
	164	`_SPH <= 0;
	165	`_SPL <= 0;
2e642f1f JW	166	rd <= 1;
	167	wr <= 0;
	168	newcycle <= 1;
	169	state <= 0;
	170	cycle <= 0;
f8db6448 JW	171	busrd <= 0;
	172	buswr <= 0;
	173	busaddress <= 0;
9c834ff2	174	ie <= 0;
f8db6448	175	iedelay <= 0;
9c834ff2 JW	176	opcode <= 0;
	177	state <= `STATE_WRITEBACK;
	178	cycle <= 0;
decafd62	179	twobyte <= 0;
91c74a3f	180	bootstrap_enb <= 1;
d1b40456	181	irqack <= 0;
2f55f809 JW	182	end
2f55f809 JW	183
b338a0b6	184	always @(negedge clk) /* Set things up at the negedge to prepare for the posedge. */
2f55f809 JW	185	case (state)
2f55f809 JW	186	`STATE_FETCH: begin
2e642f1f	187	if (newcycle) begin
decafd62	188	busaddress <= `_PC;
2e642f1f JW	189	buswr <= 0;
	190	busrd <= 1;
	191	end else begin
2f55f809	192	busaddress <= address;
2e642f1f JW	193	buswr <= wr;
2e642f1f JW	194	busrd <= rd;
1eefdc8e	195	if (wr) begin
2e642f1f	196	buswdata <= wdata;
1eefdc8e JW	197	if (address == 16'hFF50)
	198	bootstrap_enb <= 0;
	199	end
2e642f1f	200	end
b338a0b6 JW	201	end
b338a0b6 JW	202	`STATE_DECODE: begin /* Make sure this only happens for one clock. */
e29171aa JW	203	buswr <= 0;
e29171aa JW	204	busrd <= 0;
b338a0b6 JW	205	end
	206	endcase
	207
	208	always @(posedge clk)
	209	case (state)
	210	`STATE_FETCH: begin
	211	/* Things are set up in negedge so that something looking on posedge will get his shit. */
2f55f809 JW	212	state <= `STATE_DECODE;
	213	end
	214	`STATE_DECODE: begin
	215	if (newcycle) begin
decafd62	216	if (twobyte) begin
e7fb589a	217	opcode <= {1'b1,busdata};
decafd62 JW	218	twobyte <= 0;
decafd62 JW	219	end else if (ie && irq)
f8db6448 JW	220	opcode <= `INSN_VOP_INTR;
f8db6448 JW	221	else
e7fb589a	222	opcode <= {1'b0,busdata};
b85870e0	223	newcycle <= 0;
2854e399	224	rdata <= busdata;
2f55f809	225	cycle <= 0;
2e642f1f	226	end else begin
e29171aa	227	if (rd) rdata <= busdata; /* Still valid because peripherals are now expected to keep it held valid. */
2e642f1f JW	228	cycle <= cycle + 1;
2e642f1f JW	229	end
f8db6448 JW	230	if (iedelay) begin
	231	ie <= 1;
	232	iedelay <= 0;
	233	end
97649fed JW	234	wr <= 0;
97649fed JW	235	rd <= 0;
99b96879	236	`ifdef isim
97649fed JW	237	address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
97649fed JW	238	wdata <= 8'bxxxxxxxx;
99b96879	239	`endif
2f55f809 JW	240	state <= `STATE_EXECUTE;
	241	end
	242	`STATE_EXECUTE: begin
d1b40456	243	`ifdef isim
e29171aa JW	244	if (opcode[7:0] === 8'bxxxxxxxx)
e29171aa JW	245	$stop;
d1b40456	246	`endif
2f55f809	247	casex (opcode)
81358c71 JW	248	`define EXECUTE
	249	`include "allinsns.v"
	250	`undef EXECUTE
634ce02c	251	default:
99b96879 JW	252	begin
99b96879 JW	253	address <= {7'h78,opcode}; // Have the CPU tell you F0xx if something's gone wrong.
634ce02c	254	$stop;
99b96879	255	end
2f55f809 JW	256	endcase
	257	state <= `STATE_WRITEBACK;
	258	end
	259	`STATE_WRITEBACK: begin
	260	casex (opcode)
81358c71 JW	261	`define WRITEBACK
	262	`include "allinsns.v"
	263	`undef WRITEBACK
ef6fbe31 JW	264	default:
ef6fbe31 JW	265	$stop;
2f55f809 JW	266	endcase
	267	state <= `STATE_FETCH;
	268	end
	269	endcase
	270	endmodule