Ethernet TX support
[fpgaboy.git] / core / GBZ80Core.v
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1`define REG_A 0
2`define REG_B 1
3`define REG_C 2
4`define REG_D 3
5`define REG_E 4
6`define REG_F 5
7`define REG_H 6
8`define REG_L 7
9`define REG_SPH 8
10`define REG_SPL 9
11`define REG_PCH 10
12`define REG_PCL 11
2f55f809 13
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14`define _A registers[`REG_A]
15`define _B registers[`REG_B]
16`define _C registers[`REG_C]
17`define _D registers[`REG_D]
18`define _E registers[`REG_E]
19`define _F registers[`REG_F]
20`define _H registers[`REG_H]
21`define _L registers[`REG_L]
22`define _SPH registers[`REG_SPH]
23`define _SPL registers[`REG_SPL]
24`define _PCH registers[`REG_PCH]
25`define _PCL registers[`REG_PCL]
26`define _AF {`_A, `_F}
27`define _BC {`_B, `_C}
28`define _DE {`_D, `_E}
29`define _HL {`_H, `_L}
30`define _SP {`_SPH, `_SPL}
31`define _PC {`_PCH, `_PCL}
32
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33`define FLAG_Z 8'b10000000
34`define FLAG_N 8'b01000000
35`define FLAG_H 8'b00100000
36`define FLAG_C 8'b00010000
2f55f809 37
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38`define STATE_FETCH 2'h0
39`define STATE_DECODE 2'h1
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40`define STATE_EXECUTE 2'h2
41`define STATE_WRITEBACK 2'h3
42
decafd62 43`define INSN_VOP_INTR 9'b011111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
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44`define INSN_RES 9'b110xxxxxx
45`define INSN_SET 9'b111xxxxxx
a85b19a7 46
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47`define INSN_cc_NZ 2'b00
48`define INSN_cc_Z 2'b01
49`define INSN_cc_NC 2'b10
50`define INSN_cc_C 2'b11
fa136d63 51
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52`define INSN_reg_A 3'b111
53`define INSN_reg_B 3'b000
54`define INSN_reg_C 3'b001
55`define INSN_reg_D 3'b010
56`define INSN_reg_E 3'b011
57`define INSN_reg_H 3'b100
58`define INSN_reg_L 3'b101
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59`define INSN_reg_dHL 3'b110
60`define INSN_reg16_BC 2'b00
61`define INSN_reg16_DE 2'b01
62`define INSN_reg16_HL 2'b10
63`define INSN_reg16_SP 2'b11
64`define INSN_stack_AF 2'b11
65`define INSN_stack_BC 2'b00
66`define INSN_stack_DE 2'b01
67`define INSN_stack_HL 2'b10
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68`define INSN_alu_ADD 3'b000
69`define INSN_alu_ADC 3'b001
70`define INSN_alu_SUB 3'b010
71`define INSN_alu_SBC 3'b011
72`define INSN_alu_AND 3'b100
73`define INSN_alu_XOR 3'b101
74`define INSN_alu_OR 3'b110
75`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
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76`define INSN_alu_RLC 3'b000
77`define INSN_alu_RRC 3'b001
78`define INSN_alu_RL 3'b010
79`define INSN_alu_RR 3'b011
80`define INSN_alu_DA_SLA 3'b100
81`define INSN_alu_CPL_SRA 3'b101
82`define INSN_alu_SCF_SWAP 3'b110
83`define INSN_alu_CCF_SRL 3'b111
94522011 84
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85`define EXEC_INC_PC `_PC <= `_PC + 1;
86`define EXEC_NEXTADDR_PCINC address <= `_PC + 1;
87`define EXEC_NEWCYCLE begin newcycle <= 1; rd <= 1; wr <= 0; end
decafd62 88`define EXEC_NEWCYCLE_TWOBYTE begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
e7fe9dc2 89`ifdef isim
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90 `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end
91 `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end
92`else
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93 /* Work around XST's retarded bugs :\ */
94 `define EXEC_WRITE(ad, da) begin address <= (ad); wdata <= (da); wr <= 1; end end
95 `define EXEC_READ(ad) begin address <= (ad); rd <= 1; end end
e7fb589a 96`endif
5509558d 97
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98module GBZ80Core(
99 input clk,
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100 inout [15:0] bus0address, /* BUS_* is latched on STATE_FETCH. */
101 inout [7:0] bus0data,
102 inout bus0wr, bus0rd,
103 inout [15:0] bus1address, /* BUS_* is latched on STATE_FETCH. */
104 inout [7:0] bus1data,
105 inout bus1wr, bus1rd,
d1b40456 106 input irq, output reg irqack, input [7:0] jaddr,
6c46357c 107 output reg [1:0] state);
decafd62 108
6c46357c 109// reg [1:0] state; /* State within this bus cycle (see STATE_*). */
9c834ff2 110 reg [2:0] cycle; /* Cycle for instructions. */
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111
112 reg [7:0] registers[11:0];
113
114 reg [15:0] address; /* Address for the next bus operation. */
115
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116 reg [8:0] opcode; /* Opcode from the current machine cycle. */
117
2f55f809 118 reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
decafd62 119 reg rd, wr, newcycle, twobyte;
2f55f809 120
ef6fbe31 121 reg [7:0] tmp, tmp2; /* Generic temporary regs. */
b85870e0 122
2f55f809 123 reg [7:0] buswdata;
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124 wire [7:0] busdata;
125
126 reg [15:0] busaddress;
127 reg buswr, busrd;
128
129 reg bootstrap_enb;
130
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131 wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF)) /* 0 or 1 depending on which bus */
132 `ifdef isim
133 || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
134 `endif
135 ;
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136
137 assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
138 assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
139 assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
140 assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
141 assign busdata = (bus == 0) ? bus0data : bus1data;
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142 assign bus0rd = (bus == 0) ? busrd : 1'b0;
143 assign bus1rd = (bus == 1) ? busrd : 1'b0;
144 assign bus0wr = (bus == 0) ? buswr : 1'b0;
145 assign bus1wr = (bus == 1) ? buswr : 1'b0;
decafd62 146
eb0f2fe1 147 reg ie, iedelay;
decafd62 148
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149`define LOCALWIRES
150`include "allinsns.v"
151`undef LOCALWIRES
152
2f55f809 153 initial begin
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154 `_A <= 0;
155 `_B <= 0;
156 `_C <= 0;
157 `_D <= 0;
158 `_E <= 0;
159 `_F <= 0;
160 `_H <= 0;
161 `_L <= 0;
162 `_PCH <= 0;
163 `_PCL <= 0;
164 `_SPH <= 0;
165 `_SPL <= 0;
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166 rd <= 1;
167 wr <= 0;
168 newcycle <= 1;
169 state <= 0;
170 cycle <= 0;
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171 busrd <= 0;
172 buswr <= 0;
173 busaddress <= 0;
9c834ff2 174 ie <= 0;
f8db6448 175 iedelay <= 0;
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176 opcode <= 0;
177 state <= `STATE_WRITEBACK;
178 cycle <= 0;
decafd62 179 twobyte <= 0;
91c74a3f 180 bootstrap_enb <= 1;
d1b40456 181 irqack <= 0;
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182 end
183
b338a0b6 184 always @(negedge clk) /* Set things up at the negedge to prepare for the posedge. */
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185 case (state)
186 `STATE_FETCH: begin
2e642f1f 187 if (newcycle) begin
decafd62 188 busaddress <= `_PC;
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189 buswr <= 0;
190 busrd <= 1;
191 end else begin
2f55f809 192 busaddress <= address;
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193 buswr <= wr;
194 busrd <= rd;
1eefdc8e 195 if (wr) begin
2e642f1f 196 buswdata <= wdata;
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197 if (address == 16'hFF50)
198 bootstrap_enb <= 0;
199 end
2e642f1f 200 end
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201 end
202 `STATE_DECODE: begin /* Make sure this only happens for one clock. */
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203 buswr <= 0;
204 busrd <= 0;
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205 end
206 endcase
207
208 always @(posedge clk)
209 case (state)
210 `STATE_FETCH: begin
211 /* Things are set up in negedge so that something looking on posedge will get his shit. */
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212 state <= `STATE_DECODE;
213 end
214 `STATE_DECODE: begin
215 if (newcycle) begin
decafd62 216 if (twobyte) begin
e7fb589a 217 opcode <= {1'b1,busdata};
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218 twobyte <= 0;
219 end else if (ie && irq)
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220 opcode <= `INSN_VOP_INTR;
221 else
e7fb589a 222 opcode <= {1'b0,busdata};
b85870e0 223 newcycle <= 0;
2854e399 224 rdata <= busdata;
2f55f809 225 cycle <= 0;
2e642f1f 226 end else begin
e29171aa 227 if (rd) rdata <= busdata; /* Still valid because peripherals are now expected to keep it held valid. */
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228 cycle <= cycle + 1;
229 end
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230 if (iedelay) begin
231 ie <= 1;
232 iedelay <= 0;
233 end
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234 wr <= 0;
235 rd <= 0;
99b96879 236`ifdef isim
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237 address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
238 wdata <= 8'bxxxxxxxx;
99b96879 239`endif
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240 state <= `STATE_EXECUTE;
241 end
242 `STATE_EXECUTE: begin
d1b40456 243 `ifdef isim
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244 if (opcode[7:0] === 8'bxxxxxxxx)
245 $stop;
d1b40456 246 `endif
2f55f809 247 casex (opcode)
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248 `define EXECUTE
249 `include "allinsns.v"
250 `undef EXECUTE
634ce02c 251 default:
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252 begin
253 address <= {7'h78,opcode}; // Have the CPU tell you F0xx if something's gone wrong.
634ce02c 254 $stop;
99b96879 255 end
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256 endcase
257 state <= `STATE_WRITEBACK;
258 end
259 `STATE_WRITEBACK: begin
260 casex (opcode)
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261 `define WRITEBACK
262 `include "allinsns.v"
263 `undef WRITEBACK
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264 default:
265 $stop;
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266 endcase
267 state <= `STATE_FETCH;
268 end
269 endcase
270endmodule
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