ICache: Change cache_data to block RAM (yay!).
[firearm.git] / Issue.v
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1`include "ARM_Constants.v"
2
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3module Issue(
4 input clk,
09e28f01 5 input Nrst, /* XXX not used yet */
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6
7 input stall, /* pipeline control */
5b3daee2 8 input flush, /* XXX not used yet */
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9
10 input inbubble, /* stage inputs */
11 input [31:0] insn,
12 input [31:0] inpc,
ae281afd 13 input [31:0] cpsr,
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dfddccfb 15 output wire outstall, /* stage outputs */
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16 output reg outbubble = 1,
17 output reg [31:0] outpc = 0,
18 output reg [31:0] outinsn = 0
6595c4c8 19 /* XXX other? */
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20 );
21
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22`ifdef COPY_PASTA_FODDER
23 /* from page 2 of ARM7TDMIvE2.pdf */
24 casex (insn)
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25 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
26// `DECODE_ALU_MUL_LONG: /* Multiply long */
27 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
28 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
29 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
30 `DECODE_ALU_SWP: /* Atomic swap */
31 `DECODE_ALU_BX: /* Branch */
32 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
33 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
34 `DECODE_ALU: /* ALU */
35 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
36 `DECODE_LDRSTR: /* Single data transfer */
37 `DECODE_LDMSTM: /* Block data transfer */
38 `DECODE_BRANCH: /* Branch */
39 `DECODE_LDCSTC: /* Coprocessor data transfer */
40 `DECODE_CDP: /* Coprocessor data op */
41 `DECODE_MRCMCR: /* Coprocessor register transfer */
42 `DECODE_SWI: /* SWI */
43 default: /* X everything else out */
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44 endcase
45`endif
46
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47 /* Flag setting */
48 reg use_cpsr;
49 reg [15:0] use_regs;
50 reg def_cpsr;
51 reg [15:0] def_regs;
52
53 function [15:0] idxbit;
54 input [3:0] r;
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55 if (r == 15)
56 idxbit = 0;
57 else
58 idxbit = (16'b1) << r;
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59 endfunction
60
61 wire [3:0] rn = insn[19:16];
62 wire [3:0] rd = insn[15:12];
7aa8541b 63 wire [3:0] rs = insn[11:8];
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64 wire [3:0] rm = insn[3:0];
65 wire [3:0] cond = insn[31:28];
66
67 wire [3:0] rd_mul = insn[19:16];
68 wire [3:0] rn_mul = insn[15:12];
69 wire [3:0] rs_mul = insn[11:8];
70
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71 wire [3:0] alu_opc = insn[24:21];
72
73 function alu_is_logical;
74 input [3:0] op;
75
76 case (op)
77 `ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1;
78 default: alu_is_logical = 0;
79 endcase
80 endfunction
81
82 function alu_flags_only;
83 input [3:0] op;
84
85 case (op)
86 `ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1;
87 default: alu_flags_only = 0;
88 endcase
89 endfunction
90
91 function shift_requires_carry;
92 input [7:0] shift;
93
94 case(shift[1:0])
95 `SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0);
96 `SHIFT_LSR: shift_requires_carry = 0;
97 `SHIFT_ASR: shift_requires_carry = 0;
98 `SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0);
99 endcase
100 endfunction
101
e216a134 102 always @(*)
7aa8541b 103 casez (insn)
6b8a01fa 104 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
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105 begin
106 use_cpsr = `COND_MATTERS(cond);
107 use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
108 def_cpsr = insn[20] /* setcc */;
109 def_regs = idxbit(rd_mul);
110 end
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111// `DECODE_ALU_MUL_LONG: /* Multiply long */
112 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
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113 begin
114 use_cpsr = `COND_MATTERS(cond) || (insn[22] == 0) /* Source = CPSR */;
115 use_regs = 0;
116 def_cpsr = 0;
117 def_regs = idxbit(rd);
118 end
6b8a01fa 119 `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
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120 begin
121 use_cpsr = `COND_MATTERS(cond);
122 use_regs = idxbit(rm);
123 def_cpsr = 1;
124 def_regs = 0;
125 end
6b8a01fa 126 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
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127 begin
128 use_cpsr = `COND_MATTERS(cond);
129 use_regs = insn[25] ? 0 : idxbit(rm);
130 def_cpsr = 1;
131 def_regs = 0;
132 end
6b8a01fa 133 `DECODE_ALU_SWP: /* Atomic swap */
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134 begin
135 use_cpsr = `COND_MATTERS(cond);
136 use_regs = idxbit(rn) | idxbit(rm);
137 def_cpsr = 0;
138 def_regs = idxbit(rd);
139 end
6b8a01fa 140 `DECODE_ALU_BX: /* Branch */
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141 begin
142 use_cpsr = `COND_MATTERS(cond);
143 use_regs = idxbit(rm);
144 def_cpsr = 0; // don't care, we'll never get there
145 def_regs = 0;
146 end
6b8a01fa 147 `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
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148 begin
149 use_cpsr = `COND_MATTERS(cond);
150 use_regs = idxbit(rn) | idxbit(rm) | (insn[20] /* L */ ? 0 : idxbit(rd));
151 def_cpsr = 0;
152 def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
153 end
6b8a01fa 154 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
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155 begin
156 use_cpsr = `COND_MATTERS(cond);
157 use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
158 def_cpsr = 0;
159 def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
160 end
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161 `DECODE_ALU: /* ALU */
162 begin
163 use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
164 use_regs =
165 (insn[25] /* I */ ? 0 :
166 (insn[4] /* shift by reg */ ?
167 (idxbit(rs) | idxbit(rm)) :
168 (idxbit(rm)))) |
169 (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
cd577923 170 def_cpsr = insn[20] /* S */;
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171 def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
172 end
6b8a01fa 173 `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
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174 begin
175 use_cpsr = 0;
176 use_regs = 0;
177 def_cpsr = 0;
178 def_regs = 0;
179 end
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180 `DECODE_LDRSTR:
181 begin
182 use_cpsr = `COND_MATTERS(cond);
15bdd2aa 183 use_regs = idxbit(rn) | (insn[25] /* I */ ? idxbit(rm) : 0) | (insn[20] /* L */ ? 0 : idxbit(rd));
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184 def_cpsr = 0;
185 def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
186 end
187 `DECODE_LDMSTM: /* Block data transfer */
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188 begin
189 use_cpsr = `COND_MATTERS(cond);
190 use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : insn[15:0]);
191 def_cpsr = insn[22]; /* This is a superset of all cases, anyway. */
192 def_regs = (insn[21] /* W */ ? idxbit(rn) : 0) | (insn[20] /* L */ ? insn[15:0] : 0);
193 end
6b8a01fa 194 `DECODE_BRANCH: /* Branch */
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195 begin
196 use_cpsr = `COND_MATTERS(cond);
197 use_regs = 0;
198 def_cpsr = 0;
a02d953f 199 def_regs = insn[24] /* L */ ? (16'b1 << 14) : 0;
7aa8541b 200 end
6b8a01fa 201 `DECODE_LDCSTC: /* Coprocessor data transfer */
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202 begin
203 use_cpsr = `COND_MATTERS(cond);
204 use_regs = idxbit(rn);
205 def_cpsr = 0;
206 def_regs = insn[21] /* W */ ? idxbit(rn) : 0;
207 end
6b8a01fa 208 `DECODE_CDP: /* Coprocessor data op */
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209 begin
210 use_cpsr = `COND_MATTERS(cond);
211 use_regs = 0;
212 def_cpsr = 0;
213 def_regs = 0;
214 end
6b8a01fa 215 `DECODE_MRCMCR: /* Coprocessor register transfer */
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216 begin
217 use_cpsr = `COND_MATTERS(cond);
218 use_regs = insn[20] /* L */ ? 0 : idxbit(rd);
219 def_cpsr = 0;
220 def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
221 end
6b8a01fa 222 `DECODE_SWI: /* SWI */
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223 begin
224 use_cpsr = `COND_MATTERS(cond);
225 use_regs = 0;
226 def_cpsr = 0;
227 def_regs = 0;
228 end
e216a134 229 default: /* X everything else out */
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230 begin
231 use_cpsr = 1'bx;
232 use_regs = 16'bxxxxxxxxxxxxxxxx;
233 def_cpsr = 1'bx;
234 def_regs = 16'bxxxxxxxxxxxxxxxx;
235 end
e216a134 236 endcase
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237
238 /* Condition checking logic */
239 reg condition_met;
240 always @(*)
241 casez(insn[31:28])
242 `COND_EQ: condition_met = cpsr[`CPSR_Z];
243 `COND_NE: condition_met = !cpsr[`CPSR_Z];
244 `COND_CS: condition_met = cpsr[`CPSR_C];
245 `COND_CC: condition_met = !cpsr[`CPSR_C];
246 `COND_MI: condition_met = cpsr[`CPSR_N];
247 `COND_PL: condition_met = !cpsr[`CPSR_N];
248 `COND_VS: condition_met = cpsr[`CPSR_V];
249 `COND_VC: condition_met = !cpsr[`CPSR_V];
250 `COND_HI: condition_met = cpsr[`CPSR_C] && !cpsr[`CPSR_Z];
251 `COND_LS: condition_met = !cpsr[`CPSR_C] || cpsr[`CPSR_Z];
252 `COND_GE: condition_met = cpsr[`CPSR_N] == cpsr[`CPSR_V];
253 `COND_LT: condition_met = cpsr[`CPSR_N] != cpsr[`CPSR_V];
254 `COND_GT: condition_met = !cpsr[`CPSR_Z] && (cpsr[`CPSR_N] == cpsr[`CPSR_V]);
255 `COND_LE: condition_met = cpsr[`CPSR_Z] || (cpsr[`CPSR_N] != cpsr[`CPSR_V]);
256 `COND_AL: condition_met = 1;
257 `COND_NV: condition_met = 0;
258 default: condition_met = 1'bx;
259 endcase
260
261 /* Issue logic */
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262`define STAGE_EXECUTE 0
263`define STAGE_MEMORY 1
264/* Once it's hit writeback, it's essentially hit the regfile so you're done. */
265 reg cpsr_inflight [1:0];
266 reg [15:0] regs_inflight [1:0];
267
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268 initial
269 begin
270 cpsr_inflight[0] = 0;
271 cpsr_inflight[1] = 0;
272 regs_inflight[0] = 0;
273 regs_inflight[1] = 0;
274 end
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275
276 wire waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
277 wire waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
278 wire waiting = waiting_cpsr | waiting_regs;
279 assign outstall = (waiting && !inbubble && !flush) || stall;
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280
281 reg delayedflush = 0;
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282 always @(posedge clk/* or negedge Nrst*/)
283 if (!Nrst)
284 delayedflush <= 0;
285 else if (flush && outstall /* halp! I can't do it now, maybe later? */)
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286 delayedflush <= 1;
287 else if (!outstall /* anything has been handled this time around */)
288 delayedflush <= 0;
a02d953f 289
6595c4c8 290 /* Actually do the issue. */
a4f724e6 291 always @(posedge clk or negedge Nrst)
6595c4c8 292 begin
1c2e57dc 293 if (waiting)
1c2e57dc 294 $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
149bcd1a 295
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296 if (!Nrst) begin
297 cpsr_inflight[0] <= 0;
298 cpsr_inflight[1] <= 0;
299 regs_inflight[0] <= 0;
300 regs_inflight[1] <= 0;
301 outbubble <= 1;
302 end else if (!stall)
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303 begin
304 cpsr_inflight[0] <= cpsr_inflight[1]; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
305 cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
306 regs_inflight[0] <= regs_inflight[1];
307 regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
308
a02d953f 309 outbubble <= inbubble | waiting | !condition_met | flush | delayedflush;
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310 outpc <= inpc;
311 outinsn <= insn;
1c2e57dc 312 end
6595c4c8 313 end
60cc768b 314endmodule
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