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Commit | Line | Data |
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60cc768b JW |
1 | module Issue( |
2 | input clk, | |
3 | input Nrst, | |
4 | ||
5 | input stall, /* pipeline control */ | |
6 | input flush, | |
7 | ||
8 | input inbubble, /* stage inputs */ | |
9 | input [31:0] insn, | |
10 | input [31:0] inpc, | |
11 | ||
12 | output reg outbubble, /* stage outputs */ | |
13 | output reg [31:0] outpc | |
14 | /* other */ | |
15 | ); | |
16 | ||
17 | always @(posedge clk) | |
18 | begin | |
19 | outbubble <= inbubble; | |
20 | outpc <= inpc; | |
21 | end | |
22 | ||
23 | `ifdef COPY_PASTA_FODDER | |
24 | /* from page 2 of ARM7TDMIvE2.pdf */ | |
25 | casex (insn) | |
26 | 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ | |
27 | 32'b????00001???????????????1001????: /* Multiply long */ | |
28 | 32'b????00??????????????????????????: /* ALU */ | |
29 | 32'b????00010?00????????00001001????: /* Atomic swap */ | |
30 | 32'b????000100101111111111110001????: /* Branch */ | |
31 | 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */ | |
32 | 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */ | |
33 | 32'b????011????????????????????1????: /* Undefined. I hate ARM */ | |
34 | 32'b????01??????????????????????????: /* Single data transfer */ | |
35 | 32'b????100?????????????????????????: /* Block data transfer */ | |
36 | 32'b????101?????????????????????????: /* Branch */ | |
37 | 32'b????110?????????????????????????: /* Coprocessor data transfer */ | |
38 | 32'b????1110???????????????????0????: /* Coprocessor data op */ | |
39 | 32'b????1110???????????????????1????: /* Coprocessor register transfer */ | |
40 | 32'b????1111????????????????????????: /* SWI */ | |
41 | endcase | |
42 | `endif | |
43 | ||
44 | endmodule |