[firearm.git] / Issue.v

`include "ARM_Constants.v"

module Issue(
	input clk,
	input Nrst,	/* XXX not used yet */
	
	input stall,	/* pipeline control */
	input flush,	/* XXX not used yet */
	
	input inbubble,	/* stage inputs */
	input [31:0] insn,
	input [31:0] inpc,
	input [31:0] cpsr,
	
	output reg outstall = 0,	/* stage outputs */
	output reg outbubble = 1,
	output reg [31:0] outpc = 0,
	output reg [31:0] outinsn = 0
	/* XXX other? */
	);
	
`ifdef COPY_PASTA_FODDER
	/* from page 2 of ARM7TDMIvE2.pdf */
	casex (insn)
	`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
//	`DECODE_ALU_MUL_LONG:	/* Multiply long */
	`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
	`DECODE_ALU_MSR:	/* MSR (Transfer register to PSR) */
	`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
	`DECODE_ALU_SWP:	/* Atomic swap */
	`DECODE_ALU_BX:		/* Branch */
	`DECODE_ALU_HDATA_REG:	/* Halfword transfer - register offset */
	`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
	`DECODE_ALU:		/* ALU */
	`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
	`DECODE_LDRSTR:		/* Single data transfer */
	`DECODE_LDMSTM:		/* Block data transfer */
	`DECODE_BRANCH:		/* Branch */
	`DECODE_LDCSTC:		/* Coprocessor data transfer */
	`DECODE_CDP:		/* Coprocessor data op */
	`DECODE_MRCMCR:		/* Coprocessor register transfer */
	`DECODE_SWI:		/* SWI */
	default:		/* X everything else out */
	endcase
`endif

	/* Flag setting */
	reg use_cpsr;
	reg [15:0] use_regs;
	reg def_cpsr;
	reg [15:0] def_regs;
	
	function [15:0] idxbit;
		input [3:0] r;
		if (r == 15)
			idxbit = 0;
		else
			idxbit = (16'b1) << r;
	endfunction
	
	wire [3:0] rn = insn[19:16];
	wire [3:0] rd = insn[15:12];
	wire [3:0] rs = insn[11:8];
	wire [3:0] rm = insn[3:0];
	wire [3:0] cond = insn[31:28];
	
	wire [3:0] rd_mul = insn[19:16];
	wire [3:0] rn_mul = insn[15:12];
	wire [3:0] rs_mul = insn[11:8];
	
	wire [3:0] alu_opc = insn[24:21];
	
	function alu_is_logical;
		input [3:0] op;
		
		case (op)
		`ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1;
		default: alu_is_logical = 0;
		endcase
	endfunction
	
	function alu_flags_only;
		input [3:0] op;
		
		case (op)
		`ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1;
		default: alu_flags_only = 0;
		endcase
	endfunction
	
	function shift_requires_carry;
		input [7:0] shift;
		
		case(shift[1:0])
		`SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0);
		`SHIFT_LSR: shift_requires_carry = 0;
		`SHIFT_ASR: shift_requires_carry = 0;
		`SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0);
		endcase
	endfunction
	
	always @(*)
		casez (insn)
		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
			def_cpsr = insn[20] /* setcc */;
			def_regs = idxbit(rd_mul);
		end
//		`DECODE_ALU_MUL_LONG:	/* Multiply long */
		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
		begin
			use_cpsr = `COND_MATTERS(cond) || (insn[22] == 0) /* Source = CPSR */;
			use_regs = 0;
			def_cpsr = 0;
			def_regs = idxbit(rd);
		end
		`DECODE_ALU_MSR:	/* MSR (Transfer register to PSR) */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rm);
			def_cpsr = 1;
			def_regs = 0;
		end
		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = insn[25] ? 0 : idxbit(rm);
			def_cpsr = 1;
			def_regs = 0;
		end
		`DECODE_ALU_SWP:	/* Atomic swap */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rn) | idxbit(rm);
			def_cpsr = 0;
			def_regs = idxbit(rd);
		end
		`DECODE_ALU_BX:	/* Branch */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rm);
			def_cpsr = 0;	// don't care, we'll never get there
			def_regs = 0;
		end
		`DECODE_ALU_HDATA_REG:	/* Halfword transfer - register offset */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rn) | idxbit(rm) | (insn[20] /* L */ ? 0 : idxbit(rd));
			def_cpsr = 0;
			def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
		end
		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
			def_cpsr = 0;
			def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
		end
		`DECODE_ALU:	/* ALU */
		begin
			use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
			use_regs =
				(insn[25] /* I */ ? 0 :
					(insn[4] /* shift by reg */ ?
						(idxbit(rs) | idxbit(rm)) :
						(idxbit(rm)))) |
				(((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
			def_cpsr = insn[20] /* S */;
			def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
		end
		`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
		begin	
			use_cpsr = 0;
			use_regs = 0;
			def_cpsr = 0;
			def_regs = 0;
		end
		`DECODE_LDRSTR:
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rn) | (insn[25] /* I */ ? idxbit(rm) : 0) | (insn[20] /* L */ ? 0 : idxbit(rd));
			def_cpsr = 0;
			def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
		end
		`DECODE_LDMSTM:		/* Block data transfer */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : insn[15:0]);
			def_cpsr = insn[22];	/* This is a superset of all cases, anyway. */
			def_regs = (insn[21] /* W */ ? idxbit(rn) : 0) | (insn[20] /* L */ ? insn[15:0] : 0);
		end
		`DECODE_BRANCH:	/* Branch */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = 0;
			def_cpsr = 0;
			def_regs = 0;
		end
		`DECODE_LDCSTC:	/* Coprocessor data transfer */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = idxbit(rn);
			def_cpsr = 0;
			def_regs = insn[21] /* W */ ? idxbit(rn) : 0;
		end
		`DECODE_CDP:	/* Coprocessor data op */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = 0;
			def_cpsr = 0;
			def_regs = 0;
		end
		`DECODE_MRCMCR:		/* Coprocessor register transfer */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = insn[20] /* L */ ? 0 : idxbit(rd);
			def_cpsr = 0;
			def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
		end
		`DECODE_SWI:	/* SWI */
		begin
			use_cpsr = `COND_MATTERS(cond);
			use_regs = 0;
			def_cpsr = 0;
			def_regs = 0;
		end
		default:				/* X everything else out */
		begin
			use_cpsr = 1'bx;
			use_regs = 16'bxxxxxxxxxxxxxxxx;
			def_cpsr = 1'bx;
			def_regs = 16'bxxxxxxxxxxxxxxxx;
		end
		endcase
	
	/* Condition checking logic */
	reg condition_met;
	always @(*)
		casez(insn[31:28])
		`COND_EQ:	condition_met = cpsr[`CPSR_Z];
		`COND_NE:	condition_met = !cpsr[`CPSR_Z];
		`COND_CS:	condition_met = cpsr[`CPSR_C];
		`COND_CC:	condition_met = !cpsr[`CPSR_C];
		`COND_MI:	condition_met = cpsr[`CPSR_N];
		`COND_PL:	condition_met = !cpsr[`CPSR_N];
		`COND_VS:	condition_met = cpsr[`CPSR_V];
		`COND_VC:	condition_met = !cpsr[`CPSR_V];
		`COND_HI:	condition_met = cpsr[`CPSR_C] && !cpsr[`CPSR_Z];
		`COND_LS:	condition_met = !cpsr[`CPSR_C] || cpsr[`CPSR_Z];
		`COND_GE:	condition_met = cpsr[`CPSR_N] == cpsr[`CPSR_V];
		`COND_LT:	condition_met = cpsr[`CPSR_N] != cpsr[`CPSR_V];
		`COND_GT:	condition_met = !cpsr[`CPSR_Z] && (cpsr[`CPSR_N] == cpsr[`CPSR_V]);
		`COND_LE:	condition_met = cpsr[`CPSR_Z] || (cpsr[`CPSR_N] != cpsr[`CPSR_V]);
		`COND_AL:	condition_met = 1;
		`COND_NV:	condition_met = 0;
		default:	condition_met = 1'bx;
		endcase
	
	/* Issue logic */
`define STAGE_EXECUTE   0
`define STAGE_MEMORY    1
/* Once it's hit writeback, it's essentially hit the regfile so you're done. */
	reg cpsr_inflight [1:0];
	reg [15:0] regs_inflight [1:0];
	
	reg waiting_cpsr;
	reg waiting_regs;
	wire waiting = waiting_cpsr | waiting_regs;
	
	initial
	begin
		cpsr_inflight[0] = 0;
		cpsr_inflight[1] = 0;
		regs_inflight[0] = 0;
		regs_inflight[1] = 0;
	end
		
	always @(*)
	begin
		waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
		waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1]));
		
		outstall = (waiting && !inbubble && !flush) || stall;	/* Happens in an always @*, because it is an exception. */
	end

	reg delayedflush = 0;
	always @(posedge clk)
		if (flush && outstall /* halp! I can't do it now, maybe later? */)
			delayedflush <= 1;
		else if (!outstall /* anything has been handled this time around */)
			delayedflush <= 0;
	
	/* Actually do the issue. */
	always @(posedge clk)
	begin
		if (waiting)
			$display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);

		if((flush || delayedflush) && !outstall)
		begin
			cpsr_inflight[0] = 1'b0;
			cpsr_inflight[1] = 1'b0;
			regs_inflight[0] = 16'b0;
			regs_inflight[1] = 16'b0;
			outbubble <= 1'b1;
		end
		else if (!stall)
		begin
			cpsr_inflight[0] <= cpsr_inflight[1];	/* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
			cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr;
			regs_inflight[0] <= regs_inflight[1];
			regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs;
			
			outbubble <= inbubble | waiting | !condition_met;
			outpc <= inpc;
			outinsn <= insn;
		end
	end
endmodule
Commit	Line	Data
7aa8541b JW	1	`include "ARM_Constants.v"
7aa8541b JW	2
60cc768b JW	3	module Issue(
60cc768b JW	4	input clk,
09e28f01	5	input Nrst, /* XXX not used yet */
60cc768b JW	6
60cc768b JW	7	input stall, /* pipeline control */
5b3daee2	8	input flush, /* XXX not used yet */
60cc768b JW	9
	10	input inbubble, /* stage inputs */
	11	input [31:0] insn,
	12	input [31:0] inpc,
ae281afd	13	input [31:0] cpsr,
60cc768b	14
90ff449a JW	15	output reg outstall = 0, /* stage outputs */
	16	output reg outbubble = 1,
	17	output reg [31:0] outpc = 0,
	18	output reg [31:0] outinsn = 0
6595c4c8	19	/* XXX other? */
60cc768b JW	20	);
60cc768b JW	21
60cc768b JW	22	`ifdef COPY_PASTA_FODDER
	23	/* from page 2 of ARM7TDMIvE2.pdf */
	24	casex (insn)
6b8a01fa JW	25	`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	26	// `DECODE_ALU_MUL_LONG: /* Multiply long */
	27	`DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
	28	`DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
	29	`DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
	30	`DECODE_ALU_SWP: /* Atomic swap */
	31	`DECODE_ALU_BX: /* Branch */
	32	`DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
	33	`DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
	34	`DECODE_ALU: /* ALU */
	35	`DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
	36	`DECODE_LDRSTR: /* Single data transfer */
	37	`DECODE_LDMSTM: /* Block data transfer */
	38	`DECODE_BRANCH: /* Branch */
	39	`DECODE_LDCSTC: /* Coprocessor data transfer */
	40	`DECODE_CDP: /* Coprocessor data op */
	41	`DECODE_MRCMCR: /* Coprocessor register transfer */
	42	`DECODE_SWI: /* SWI */
	43	default: /* X everything else out */
60cc768b JW	44	endcase
	45	`endif
	46
e216a134 JW	47	/* Flag setting */
	48	reg use_cpsr;
	49	reg [15:0] use_regs;
	50	reg def_cpsr;
	51	reg [15:0] def_regs;
	52
	53	function [15:0] idxbit;
	54	input [3:0] r;
7aa8541b JW	55	if (r == 15)
	56	idxbit = 0;
	57	else
	58	idxbit = (16'b1) << r;
e216a134 JW	59	endfunction
	60
	61	wire [3:0] rn = insn[19:16];
	62	wire [3:0] rd = insn[15:12];
7aa8541b	63	wire [3:0] rs = insn[11:8];
e216a134 JW	64	wire [3:0] rm = insn[3:0];
	65	wire [3:0] cond = insn[31:28];
	66
	67	wire [3:0] rd_mul = insn[19:16];
	68	wire [3:0] rn_mul = insn[15:12];
	69	wire [3:0] rs_mul = insn[11:8];
	70
7aa8541b JW	71	wire [3:0] alu_opc = insn[24:21];
	72
	73	function alu_is_logical;
	74	input [3:0] op;
	75
	76	case (op)
	77	`ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1;
	78	default: alu_is_logical = 0;
	79	endcase
	80	endfunction
	81
	82	function alu_flags_only;
	83	input [3:0] op;
	84
	85	case (op)
	86	`ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1;
	87	default: alu_flags_only = 0;
	88	endcase
	89	endfunction
	90
	91	function shift_requires_carry;
	92	input [7:0] shift;
	93
	94	case(shift[1:0])
	95	`SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0);
	96	`SHIFT_LSR: shift_requires_carry = 0;
	97	`SHIFT_ASR: shift_requires_carry = 0;
	98	`SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0);
	99	endcase
	100	endfunction
	101
e216a134	102	always @(*)
7aa8541b	103	casez (insn)
6b8a01fa	104	`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
e216a134 JW	105	begin
	106	use_cpsr = `COND_MATTERS(cond);
	107	use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) \| idxbit(rs_mul) \| idxbit(rm);
	108	def_cpsr = insn[20] /* setcc */;
	109	def_regs = idxbit(rd_mul);
	110	end
6b8a01fa JW	111	// `DECODE_ALU_MUL_LONG: /* Multiply long */
6b8a01fa JW	112	`DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
7aa8541b JW	113	begin
	114	use_cpsr = `COND_MATTERS(cond) \|\| (insn[22] == 0) /* Source = CPSR */;
	115	use_regs = 0;
	116	def_cpsr = 0;
	117	def_regs = idxbit(rd);
	118	end
6b8a01fa	119	`DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
7aa8541b JW	120	begin
	121	use_cpsr = `COND_MATTERS(cond);
	122	use_regs = idxbit(rm);
	123	def_cpsr = 1;
	124	def_regs = 0;
	125	end
6b8a01fa	126	`DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
7aa8541b JW	127	begin
	128	use_cpsr = `COND_MATTERS(cond);
	129	use_regs = insn[25] ? 0 : idxbit(rm);
	130	def_cpsr = 1;
	131	def_regs = 0;
	132	end
6b8a01fa	133	`DECODE_ALU_SWP: /* Atomic swap */
7aa8541b JW	134	begin
	135	use_cpsr = `COND_MATTERS(cond);
	136	use_regs = idxbit(rn) \| idxbit(rm);
	137	def_cpsr = 0;
	138	def_regs = idxbit(rd);
	139	end
6b8a01fa	140	`DECODE_ALU_BX: /* Branch */
7aa8541b JW	141	begin
	142	use_cpsr = `COND_MATTERS(cond);
	143	use_regs = idxbit(rm);
	144	def_cpsr = 0; // don't care, we'll never get there
	145	def_regs = 0;
	146	end
6b8a01fa	147	`DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
7aa8541b JW	148	begin
	149	use_cpsr = `COND_MATTERS(cond);
	150	use_regs = idxbit(rn) \| idxbit(rm) \| (insn[20] /* L */ ? 0 : idxbit(rd));
	151	def_cpsr = 0;
	152	def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
	153	end
6b8a01fa	154	`DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
7aa8541b JW	155	begin
	156	use_cpsr = `COND_MATTERS(cond);
	157	use_regs = idxbit(rn) \| (insn[20] /* L */ ? 0 : idxbit(rd));
	158	def_cpsr = 0;
	159	def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
	160	end
0ede28ef JW	161	`DECODE_ALU: /* ALU */
	162	begin
	163	use_cpsr = `COND_MATTERS(cond) \| (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
	164	use_regs =
	165	(insn[25] /* I */ ? 0 :
	166	(insn[4] /* shift by reg */ ?
	167	(idxbit(rs) \| idxbit(rm)) :
	168	(idxbit(rm)))) \|
	169	(((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
cd577923	170	def_cpsr = insn[20] /* S */;
0ede28ef JW	171	def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
0ede28ef JW	172	end
6b8a01fa	173	`DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
7aa8541b JW	174	begin
	175	use_cpsr = 0;
	176	use_regs = 0;
	177	def_cpsr = 0;
	178	def_regs = 0;
	179	end
6b8a01fa JW	180	`DECODE_LDRSTR:
	181	begin
	182	use_cpsr = `COND_MATTERS(cond);
15bdd2aa	183	use_regs = idxbit(rn) \| (insn[25] /* I / ? idxbit(rm) : 0) \| (insn[20] / L */ ? 0 : idxbit(rd));
6b8a01fa JW	184	def_cpsr = 0;
	185	def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
	186	end
	187	`DECODE_LDMSTM: /* Block data transfer */
7aa8541b JW	188	begin
	189	use_cpsr = `COND_MATTERS(cond);
	190	use_regs = idxbit(rn) \| (insn[20] /* L */ ? 0 : insn[15:0]);
	191	def_cpsr = insn[22]; /* This is a superset of all cases, anyway. */
	192	def_regs = (insn[21] /* W / ? idxbit(rn) : 0) \| (insn[20] / L */ ? insn[15:0] : 0);
	193	end
6b8a01fa	194	`DECODE_BRANCH: /* Branch */
7aa8541b JW	195	begin
	196	use_cpsr = `COND_MATTERS(cond);
	197	use_regs = 0;
	198	def_cpsr = 0;
	199	def_regs = 0;
	200	end
6b8a01fa	201	`DECODE_LDCSTC: /* Coprocessor data transfer */
7aa8541b JW	202	begin
	203	use_cpsr = `COND_MATTERS(cond);
	204	use_regs = idxbit(rn);
	205	def_cpsr = 0;
	206	def_regs = insn[21] /* W */ ? idxbit(rn) : 0;
	207	end
6b8a01fa	208	`DECODE_CDP: /* Coprocessor data op */
7aa8541b JW	209	begin
	210	use_cpsr = `COND_MATTERS(cond);
	211	use_regs = 0;
	212	def_cpsr = 0;
	213	def_regs = 0;
	214	end
6b8a01fa	215	`DECODE_MRCMCR: /* Coprocessor register transfer */
7aa8541b JW	216	begin
	217	use_cpsr = `COND_MATTERS(cond);
	218	use_regs = insn[20] /* L */ ? 0 : idxbit(rd);
	219	def_cpsr = 0;
	220	def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
	221	end
6b8a01fa	222	`DECODE_SWI: /* SWI */
7aa8541b JW	223	begin
	224	use_cpsr = `COND_MATTERS(cond);
	225	use_regs = 0;
	226	def_cpsr = 0;
	227	def_regs = 0;
	228	end
e216a134	229	default: /* X everything else out */
7aa8541b JW	230	begin
	231	use_cpsr = 1'bx;
	232	use_regs = 16'bxxxxxxxxxxxxxxxx;
	233	def_cpsr = 1'bx;
	234	def_regs = 16'bxxxxxxxxxxxxxxxx;
	235	end
e216a134	236	endcase
ae281afd JW	237
	238	/* Condition checking logic */
	239	reg condition_met;
	240	always @(*)
	241	casez(insn[31:28])
	242	`COND_EQ: condition_met = cpsr[`CPSR_Z];
	243	`COND_NE: condition_met = !cpsr[`CPSR_Z];
	244	`COND_CS: condition_met = cpsr[`CPSR_C];
	245	`COND_CC: condition_met = !cpsr[`CPSR_C];
	246	`COND_MI: condition_met = cpsr[`CPSR_N];
	247	`COND_PL: condition_met = !cpsr[`CPSR_N];
	248	`COND_VS: condition_met = cpsr[`CPSR_V];
	249	`COND_VC: condition_met = !cpsr[`CPSR_V];
	250	`COND_HI: condition_met = cpsr[`CPSR_C] && !cpsr[`CPSR_Z];
	251	`COND_LS: condition_met = !cpsr[`CPSR_C] \|\| cpsr[`CPSR_Z];
	252	`COND_GE: condition_met = cpsr[`CPSR_N] == cpsr[`CPSR_V];
	253	`COND_LT: condition_met = cpsr[`CPSR_N] != cpsr[`CPSR_V];
	254	`COND_GT: condition_met = !cpsr[`CPSR_Z] && (cpsr[`CPSR_N] == cpsr[`CPSR_V]);
	255	`COND_LE: condition_met = cpsr[`CPSR_Z] \|\| (cpsr[`CPSR_N] != cpsr[`CPSR_V]);
	256	`COND_AL: condition_met = 1;
	257	`COND_NV: condition_met = 0;
	258	default: condition_met = 1'bx;
	259	endcase
	260
	261	/* Issue logic */
6595c4c8 JW	262	`define STAGE_EXECUTE 0
	263	`define STAGE_MEMORY 1
	264	/* Once it's hit writeback, it's essentially hit the regfile so you're done. */
	265	reg cpsr_inflight [1:0];
	266	reg [15:0] regs_inflight [1:0];
	267
	268	reg waiting_cpsr;
	269	reg waiting_regs;
	270	wire waiting = waiting_cpsr \| waiting_regs;
	271
3ae4e7db JW	272	initial
	273	begin
	274	cpsr_inflight[0] = 0;
	275	cpsr_inflight[1] = 0;
	276	regs_inflight[0] = 0;
	277	regs_inflight[1] = 0;
	278	end
	279
6595c4c8 JW	280	always @(*)
	281	begin
	282	waiting_cpsr = use_cpsr & (cpsr_inflight[0] \| cpsr_inflight[1]);
	283	waiting_regs = \|(use_regs & (regs_inflight[0] \| regs_inflight[1]));
90ff449a	284
c4e2ac3b	285	outstall = (waiting && !inbubble && !flush) \|\| stall; /* Happens in an always @, because it is an exception. /
6595c4c8	286	end
c4e2ac3b JW	287
	288	reg delayedflush = 0;
	289	always @(posedge clk)
	290	if (flush && outstall /* halp! I can't do it now, maybe later? */)
	291	delayedflush <= 1;
	292	else if (!outstall /* anything has been handled this time around */)
	293	delayedflush <= 0;
6595c4c8 JW	294
6595c4c8 JW	295	/* Actually do the issue. */
6595c4c8 JW	296	always @(posedge clk)
6595c4c8 JW	297	begin
1c2e57dc	298	if (waiting)
1c2e57dc	299	$display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs);
149bcd1a	300
c4e2ac3b	301	if((flush \|\| delayedflush) && !outstall)
149bcd1a CL	302	begin
	303	cpsr_inflight[0] = 1'b0;
	304	cpsr_inflight[1] = 1'b0;
	305	regs_inflight[0] = 16'b0;
	306	regs_inflight[1] = 16'b0;
739fa95a	307	outbubble <= 1'b1;
149bcd1a CL	308	end
149bcd1a CL	309	else if (!stall)
4ddc4b72 JW	310	begin
	311	cpsr_inflight[0] <= cpsr_inflight[1]; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
	312	cpsr_inflight[1] <= (waiting \|\| inbubble \|\| !condition_met) ? 0 : def_cpsr;
	313	regs_inflight[0] <= regs_inflight[1];
	314	regs_inflight[1] <= (waiting \|\| inbubble \|\| !condition_met) ? 0 : def_regs;
	315
739fa95a	316	outbubble <= inbubble \| waiting \| !condition_met;
4ddc4b72 JW	317	outpc <= inpc;
4ddc4b72 JW	318	outinsn <= insn;
1c2e57dc	319	end
6595c4c8	320	end
60cc768b	321	endmodule