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(parent: 5ca2794) | patch
Add verbosity to issue when it stalls an instruction.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 27 Dec 2008 10:38:49 +0000 (05:38 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 27 Dec 2008 10:38:49 +0000 (05:38 -0500)
commit1c2e57dc81bb31f2f577481bac788d279956dc39
tree17809b81fc0fdf8107d1eb716763b5ddb5bc792ftree | snapshot
parent5ca2794992bb38cc521e32c47fba9135a2e2fbd5commit | diff
Add verbosity to issue when it stalls an instruction.
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FireARM pipelined ARM-like CPU implementation in Verilog
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