Update copypasta fodder.
[firearm.git] / Issue.v
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60cc768b
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1module Issue(
2 input clk,
3 input Nrst,
4
5 input stall, /* pipeline control */
6 input flush,
7
8 input inbubble, /* stage inputs */
9 input [31:0] insn,
10 input [31:0] inpc,
11
12 output reg outbubble, /* stage outputs */
13 output reg [31:0] outpc
14 /* other */
15 );
16
17 always @(posedge clk)
18 begin
19 outbubble <= inbubble;
20 outpc <= inpc;
21 end
22
23`ifdef COPY_PASTA_FODDER
24 /* from page 2 of ARM7TDMIvE2.pdf */
25 casex (insn)
26 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
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27// 32'b????00001???????????????1001????: /* Multiply long */
28 32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */
29 32'b????00010?101001111100000000????: /* MSR (Transfer register to PSR) */
30 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
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31 32'b????00??????????????????????????: /* ALU */
32 32'b????00010?00????????00001001????: /* Atomic swap */
33 32'b????000100101111111111110001????: /* Branch */
34 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
35 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */
36 32'b????011????????????????????1????: /* Undefined. I hate ARM */
37 32'b????01??????????????????????????: /* Single data transfer */
38 32'b????100?????????????????????????: /* Block data transfer */
39 32'b????101?????????????????????????: /* Branch */
40 32'b????110?????????????????????????: /* Coprocessor data transfer */
41 32'b????1110???????????????????0????: /* Coprocessor data op */
42 32'b????1110???????????????????1????: /* Coprocessor register transfer */
43 32'b????1111????????????????????????: /* SWI */
e216a134 44 default: /* X everything else out */
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45 endcase
46`endif
47
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48`ifdef WIP
49 /* Flag setting */
50 reg use_cpsr;
51 reg [15:0] use_regs;
52 reg def_cpsr;
53 reg [15:0] def_regs;
54
55 function [15:0] idxbit;
56 input [3:0] r;
57 idxbit = (16'b1) << r;
58 endfunction
59
60 wire [3:0] rn = insn[19:16];
61 wire [3:0] rd = insn[15:12];
62 wire [3:0] rm = insn[3:0];
63 wire [3:0] cond = insn[31:28];
64
65 wire [3:0] rd_mul = insn[19:16];
66 wire [3:0] rn_mul = insn[15:12];
67 wire [3:0] rs_mul = insn[11:8];
68
69 always @(*)
70 casex (insn)
71 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
72 begin
73 use_cpsr = `COND_MATTERS(cond);
74 use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
75 def_cpsr = insn[20] /* setcc */;
76 def_regs = idxbit(rd_mul);
77 end
78// 32'b????00001???????????????1001????: /* Multiply long */
79 32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */
80 32'b????00010?101001111100000000????: /* MSR (Transfer register to PSR) */
81 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
82 32'b????00??????????????????????????: /* ALU */
83 32'b????00010?00????????00001001????: /* Atomic swap */
84 32'b????000100101111111111110001????: /* Branch */
85 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
86 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */
87 32'b????011????????????????????1????: /* Undefined. I hate ARM */
88 32'b????01??????????????????????????: /* Single data transfer */
89 32'b????100?????????????????????????: /* Block data transfer */
90 32'b????101?????????????????????????: /* Branch */
91 32'b????110?????????????????????????: /* Coprocessor data transfer */
92 32'b????1110???????????????????0????: /* Coprocessor data op */
93 32'b????1110???????????????????1????: /* Coprocessor register transfer */
94 32'b????1111????????????????????????: /* SWI */
95 default: /* X everything else out */
96 endcase
97`endif
60cc768b 98endmodule
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