memory wea
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         input [31:0] inspsr,
9         output reg [31:0] op0,
10         output reg [31:0] op1,
11         output reg [31:0] op2,
12         output reg carry,
13         output reg [31:0] outspsr,
14
15         output reg [3:0] read_0,
16         output reg [3:0] read_1,
17         output reg [3:0] read_2,
18         input [31:0] rdata_0,
19         input [31:0] rdata_1,
20         input [31:0] rdata_2
21         );
22
23         wire [31:0] regs0, regs1, regs2;
24         reg [31:0] rpc;
25         reg [31:0] op0_out, op1_out, op2_out;
26         reg carry_out;
27
28         /* shifter stuff */
29         wire [31:0] shift_oper;
30         wire [31:0] shift_res;
31         wire shift_cflag_out;
32         wire [31:0] rotate_res;
33
34         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
35         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
36         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
37
38         IREALLYHATEARMSHIFT shift(.insn(insn),
39                                   .operand(regs1),
40                                   .reg_amt(regs2),
41                                   .cflag_in(incpsr[`CPSR_C]),
42                                   .res(shift_res),
43                                   .cflag_out(shift_cflag_out));
44
45         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
46                               .amt(insn[11:8]),
47                               .res(rotate_res));
48
49         always @(*)
50                 casez (insn)
51                 `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
52 //              `DECODE_ALU_MUL_LONG,           /* Multiply long */
53                 `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
54                 `DECODE_ALU_MSR,                /* MSR (Transfer register to PSR) */
55                 `DECODE_ALU_MSR_FLAGS,          /* MSR (Transfer register or immediate to PSR, flag bits only) */
56                 `DECODE_ALU_SWP,                /* Atomic swap */
57                 `DECODE_ALU_BX,                 /* Branch and exchange */
58                 `DECODE_ALU_HDATA_REG,          /* Halfword transfer - register offset */
59                 `DECODE_ALU_HDATA_IMM,          /* Halfword transfer - register offset */
60                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
61                 `DECODE_LDRSTR,                 /* Single data transfer */
62                 `DECODE_LDMSTM,                 /* Block data transfer */
63                 `DECODE_BRANCH,                 /* Branch */
64                 `DECODE_LDCSTC,                 /* Coprocessor data transfer */
65                 `DECODE_CDP,                    /* Coprocessor data op */
66                 `DECODE_SWI:                    /* SWI */
67                         rpc = inpc + 8;
68                 `DECODE_MRCMCR:                 /* Coprocessor register transfer */
69                         rpc = inpc + 12;
70                 `DECODE_ALU:                    /* ALU */
71                         rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
72                 default:                        /* X everything else out */
73                         rpc = 32'hxxxxxxxx;
74                 endcase
75         
76         always @(*) begin
77                 read_0 = 4'hx;
78                 read_1 = 4'hx;
79                 read_2 = 4'hx;
80                 
81                 op0_out = 32'hxxxxxxxx;
82                 op1_out = 32'hxxxxxxxx;
83                 op2_out = 32'hxxxxxxxx;
84                 carry_out = 1'bx;
85                 
86                 casez (insn)
87                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
88                 begin
89                         read_0 = insn[15:12]; /* Rn */
90                         read_1 = insn[3:0];   /* Rm */
91                         read_2 = insn[11:8];  /* Rs */
92                         
93                         op0_out = regs0;
94                         op1_out = regs1;
95                         op2_out = regs2;
96                 end
97 //              `DECODE_ALU_MUL_LONG:   /* Multiply long */
98 //              begin
99 //                      read_0 = insn[11:8]; /* Rn */
100 //                      read_1 = insn[3:0];   /* Rm */
101 //                      read_2 = 4'b0;       /* anyus */
102 //
103 //                      op1_res = regs1;
104 //              end
105                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
106                 begin end
107                 `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
108                 begin
109                         read_0 = insn[3:0];     /* Rm */
110                         
111                         op0_out = regs0;
112                 end
113                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
114                 begin
115                         read_0 = insn[3:0];     /* Rm */
116                         
117                         if(insn[25]) begin     /* the constant case */
118                                 op0_out = rotate_res;
119                         end else begin
120                                 op0_out = regs0;
121                         end
122                 end
123                 `DECODE_ALU_SWP:        /* Atomic swap */
124                 begin
125                         read_0 = insn[19:16]; /* Rn */
126                         read_1 = insn[3:0];   /* Rm */
127                         
128                         op0_out = regs0;
129                         op1_out = regs1;
130                 end
131                 `DECODE_ALU_BX:         /* Branch and exchange */
132                 begin
133                         read_0 = insn[3:0];   /* Rn */
134                         
135                         op0_out = regs0;
136                 end
137                 `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
138                 begin
139                         read_0 = insn[19:16];
140                         read_1 = insn[3:0];
141                         
142                         op0_out = regs0;
143                         op1_out = regs1;
144                 end
145                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
146                 begin
147                         read_0 = insn[19:16];
148                         
149                         op0_out = regs0;
150                         op1_out = {24'b0, insn[11:8], insn[3:0]};
151                 end
152                 `DECODE_ALU:            /* ALU */
153                 begin
154                         read_0 = insn[19:16]; /* Rn */
155                         read_1 = insn[3:0];   /* Rm */
156                         read_2 = insn[11:8];  /* Rs for shift */
157                         
158                         op0_out = regs0;
159                         if(insn[25]) begin     /* the constant case */
160                                 carry_out = incpsr[`CPSR_C];
161                                 op1_out = rotate_res;
162                         end else begin
163                                 carry_out = shift_cflag_out;
164                                 op1_out = shift_res;
165                         end
166                 end
167                 `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
168                 begin
169                         /* eat shit */
170                 end
171                 `DECODE_LDRSTR:         /* Single data transfer */
172                 begin
173                         read_0 = insn[19:16]; /* Rn */
174                         read_1 = insn[3:0];   /* Rm */
175                         read_2 = insn[15:12];
176                         
177                         op0_out = regs0;
178                         if(insn[25]) begin
179                                 op1_out = {20'b0, insn[11:0]};
180                                 carry_out = incpsr[`CPSR_C];
181                         end else begin
182                                 op1_out = shift_res;
183                                 carry_out = shift_cflag_out;
184                         end
185                         op2_out = regs2;
186                 end
187                 `DECODE_LDMSTM:         /* Block data transfer */
188                 begin
189                         read_0 = insn[19:16];
190                         
191                         op0_out = regs0;
192                         op1_out = {16'b0, insn[15:0]};
193                 end
194                 `DECODE_BRANCH:         /* Branch */
195                 begin
196                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
197                 end
198                 `DECODE_LDCSTC:         /* Coprocessor data transfer */
199                 begin
200                         read_0 = insn[19:16];
201                         
202                         op0_out = regs0;
203                         op1_out = {24'b0, insn[7:0]};
204                 end
205                 `DECODE_CDP:            /* Coprocessor data op */
206                 begin
207                 end
208                 `DECODE_MRCMCR:         /* Coprocessor register transfer */
209                 begin
210                         read_0 = insn[15:12];
211                         
212                         op0_out = regs0;
213                 end
214                 `DECODE_SWI:            /* SWI */
215                 begin
216                 end
217                 default:
218                         $display("Undecoded instruction");
219                 endcase
220         end
221
222         
223         always @ (posedge clk) begin
224                 op0 <= op0_out;   /* Rn - always */
225                 op1 <= op1_out; /* 'operand 2' - Rm */
226                 op2 <= op2_out;   /* thirdedge - Rs */
227                 carry <= carry_out;
228                 outspsr <= inspsr;
229         end
230
231 endmodule
232
233 module IREALLYHATEARMSHIFT(
234         input [31:0] insn,
235         input [31:0] operand,
236         input [31:0] reg_amt,
237         input cflag_in,
238         output reg [31:0] res,
239         output reg cflag_out
240 );
241         wire [5:0] shift_amt;
242         reg is_arith, is_rot;
243         wire rshift_cout;
244         wire [31:0] rshift_res;
245
246         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
247                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
248
249         SuckLessShifter barrel(.oper(operand),
250                                .carryin(cflag_in),
251                                .amt(shift_amt),
252                                .is_arith(is_arith),
253                                .is_rot(is_rot),
254                                .res(rshift_res),
255                                .carryout(rshift_cout));
256
257         always @(*)
258                 case (insn[6:5])
259                 `SHIFT_LSL: begin
260                         /* meaningless */
261                         is_rot = 1'b0;
262                         is_arith = 1'b0;
263                 end
264                 `SHIFT_LSR: begin
265                         is_rot = 1'b0;
266                         is_arith = 1'b0;
267                 end
268                 `SHIFT_ASR: begin
269                         is_rot = 1'b0;
270                         is_arith = 1'b1;
271                 end
272                 `SHIFT_ROR: begin
273                         is_rot = 1'b1;
274                         is_arith = 1'b0;
275                 end
276                 endcase
277
278         always @(*)
279                 case (insn[6:5]) /* shift type */
280                 `SHIFT_LSL:
281                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
282                 `SHIFT_LSR: begin
283                         res = rshift_res;
284                         cflag_out = rshift_cout;
285                 end
286                 `SHIFT_ASR: begin
287                         res = rshift_res;
288                         cflag_out = rshift_cout;
289                 end
290                 `SHIFT_ROR: begin
291                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
292                                 res = {cflag_in, operand[31:1]};
293                                 cflag_out = operand[0];
294                         end else begin
295                                 res = rshift_res;
296                                 cflag_out = rshift_cout;
297                         end
298                 end
299                 endcase
300 endmodule
301
302 module SuckLessShifter(
303         input [31:0] oper,
304         input carryin,
305         input [5:0] amt,
306         input is_arith,
307         input is_rot,
308         output wire [31:0] res,
309         output wire carryout
310 );
311
312         wire [32:0] stage1, stage2, stage3, stage4, stage5;
313
314         wire pushbits = is_arith & oper[31];
315
316         /* do a barrel shift */
317         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
318         assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
319         assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
320         assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
321         assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
322         assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
323
324 endmodule
325
326 module SuckLessRotator(
327         input [31:0] oper,
328         input [3:0] amt,
329         output wire [31:0] res
330 );
331
332         wire [31:0] stage1, stage2, stage3;
333         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
334         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
335         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
336         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
337
338 endmodule
339
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