-VLOGS=Uart.v Timer.v Interrupt.v GBZ80Core.v CPUDCM.v 7seg.v System.v allinsns.v insn_ld_reg_imm8.v
+VLOGS = 7seg.v GBZ80Core.v insn_call-callcc.v insn_incdec16.v \
+ insn_jr-jrcc.v insn_ld_reg_hl.v insn_ld_reg_reg.v insn_nop.v \
+ insn_ret-retcc.v Interrupt.v Uart.v allinsns.v insn_alu8.v \
+ insn_di-ei.v insn_jp_hl.v insn_ldh_ac.v insn_ld_reg_imm16.v \
+ insn_ld_sp_hl.v insn_pop_reg.v insn_rst.v System.v CPUDCM.v \
+ insn_alu_a.v insn_halt.v insn_jp-jpcc.v insn_ld_hl_reg.v \
+ insn_ld_reg_imm8.v insn_ldx_ahl.v insn_push_reg.v insn_vop_intr.v \
+ Timer.v
-all: CoreTop.svf CoreTop.twr
+all: CoreTop_rom.svf CoreTop_diag.svf CoreTop.twr
CoreTop.ngc: CoreTop.xst CoreTop.prj $(VLOGS) CoreTop.ucf
xst -ifn CoreTop.xst -ofn CoreTop.syr
-CoreTop.ngd: CoreTop.ngc foo.bmm
- ngdbuild -dd _ngo -nt timestamp -i -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
+CoreTop.ngd: CoreTop.ngc foo.bmm CoreTop.ucf
+ ngdbuild -dd _ngo -uc CoreTop.ucf -nt timestamp -bm "foo.bmm" -p xc3s500e-fg320-5 "CoreTop.ngc" CoreTop.ngd
CoreTop_map.ncd: CoreTop.ngd
map -p xc3s500e-fg320-5 -cm area -pr off -k 4 -c 100 -o CoreTop_map.ncd CoreTop.ngd CoreTop.pcf
CoreTop.bit: CoreTop.ut CoreTop.ncd
bitgen -f CoreTop.ut CoreTop.ncd
-CoreTop_rom.bit: rom.hex CoreTop.bit foo_bd.bmm
- data2mem -bm foo_bd.bmm -bd rom.mem -bt CoreTop.bit -o b CoreTop_rom.bit
+%.o: %.asm
+ rgbasm -o$@ $<
-CoreTop.svf: CoreTop_rom.bit rom.hex impact.cmd
- impact -batch impact.cmd
+%.bin: %.o rom.lnk
+ echo "[Objects]" > tmp.lnk
+ echo $< >> tmp.lnk
+ echo "" >> tmp.lnk
+ echo "[Output]" >> tmp.lnk
+ echo $@ >> tmp.lnk
+ xlink tmp.lnk
+ rm tmp.lnk
-rom.o: rom.asm
- rgbasm -orom.o rom.asm
+%.mem: %.bin
+ ./mashrom < $< > $@
-rom.bin: rom.o rom.lnk
- xlink rom.lnk
+CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
+ data2mem -bm foo_bd.bmm -bd $< -bt CoreTop.bit -o b $@
-rom.hex: rom.bin
- ./mashrom < rom.bin > rom.hex
+CoreTop_%.svf: CoreTop_%.bit impact.cmd
+ sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
+ impact -batch tmp.cmd
--- /dev/null
+ SECTION "a",HOME
+
+main:
+ ld c, $51 ; Note that we are alive.
+ ld a, $FF
+ ld [c],a
+
+ ld sp, $DFF0
+
+ ld hl, signon
+ call puts
+
+ call memtest
+
+ call insntest
+
+ call waitsw
+
+ jr main
+
+signon:
+ db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
+
+; Memory tester: writes h ^ l to all addresses from C000 to DF80.
+memtest:
+ ld hl,memteststr
+ call puts
+
+ ld hl, $C001 ; Write loop
+.wr:
+ ld a,h
+ xor l
+ ld [hli],a
+ ld a, $DF
+ cp h
+ jr nz, .wr
+ ld a, $80
+ cp l
+ jr nz, .wr
+
+ ld hl, $C001 ; Read loop
+.rd:
+ ld a,h
+ xor l
+ ld b,a
+ ld a, [hli]
+ cp b
+ jr nz, .memfail
+
+ ld a, $DF
+ cp h
+ jr nz, .rd
+ ld a, $80
+ cp l
+ jr nz, .rd
+
+ ld hl, testokstr ; Say we're OK
+ call puts
+ ret
+.memfail: ; Say we failed (sadface)
+ ; decrement hl the easy way
+ ld a,[hld]
+ push hl
+ ld hl, failatstr
+ call puts
+ pop hl
+ ld a, h
+ call puthex
+ ld a, l
+ call puthex
+ ld a, $0A
+ call putc
+ ld a, $0D
+ call putc
+ ret
+memteststr:
+ db "Testing memory from $C000 to $DF80...",0
+testokstr:
+ db " OK!",$0D,$0A,0
+failatstr:
+ db " Test failed at $",0
+
+puthex: ; Put two hex nibbles to the serial console.
+ push af
+ rra
+ rra
+ rra
+ rra
+ ld b,$0F
+ and b
+ ld b,$30
+ add b
+ call putc
+ pop af
+ ld b,$0F
+ and b
+ ld b,$30
+ add b
+ call putc
+ ret
+
+; Wait for switches to be flipped on and off again.
+waitsw:
+ ld hl,waitswstr
+ call puts
+
+ ld c, $51
+ xor a
+ ld [c],a
+
+ ld b, $0
+.loop1:
+ ld a,[c]
+ cp b
+ jr z,.loop1
+.loop2:
+ ld a,[c]
+ cp b
+ jr nz,.loop2
+ ret
+
+waitswstr:
+ db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset. Expect A.",$0D,$0A,0
+
+; Core instruction basic acceptance tests.
+insntest:
+ ld hl, .insnteststr
+ call puts
+
+ ; Test PUSH and POP.
+ ld b, $12
+ ld c, $34
+ ld d, $56
+ ld e, $78
+ push bc
+ pop de
+ ld hl, .pushpopfail
+ ld a, d
+ cp b
+ jr nz,.fail
+ ld a, e
+ cp c
+ jr nz,.fail
+
+ ; Test ALU (HL).
+ ld hl, .ff
+ ld a, $FF
+ xor [hl]
+ ld hl, .xorhlfail
+ jr nz, .fail
+
+ ; Test JP (HL)
+ ld hl, .jphl
+ jp [hl]
+ ld hl, .jphlfail
+ jr .fail
+ rst $00
+.jphl:
+
+ ; Test JR
+ ld a, $FF
+ ld b, $00
+ cp b
+ jr nz,.jr
+ ld hl, .jrfail
+ jr .fail
+ rst $00
+.jr:
+
+ ; Test inc16
+ ld d, $12
+ ld e, $FF
+ ld hl, .inc16fail
+ inc de
+ ld a, $13
+ cp d
+ jr nz, .fail
+ ld a, $00
+ cp e
+ jr nz, .fail
+
+ ; Test CP.
+ ld hl, .cpfail
+ ld a, $10
+ ld b, $20
+ cp b
+ jr nc,.fail
+ ld a, $20
+ ld b, $10
+ cp b
+ jr c,.fail
+
+ ; Test CPL
+ ld hl, .cplfail
+ ld a, $55
+ ld b, $AA
+ cpl
+ cp b
+ jr nz,.fail
+
+ ld hl, .ok
+ call puts
+ ret
+.fail:
+ call puts
+ ld hl, .testfailed
+ call puts
+ ret
+.insnteststr:
+ db "Testing instructions... ",0
+.pushpopfail:
+ db "PUSH/POP",0
+.ff:
+ db $FF
+.xorhlfail:
+ db "XOR [HL]",0
+.jphlfail:
+ db "JP [HL]",0
+.jrfail:
+ db "JR",0
+.cpfail:
+ db "CP",0
+.cplfail:
+ db "CPL",0
+.inc16fail:
+ db "INC16",0
+.testfailed:
+ db " test failed.",$0D,$0A,0
+.ok:
+ db "OK!",$0D,$0A,0
+
+; Serial port manipulation functions.
+putc:
+ ld b, 0
+ ld c, $50
+ push af
+.waitport:
+ ld a,[c]
+ cp b
+ jr nz,.waitport
+ pop af
+ ld [c],a
+ ret
+
+puts:
+ ld a, [hli]
+ ld b, $00
+ cp b
+ ret z
+ call putc
+ jr puts
setMode -bs
-setCable -port svf -file "/home/joshua/projects/fpga/FPGABoy/CoreTop.svf"
-addDevice -p 1 -file "/home/joshua/projects/fpga/FPGABoy/CoreTop_rom.bit"
+setCable -port svf -file "/home/joshua/projects/fpga/FPGABoy/XXX.svf"
+addDevice -p 1 -file "/home/joshua/projects/fpga/FPGABoy/XXX.bit"
addDevice -p 2 -part xcf04s
Program -p 1 -defaultVersion 0
quit
ld sp, $DFF0
- ld hl, $DF81
- ld a, $80
- ld [hl], a
+; ld hl, $DF81
+; ld a, $80
+; ld [hl], a
; ld c, $07
-; ld a, $04 ;start timer, 4.096KHz
+; ld a, $07 ;start timer, 4.096KHz
; ld [c], a
-diqs:; ei
- jr diqs
-
- ld hl, signon
- call puts
-
-
- ei
-
- call memtest
-
- call insntest
+;diqs: ei
+; ld a, $80
+; ld c, $51
+; ld [c], a
+; jr diqs
+ call irqhand
+coqs: jr coqs
- call waitsw
+ section "Diq", HOME[$38]
+fuqed:
di
+ jr fuqed
- jr main
-
- section "fuq",HOME[$50]
+ section "fuq",HOME[$100]
irqhand:
PUSH AF
PUSH BC
;ld a, $41 ; print A
;call putc
- ld hl, $DF81
- ld a, [hl]
+; ld hl, $DF81
+; ld a, [hl]
; ld b, 1
; add b
- ld c, $51
-; ld [c], a
-; ld [hl], a
+ ld a, $08
+ ld hl, $FF51
+; ld c, $51
+ nop
+ nop
+ ld [hl], a
; ld c, $51
POP BC
POP AF
RETI
-
-signon:
- db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
-
-; Memory tester: writes h ^ l to all addresses from C000 to DF80.
-memtest:
- ld hl,memteststr
- call puts
-
- ld hl, $C001 ; Write loop
-.wr:
- ld a,h
- xor l
- ld [hli],a
- ld a, $DF
- cp h
- jr nz, .wr
- ld a, $80
- cp l
- jr nz, .wr
-
- ld hl, $C001 ; Read loop
-.rd:
- ld a,h
- xor l
- ld b,a
- ld a, [hli]
- cp b
- jr nz, .memfail
-
- ld a, $DF
- cp h
- jr nz, .rd
- ld a, $80
- cp l
- jr nz, .rd
-
- ld hl, testokstr ; Say we're OK
- call puts
- ret
-.memfail: ; Say we failed (sadface)
- ; decrement hl the easy way
- ld a,[hld]
- push hl
- ld hl, failatstr
- call puts
- pop hl
- ld a, h
- call puthex
- ld a, l
- call puthex
- ld a, $0A
- call putc
- ld a, $0D
- call putc
- ret
-memteststr:
- db "Testing memory from $C000 to $DF80...",0
-testokstr:
- db " OK!",$0D,$0A,0
-failatstr:
- db " Test failed at $",0
-
-puthex: ; Put two hex nibbles to the serial console.
- push af
- rra
- rra
- rra
- rra
- ld b,$0F
- and b
- ld b,$30
- add b
- call putc
- pop af
- ld b,$0F
- and b
- ld b,$30
- add b
- call putc
- ret
-
-; Wait for switches to be flipped on and off again.
-waitsw:
- ld hl,waitswstr
- call puts
-
- ld c, $51
- xor a
- ld [c],a
-
- ld b, $0
-.loop1:
- ld a,[c]
- cp b
- ei
- jr z,.loop1
-.loop2:
- ld a,[c]
- cp b
- jr nz,.loop2
- ret
-
-waitswstr:
- db "Diagnostic ROM complete; flip switches to nonzero and then to zero to reset. Expect A.",$0D,$0A,0
-
-; Core instruction basic acceptance tests.
-insntest:
- ld hl, .insnteststr
- call puts
-
- ; Test PUSH and POP.
- ld b, $12
- ld c, $34
- ld d, $56
- ld e, $78
- push bc
- pop de
- ld hl, .pushpopfail
- ld a, d
- cp b
- jr nz,.fail
- ld a, e
- cp c
- jr nz,.fail
-
- ; Test ALU (HL).
- ld hl, .ff
- ld a, $FF
- xor [hl]
- ld hl, .xorhlfail
- jr nz, .fail
-
- ; Test JP (HL)
- ld hl, .jphl
- jp [hl]
- ld hl, .jphlfail
- jr .fail
- rst $00
-.jphl:
-
- ; Test JR
- ld a, $FF
- ld b, $00
- cp b
- jr nz,.jr
- ld hl, .jrfail
- jr .fail
- rst $00
-.jr:
-
- ; Test inc16
- ld d, $12
- ld e, $FF
- ld hl, .inc16fail
- inc de
- ld a, $13
- cp d
- jr nz, .fail
- ld a, $00
- cp e
- jr nz, .fail
-
- ; Test CP.
- ld hl, .cpfail
- ld a, $10
- ld b, $20
- cp b
- jr nc,.fail
- ld a, $20
- ld b, $10
- cp b
- jr c,.fail
-
- ; Test CPL
- ld hl, .cplfail
- ld a, $55
- ld b, $AA
- cpl
- cp b
- jr nz,.fail
-
- ld hl, .ok
- call puts
- ret
-.fail:
- call puts
- ld hl, .testfailed
- call puts
- ret
-.insnteststr:
- db "Testing instructions... ",0
-.pushpopfail:
- db "PUSH/POP",0
-.ff:
- db $FF
-.xorhlfail:
- db "XOR [HL]",0
-.jphlfail:
- db "JP [HL]",0
-.jrfail:
- db "JR",0
-.cpfail:
- db "CP",0
-.cplfail:
- db "CPL",0
-.inc16fail:
- db "INC16",0
-.testfailed:
- db " test failed.",$0D,$0A,0
-.ok:
- db "OK!",$0D,$0A,0
-
-; Serial port manipulation functions.
-putc:
- ld b, 0
- ld c, $50
- push af
-.waitport:
- ld a,[c]
- cp b
- jr nz,.waitport
- pop af
- ld [c],a
- ret
-
-puts:
- ld a, [hli]
- ld b, $00
- cp b
- ret z
- call putc
- jr puts
+ db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+ db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
+ db $18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE,$18,$FE
git.joshuawise.com / fpgaboy.git / commitdiff