Joshua Wise's Git repositories - firearm.git/search

]> Joshua Wise's Git repositories - firearm.git/search

git.joshuawise.com / firearm.git / search

2009-01-07	Joshua Wise	Decode: Set correct rpc for coprocessor register transfer.	commit \| commitdiff \| tree
2009-01-07	Joshua Wise	Add special CPSR behavior for ARM MCR.	commit \| commitdiff \| tree
2009-01-07	Joshua Wise	Add LDR test instruction.	commit \| commitdiff \| tree
2009-01-07	Joshua Wise	Memory: Add CDP and MRC/MCR.	commit \| commitdiff \| tree
2009-01-07	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2009-01-07	Joshua Wise	Memory: Add coprocessor interface stub.	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	system: Remember to wire the DCache to the memory!	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Wire in Memory. Fix small bug in Memory involving...	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	st_data -> op2	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Merge Memory.	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Memory.v: Cleanup pass 1 before integration.	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	System.v: Wire up DCache	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	system.v: Silly typo fix -- why didn't Verilator warn...	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Execute.v: Add outpc and outinsn. System.v: Add and...	commit \| commitdiff \| tree
2009-01-06	Joshua Wise	Add the DCache.	commit \| commitdiff \| tree
2009-01-05	Joshua Wise	Ok, it work.	commit \| commitdiff \| tree
2009-01-05	Joshua Wise	Add a jump test	commit \| commitdiff \| tree
2009-01-05	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2009-01-05	Joshua Wise	Isuse.v: fix error in which cpsr was marked as defined...	commit \| commitdiff \| tree
2009-01-05	Joshua Wise	Add SPSR logic to Execute.	commit \| commitdiff \| tree
2008-12-31	Joshua Wise	Add skeleton to Execute.v	commit \| commitdiff \| tree
2008-12-30	Joshua Wise	Cleanup pass on Decode. We may have to revert this...	commit \| commitdiff \| tree
2008-12-30	Joshua Wise	Fix up ALU order in Issue.	commit \| commitdiff \| tree
2008-12-30	Joshua Wise	Fix up Issue to use the new constants.	commit \| commitdiff \| tree
2008-12-30	Joshua Wise	Convert decode to... use decode constants.	commit \| commitdiff \| tree
2008-12-30	Joshua Wise	Add decode constants.	commit \| commitdiff \| tree
2008-12-30	Joshua Wise	Add wires for ALU.	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	Fix stupid pc request in Fetch	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	fixups to get workign compilation with isim	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	with more reg	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	do some first pass Execute wiring	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	holy shit my multiplier compiled the first time o__o	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	elanus	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	Add testbench	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	add execute skeleton	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	Return decode to a state of cleanliness.	commit \| commitdiff \| tree
2008-12-28	Joshua Wise	Ok, move read_0, read_1, read_2 back into a unified...	commit \| commitdiff \| tree
2008-12-27	Joshua Wise	Add verbosity to issue when it stalls an instruction.	commit \| commitdiff \| tree
2008-12-27	Joshua Wise	Wire up decode.	commit \| commitdiff \| tree
2008-12-27	Joshua Wise	Fix up decode	commit \| commitdiff \| tree
2008-12-27	Joshua Wise	assign read_0 out	commit \| commitdiff \| tree
2008-12-27	Joshua Wise	Nicer dump information.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	name normalization pass	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Deal with at least one case of A in decode by moving...	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Merge nyus:/storage/git/firearm	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Ok, A mitigated.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Initialize more things, and follow more clocking rules.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Only emit a stall if we didn't take a bubble in.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	initialize inflights	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Wire things up, and fix circular logic in issue.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Actually do the issue???	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Add condition checking logic.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Commit flag setter for issue.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Update copypasta fodder.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Add more constants.	commit \| commitdiff \| tree
2008-12-26	Joshua Wise	Add some ARM constants.	commit \| commitdiff \| tree
2008-12-25	Joshua Wise	a bit of issue	commit \| commitdiff \| tree
2008-12-24	Joshua Wise	Add the register file.	commit \| commitdiff \| tree
2008-12-22	Joshua Wise	system.v	commit \| commitdiff \| tree
2008-12-20	Joshua Wise	Bug fixes, and a first cut at a bus arbiter	commit \| commitdiff \| tree
2008-12-19	Joshua Wise	Fix syntax errors and make it compile in verilator.	commit \| commitdiff \| tree
2008-12-19	Joshua Wise	actually fill the cache?	commit \| commitdiff \| tree
2008-12-19	Joshua Wise	some work on cache filling, and fleshing out a bus...	commit \| commitdiff \| tree
2008-09-01	Joshua Wise	Fix tag position	commit \| commitdiff \| tree
2008-09-01	Joshua Wise	Add icache kind of	commit \| commitdiff \| tree

FireARM pipelined ARM-like CPU implementation in Verilog

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