Deal with at least one case of A in decode by moving rpc out to its own case statemen...
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 26 Dec 2008 13:36:25 +0000 (08:36 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Fri, 26 Dec 2008 13:36:25 +0000 (08:36 -0500)
Decode.v

index 5690062..f38ca0d 100644 (file)
--- a/Decode.v
+++ b/Decode.v
@@ -2,7 +2,7 @@
 
 module Decode(
        input clk,
-       input [31:0] ansn,
+       input [31:0] insn,
        input [31:0] inpc,
        input [31:0] cps_in,
        output reg [31:0] op0,
@@ -30,92 +30,108 @@ module Decode(
        assign regs1 = (regsel1 == 4'b1111) ? rpc : iregs1;
        assign regs2 = iregs2; /* use regs2 for things that cannot be r15 */
 
-       IHATEARMSHIFT blowme(.insn(ansn),
+       IHATEARMSHIFT blowme(.insn(insn),
                             .operand(regs1),
                             .reg_amt(regs2),
                             .cflag_in(cps_in[`CPSR_C]),
                             .res(shift_res),
                             .cflag_out(shift_cflag_out));
+       
+       always @(*)
+               casez (insn)
+               32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
+//             32'b????00001???????????????1001????,   /* Multiply long */
+               32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
+               32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
+               32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
+               32'b????00010?00????????00001001????,   /* Atomic swap */
+               32'b????000100101111111111110001????,   /* Branch */
+               32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
+               32'b????011????????????????????1????,   /* Undefined. I hate ARM */
+               32'b????01??????????????????????????,   /* Single data transfer */
+               32'b????100?????????????????????????,   /* Block data transfer */
+               32'b????101?????????????????????????,   /* Branch */
+               32'b????110?????????????????????????,   /* Coprocessor data transfer */
+               32'b????1110???????????????????0????,   /* Coprocessor data op */
+               32'b????1110???????????????????1????,   /* Coprocessor register transfer */
+               32'b????1111????????????????????????:   /* SWI */
+                       rpc = inpc - 8;
+               32'b????00??????????????????????????:   /* ALU */
+                       rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
+               default:                                /* X everything else out */
+                       rpc = 32'hxxxxxxxx;
+               endcase
 
        always @ (*) begin
-               casez (ansn)
+               casez (insn)
                32'b????000000??????????????1001????: begin /* Multiply */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[15:12]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       regsel2 = ansn[11:8];  /* Rs */
+                       regsel0 = insn[15:12]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */
+                       regsel2 = insn[11:8];  /* Rs */
                        op1_res = regs1;
                        new_cps = cps_in;
                end
 /*
                32'b????00001???????????????1001????: begin * Multiply long *
-                       regsel0 = ansn[11:8]; * Rn *
-                       regsel1 = ansn[3:0];  * Rm *
+                       regsel0 = insn[11:8]; * Rn *
+                       regsel1 = insn[3:0];  * Rm *
                        regsel2 = 4'b0;       * anyus *
                        op1_res = regs1;
                end
 */
                32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
-                       rpc = inpc - 8;
                        new_cps = cps_in;
                end
                32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
-                       rpc = inpc - 8;
                        new_cps = cps_in;
                end
                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
-                       rpc = inpc - 8;
                        new_cps = cps_in;
                 end
                32'b????00??????????????????????????: begin /* ALU */
-                       rpc = inpc - (ansn[25] ? 8 : (ansn[4] ? 12 : 8));
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       regsel2 = ansn[11:8];  /* Rs for shift */
-                       if(ansn[25]) begin     /* the constant case */
+                       regsel0 = insn[19:16]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */
+                       regsel2 = insn[11:8];  /* Rs for shift */
+                       if(insn[25]) begin     /* the constant case */
                                new_cps = cps_in;
-                               op1_res = ({24'b0, ansn[7:0]} >> {ansn[11:8], 1'b0}) | ({24'b0, ansn[7:0]} << (5'b0 - {ansn[11:8], 1'b0}));
+                               op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
                        end else begin
                                new_cps = {cps_in[31:30], shift_cflag_out, cps_in[28:0]};
                                op1_res = shift_res;
                        end
                end
                32'b????00010?00????????00001001????: begin /* Atomic swap */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
+                       regsel0 = insn[19:16]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */
                        regsel2 = 4'b0;        /* anyus */
                        op1_res = regs1;
                end
                32'b????000100101111111111110001????: begin /* Branch and exchange */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[3:0];   /* Rn */
+                       regsel0 = insn[3:0];   /* Rn */
                        new_cps = cps_in;
                end
                32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       regsel1 = ansn[3:0];
+                       regsel0 = insn[19:16];
+                       regsel1 = insn[3:0];
                        regsel2 = 4'b0;
                        op1_res = regs1;
                        new_cps = cps_in;
                end
                32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       regsel1 = ansn[3:0];
-                       op1_res = {24'b0, ansn[11:8], ansn[3:0]};
+                       regsel0 = insn[19:16];
+                       regsel1 = insn[3:0];
+                       op1_res = {24'b0, insn[11:8], insn[3:0]};
                        new_cps = cps_in;
                end
                32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
                        /* eat shit */
                end
                32'b????01??????????????????????????: begin /* Single data transfer */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16]; /* Rn */
-                       regsel1 = ansn[3:0];   /* Rm */
-                       if(ansn[25]) begin
-                               op1_res = {20'b0, ansn[11:0]};
+                       regsel0 = insn[19:16]; /* Rn */
+                       regsel1 = insn[3:0];   /* Rm */
+                       if(insn[25]) begin
+                               op1_res = {20'b0, insn[11:0]};
                                new_cps = cps_in;
                        end else begin
                                op1_res = shift_res;
@@ -123,32 +139,26 @@ module Decode(
                        end
                end
                32'b????100?????????????????????????: begin /* Block data transfer */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       op1_res = {16'b0, ansn[15:0]};
+                       regsel0 = insn[19:16];
+                       op1_res = {16'b0, insn[15:0]};
                        new_cps = cps_in;
                end
                32'b????101?????????????????????????: begin /* Branch */
-                       rpc = inpc - 8;
-                       op1_res = {{6{ansn[23]}}, ansn[23:0], 2'b0};
+                       op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
                        new_cps = cps_in;
                end
                32'b????110?????????????????????????: begin /* Coprocessor data transfer */
-                       rpc = inpc - 8;
-                       regsel0 = ansn[19:16];
-                       op1_res = {24'b0, ansn[7:0]};
+                       regsel0 = insn[19:16];
+                       op1_res = {24'b0, insn[7:0]};
                        new_cps = cps_in;
                end
                32'b????1110???????????????????0????: begin /* Coprocessor data op */
-                       rpc = inpc - 8;
                        new_cps = cps_in;
                end
                32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
-                       rpc = inpc - 8;
                        new_cps = cps_in;
                end
                32'b????1111????????????????????????: begin /* SWI */
-                       rpc = inpc - 8;
                        new_cps = cps_in;
                end
                default: begin end
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