Nicer dump information.
authorJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 27 Dec 2008 09:40:15 +0000 (04:40 -0500)
committerJoshua Wise <joshua@rebirth.joshuawise.com>
Sat, 27 Dec 2008 09:40:15 +0000 (04:40 -0500)
system.v

index afd7a17..de462cd 100644 (file)
--- a/system.v
+++ b/system.v
@@ -85,10 +85,12 @@ module System(input clk, output wire bubbleshield, output wire [31:0] insn, outp
                .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
                .outpc(pc_out_issue), .outinsn(insn_out_issue));
        
+       reg [31:0] clockno = 0;
        always @(posedge clk)
        begin
-               $display("Clock-time dump:");
-               $display("Fetch stage: Bubble output: %d, Instruction: %08x, PC: %08x", bubble_out_fetch, insn_out_fetch, pc_out_fetch);
-               $display("Issue stage: Stall output: %d, Bubble output: %d, Instruction: %08x, PC: %08x", stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
+               clockno <= clockno + 1;
+               $display("------------------------------------------------------------------------------");
+               $display("%3d: FETCH:           Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
+               $display("%3d: ISSUE: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
        end
 endmodule
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