[firearm.git] / Decode.v

`include "ARM_Constants.v"

module Decode(
	input clk,
	input [31:0] insn,
	input [31:0] inpc,
	input [31:0] incpsr,
	input [31:0] inspsr,
	output reg [31:0] op0,
	output reg [31:0] op1,
	output reg [31:0] op2,
	output reg carry,
	output reg [31:0] outcpsr,
	output reg [31:0] outspsr,

	output reg [3:0] read_0,
	output reg [3:0] read_1,
	output reg [3:0] read_2,
	input [31:0] rdata_0,
	input [31:0] rdata_1,
	input [31:0] rdata_2
	);

	wire [31:0] regs0, regs1, regs2;
	reg [31:0] rpc;
	reg [31:0] op0_out, op1_out, op2_out;
	reg carry_out;

	/* shifter stuff */
	wire [31:0] shift_oper;
	wire [31:0] shift_res;
	wire shift_cflag_out;
	wire [31:0] rotate_res;

	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */

	IREALLYHATEARMSHIFT shift(.insn(insn),
	                          .operand(regs1),
	                          .reg_amt(regs2),
	                          .cflag_in(incpsr[`CPSR_C]),
	                          .res(shift_res),
	                          .cflag_out(shift_cflag_out));

	SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
	                      .amt(insn[11:8]),
	                      .res(rotate_res));

	always @(*)
		casez (insn)
		`DECODE_ALU_MULT,		/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
//		`DECODE_ALU_MUL_LONG,		/* Multiply long */
		`DECODE_ALU_MRS,		/* MRS (Transfer PSR to register) */
		`DECODE_ALU_MSR,		/* MSR (Transfer register to PSR) */
		`DECODE_ALU_MSR_FLAGS,		/* MSR (Transfer register or immediate to PSR, flag bits only) */
		`DECODE_ALU_SWP,		/* Atomic swap */
		`DECODE_ALU_BX,			/* Branch and exchange */
		`DECODE_ALU_HDATA_REG,		/* Halfword transfer - register offset */
		`DECODE_ALU_HDATA_IMM,		/* Halfword transfer - register offset */
		`DECODE_LDRSTR_UNDEFINED,	/* Undefined. I hate ARM */
		`DECODE_LDRSTR,			/* Single data transfer */
		`DECODE_LDMSTM,			/* Block data transfer */
		`DECODE_BRANCH,			/* Branch */
		`DECODE_LDCSTC,			/* Coprocessor data transfer */
		`DECODE_CDP,			/* Coprocessor data op */
		`DECODE_SWI:			/* SWI */
			rpc = inpc + 8;
		`DECODE_MRCMCR:			/* Coprocessor register transfer */
			rpc = inpc + 12;
		`DECODE_ALU:			/* ALU */
			rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
		default:			/* X everything else out */
			rpc = 32'hxxxxxxxx;
		endcase
	
	always @(*) begin
		read_0 = 4'hx;
		read_1 = 4'hx;
		read_2 = 4'hx;
		
		op0_out = 32'hxxxxxxxx;
		op1_out = 32'hxxxxxxxx;
		op2_out = 32'hxxxxxxxx;
		carry_out = 1'bx;
		
		casez (insn)
		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			read_0 = insn[15:12]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs */
			
			op0_out = regs0;
			op1_out = regs1;
			op2_out = regs2;
		end
//		`DECODE_ALU_MUL_LONG:	/* Multiply long */
//		begin
//			read_0 = insn[11:8]; /* Rn */
//			read_1 = insn[3:0];   /* Rm */
//			read_2 = 4'b0;       /* anyus */
//
//			op1_res = regs1;
//		end
		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
		begin end
		`DECODE_ALU_MSR:	/* MSR (Transfer register to PSR) */
		begin
			read_0 = insn[3:0];	/* Rm */
			
			op0_out = regs0;
		end
		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		begin
			read_0 = insn[3:0];	/* Rm */
			
			if(insn[25]) begin     /* the constant case */
				op0_out = rotate_res;
			end else begin
				op0_out = regs0;
			end
		end
		`DECODE_ALU_SWP:	/* Atomic swap */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			
			op0_out = regs0;
			op1_out = regs1;
		end
		`DECODE_ALU_BX:		/* Branch and exchange */
		begin
			read_0 = insn[3:0];   /* Rn */
			
			op0_out = regs0;
		end
		`DECODE_ALU_HDATA_REG:	/* Halfword transfer - register offset */
		begin
			read_0 = insn[19:16];
			read_1 = insn[3:0];
			
			op0_out = regs0;
			op1_out = regs1;
		end
		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
		begin
			read_0 = insn[19:16];
			
			op0_out = regs0;
			op1_out = {24'b0, insn[11:8], insn[3:0]};
		end
		`DECODE_ALU:		/* ALU */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs for shift */
			
			op0_out = regs0;
			if(insn[25]) begin     /* the constant case */
				carry_out = incpsr[`CPSR_C];
				op1_out = rotate_res;
			end else begin
				carry_out = shift_cflag_out;
				op1_out = shift_res;
			end
		end
		`DECODE_LDRSTR_UNDEFINED:	/* Undefined. I hate ARM */
		begin
			/* eat shit */
		end
		`DECODE_LDRSTR:		/* Single data transfer */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[15:12];
			
			op0_out = regs0;
			if(insn[25]) begin
				op1_out = {20'b0, insn[11:0]};
				carry_out = incpsr[`CPSR_C];
			end else begin
				op1_out = shift_res;
				carry_out = shift_cflag_out;
			end
			op2_out = regs2;
		end
		`DECODE_LDMSTM:		/* Block data transfer */
		begin
			read_0 = insn[19:16];
			
			op0_out = regs0;
			op1_out = {16'b0, insn[15:0]};
		end
		`DECODE_BRANCH:		/* Branch */
		begin
			op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
		end
		`DECODE_LDCSTC:		/* Coprocessor data transfer */
		begin
			read_0 = insn[19:16];
			
			op0_out = regs0;
			op1_out = {24'b0, insn[7:0]};
		end
		`DECODE_CDP:		/* Coprocessor data op */
		begin
		end
		`DECODE_MRCMCR:		/* Coprocessor register transfer */
		begin
			read_0 = insn[15:12];
			
			op0_out = regs0;
		end
		`DECODE_SWI:		/* SWI */
		begin
		end
		default:
			$display("Undecoded instruction");
		endcase
	end

	
	always @ (posedge clk) begin
		op0 <= op0_out;   /* Rn - always */
		op1 <= op1_out; /* 'operand 2' - Rm */
		op2 <= op2_out;   /* thirdedge - Rs */
		carry <= carry_out;
		outcpsr <= incpsr;
		outspsr <= inspsr;
	end

endmodule

module IREALLYHATEARMSHIFT(
	input [31:0] insn,
	input [31:0] operand,
	input [31:0] reg_amt,
	input cflag_in,
	output reg [31:0] res,
	output reg cflag_out
);
	wire [5:0] shift_amt;
	reg is_arith, is_rot;
	wire rshift_cout;
	wire [31:0] rshift_res;

	assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
	                           : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */

	SuckLessShifter barrel(.oper(operand),
	                       .carryin(cflag_in),
	                       .amt(shift_amt),
	                       .is_arith(is_arith),
	                       .is_rot(is_rot),
	                       .res(rshift_res),
	                       .carryout(rshift_cout));

	always @(*)
		case (insn[6:5])
		`SHIFT_LSL: begin
			/* meaningless */
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_LSR: begin
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_ASR: begin
			is_rot = 1'b0;
			is_arith = 1'b1;
		end
		`SHIFT_ROR: begin
			is_rot = 1'b1;
			is_arith = 1'b0;
		end
		endcase

	always @(*)
		case (insn[6:5]) /* shift type */
		`SHIFT_LSL:
			{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
		`SHIFT_LSR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ASR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ROR: begin
			if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
				res = {cflag_in, operand[31:1]};
				cflag_out = operand[0];
			end else begin
				res = rshift_res;
				cflag_out = rshift_cout;
			end
		end
		endcase
endmodule

module SuckLessShifter(
	input [31:0] oper,
	input carryin,
	input [5:0] amt,
	input is_arith,
	input is_rot,
	output wire [31:0] res,
	output wire carryout
);

	wire [32:0] stage1, stage2, stage3, stage4, stage5;

	wire pushbits = is_arith & oper[31];

	/* do a barrel shift */
	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
	assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
	assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
	assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
	assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
	assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;

endmodule

module SuckLessRotator(
	input [31:0] oper,
	input [3:0] amt,
	output wire [31:0] res
);

	wire [31:0] stage1, stage2, stage3;
	assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
	assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
	assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
	assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;

endmodule
Commit	Line	Data
26049339 CL	1	`include "ARM_Constants.v"
26049339 CL	2
bae77231 CL	3	module Decode(
bae77231 CL	4	input clk,
be64a9df	5	input [31:0] insn,
bae77231	6	input [31:0] inpc,
821617bb	7	input [31:0] incpsr,
cb0428b6	8	input [31:0] inspsr,
bae77231 CL	9	output reg [31:0] op0,
	10	output reg [31:0] op1,
	11	output reg [31:0] op2,
42c1e610	12	output reg carry,
ab7ee9fc	13	output reg [31:0] outcpsr,
cb0428b6	14	output reg [31:0] outspsr,
bae77231	15
fbe84cc1 JW	16	output reg [3:0] read_0,
	17	output reg [3:0] read_1,
	18	output reg [3:0] read_2,
821617bb JW	19	input [31:0] rdata_0,
	20	input [31:0] rdata_1,
	21	input [31:0] rdata_2
bae77231 CL	22	);
bae77231 CL	23
fbe84cc1 JW	24	wire [31:0] regs0, regs1, regs2;
	25	reg [31:0] rpc;
	26	reg [31:0] op0_out, op1_out, op2_out;
	27	reg carry_out;
bae77231 CL	28
	29	/* shifter stuff */
	30	wire [31:0] shift_oper;
	31	wire [31:0] shift_res;
	32	wire shift_cflag_out;
a0c8a75c	33	wire [31:0] rotate_res;
bae77231	34
821617bb JW	35	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	36	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	37	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231	38
96f7e6e1 JW	39	IREALLYHATEARMSHIFT shift(.insn(insn),
	40	.operand(regs1),
	41	.reg_amt(regs2),
	42	.cflag_in(incpsr[`CPSR_C]),
	43	.res(shift_res),
	44	.cflag_out(shift_cflag_out));
e2c5d224	45
a0c8a75c CL	46	SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
	47	.amt(insn[11:8]),
	48	.res(rotate_res));
	49
be64a9df JW	50	always @(*)
be64a9df JW	51	casez (insn)
2c523f8a JW	52	`DECODE_ALU_MULT, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	53	// `DECODE_ALU_MUL_LONG, /* Multiply long */
	54	`DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
	55	`DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
	56	`DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
	57	`DECODE_ALU_SWP, /* Atomic swap */
	58	`DECODE_ALU_BX, /* Branch and exchange */
	59	`DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
	60	`DECODE_ALU_HDATA_IMM, /* Halfword transfer - register offset */
	61	`DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
	62	`DECODE_LDRSTR, /* Single data transfer */
	63	`DECODE_LDMSTM, /* Block data transfer */
	64	`DECODE_BRANCH, /* Branch */
	65	`DECODE_LDCSTC, /* Coprocessor data transfer */
	66	`DECODE_CDP, /* Coprocessor data op */
2c523f8a	67	`DECODE_SWI: /* SWI */
b3bb2fb8	68	rpc = inpc + 8;
04d95cf5 JW	69	`DECODE_MRCMCR: /* Coprocessor register transfer */
04d95cf5 JW	70	rpc = inpc + 12;
2c523f8a	71	`DECODE_ALU: /* ALU */
b3bb2fb8	72	rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
2c523f8a	73	default: /* X everything else out */
be64a9df JW	74	rpc = 32'hxxxxxxxx;
be64a9df JW	75	endcase
96f7e6e1	76
326fd4c3 JW	77	always @(*) begin
	78	read_0 = 4'hx;
	79	read_1 = 4'hx;
	80	read_2 = 4'hx;
	81
96f7e6e1 JW	82	op0_out = 32'hxxxxxxxx;
	83	op1_out = 32'hxxxxxxxx;
	84	op2_out = 32'hxxxxxxxx;
	85	carry_out = 1'bx;
	86
0bc7ede9	87	casez (insn)
2c523f8a	88	`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3	89	begin
0bc7ede9	90	read_0 = insn[15:12]; /* Rn */
326fd4c3 JW	91	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	92	read_2 = insn[11:8]; /* Rs */
96f7e6e1 JW	93
	94	op0_out = regs0;
	95	op1_out = regs1;
	96	op2_out = regs2;
326fd4c3	97	end
2c523f8a	98	// `DECODE_ALU_MUL_LONG: /* Multiply long */
96f7e6e1	99	// begin
0bc7ede9	100	// read_0 = insn[11:8]; /* Rn */
326fd4c3 JW	101	// read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	102	// read_2 = 4'b0; /* anyus */
96f7e6e1 JW	103	//
	104	// op1_res = regs1;
	105	// end
2c523f8a	106	`DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
42c1e610	107	begin end
96f7e6e1 JW	108	`DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */
	109	begin
	110	read_0 = insn[3:0]; /* Rm */
	111
	112	op0_out = regs0;
	113	end
2c523f8a	114	`DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
96f7e6e1	115	begin
42c1e610	116	read_0 = insn[3:0]; /* Rm */
96f7e6e1 JW	117
	118	if(insn[25]) begin /* the constant case */
	119	op0_out = rotate_res;
	120	end else begin
	121	op0_out = regs0;
	122	end
	123	end
2c523f8a	124	`DECODE_ALU_SWP: /* Atomic swap */
326fd4c3	125	begin
0bc7ede9	126	read_0 = insn[19:16]; /* Rn */
326fd4c3	127	read_1 = insn[3:0]; /* Rm */
96f7e6e1 JW	128
	129	op0_out = regs0;
	130	op1_out = regs1;
326fd4c3	131	end
2c523f8a	132	`DECODE_ALU_BX: /* Branch and exchange */
96f7e6e1	133	begin
0bc7ede9	134	read_0 = insn[3:0]; /* Rn */
96f7e6e1 JW	135
	136	op0_out = regs0;
	137	end
2c523f8a	138	`DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */
326fd4c3	139	begin
0bc7ede9	140	read_0 = insn[19:16];
326fd4c3	141	read_1 = insn[3:0];
96f7e6e1 JW	142
	143	op0_out = regs0;
	144	op1_out = regs1;
326fd4c3	145	end
2c523f8a	146	`DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
326fd4c3	147	begin
0bc7ede9	148	read_0 = insn[19:16];
96f7e6e1 JW	149
	150	op0_out = regs0;
	151	op1_out = {24'b0, insn[11:8], insn[3:0]};
326fd4c3	152	end
2c523f8a JW	153	`DECODE_ALU: /* ALU */
	154	begin
	155	read_0 = insn[19:16]; /* Rn */
	156	read_1 = insn[3:0]; /* Rm */
	157	read_2 = insn[11:8]; /* Rs for shift */
96f7e6e1	158
2c523f8a JW	159	op0_out = regs0;
	160	if(insn[25]) begin /* the constant case */
	161	carry_out = incpsr[`CPSR_C];
	162	op1_out = rotate_res;
	163	end else begin
	164	carry_out = shift_cflag_out;
	165	op1_out = shift_res;
	166	end
	167	end
96f7e6e1 JW	168	`DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */
96f7e6e1 JW	169	begin
bae77231 CL	170	/* eat shit */
bae77231 CL	171	end
96f7e6e1 JW	172	`DECODE_LDRSTR: /* Single data transfer */
	173	begin
	174	read_0 = insn[19:16]; /* Rn */
	175	read_1 = insn[3:0]; /* Rm */
6d0f9d82	176	read_2 = insn[15:12];
96f7e6e1	177
42c1e610	178	op0_out = regs0;
be64a9df	179	if(insn[25]) begin
42c1e610 JW	180	op1_out = {20'b0, insn[11:0]};
42c1e610 JW	181	carry_out = incpsr[`CPSR_C];
bae77231	182	end else begin
42c1e610 JW	183	op1_out = shift_res;
42c1e610 JW	184	carry_out = shift_cflag_out;
bae77231	185	end
6d0f9d82	186	op2_out = regs2;
bae77231	187	end
96f7e6e1 JW	188	`DECODE_LDMSTM: /* Block data transfer */
	189	begin
	190	read_0 = insn[19:16];
	191
42c1e610 JW	192	op0_out = regs0;
42c1e610 JW	193	op1_out = {16'b0, insn[15:0]};
bae77231	194	end
96f7e6e1 JW	195	`DECODE_BRANCH: /* Branch */
96f7e6e1 JW	196	begin
42c1e610	197	op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231	198	end
96f7e6e1 JW	199	`DECODE_LDCSTC: /* Coprocessor data transfer */
	200	begin
	201	read_0 = insn[19:16];
	202
42c1e610 JW	203	op0_out = regs0;
42c1e610 JW	204	op1_out = {24'b0, insn[7:0]};
bae77231	205	end
96f7e6e1 JW	206	`DECODE_CDP: /* Coprocessor data op */
96f7e6e1 JW	207	begin
bae77231	208	end
96f7e6e1 JW	209	`DECODE_MRCMCR: /* Coprocessor register transfer */
	210	begin
	211	read_0 = insn[15:12];
	212
42c1e610	213	op0_out = regs0;
bae77231	214	end
96f7e6e1 JW	215	`DECODE_SWI: /* SWI */
96f7e6e1 JW	216	begin
bae77231	217	end
96f7e6e1 JW	218	default:
96f7e6e1 JW	219	$display("Undecoded instruction");
bae77231 CL	220	endcase
	221	end
	222
96f7e6e1	223
bae77231	224	always @ (posedge clk) begin
42c1e610 JW	225	op0 <= op0_out; /* Rn - always */
	226	op1 <= op1_out; /* 'operand 2' - Rm */
	227	op2 <= op2_out; /* thirdedge - Rs */
	228	carry <= carry_out;
ab7ee9fc	229	outcpsr <= incpsr;
cb0428b6	230	outspsr <= inspsr;
bae77231 CL	231	end
	232
	233	endmodule
	234
e2c5d224	235	module IREALLYHATEARMSHIFT(
bae77231 CL	236	input [31:0] insn,
	237	input [31:0] operand,
	238	input [31:0] reg_amt,
	239	input cflag_in,
fbe84cc1 JW	240	output reg [31:0] res,
fbe84cc1 JW	241	output reg cflag_out
bae77231	242	);
bae77231	243	wire [5:0] shift_amt;
f61f8d6f JW	244	reg is_arith, is_rot;
	245	wire rshift_cout;
	246	wire [31:0] rshift_res;
e2c5d224 CL	247
	248	assign shift_amt = insn[4] ? {\|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
	249	: {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231	250
96f7e6e1	251	SuckLessShifter barrel(.oper(operand),
e2c5d224 CL	252	.carryin(cflag_in),
	253	.amt(shift_amt),
	254	.is_arith(is_arith),
	255	.is_rot(is_rot),
	256	.res(rshift_res),
	257	.carryout(rshift_cout));
bae77231	258
821617bb	259	always @(*)
e2c5d224 CL	260	case (insn[6:5])
e2c5d224 CL	261	`SHIFT_LSL: begin
e5fb7d86	262	/* meaningless */
e2c5d224 CL	263	is_rot = 1'b0;
e2c5d224 CL	264	is_arith = 1'b0;
26049339	265	end
e2c5d224 CL	266	`SHIFT_LSR: begin
	267	is_rot = 1'b0;
	268	is_arith = 1'b0;
	269	end
	270	`SHIFT_ASR: begin
	271	is_rot = 1'b0;
	272	is_arith = 1'b1;
	273	end
	274	`SHIFT_ROR: begin
	275	is_rot = 1'b1;
	276	is_arith = 1'b0;
	277	end
	278	endcase
	279
821617bb	280	always @(*)
26049339	281	case (insn[6:5]) /* shift type */
e2c5d224 CL	282	`SHIFT_LSL:
e2c5d224 CL	283	{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231	284	`SHIFT_LSR: begin
e2c5d224 CL	285	res = rshift_res;
e2c5d224 CL	286	cflag_out = rshift_cout;
bae77231 CL	287	end
bae77231 CL	288	`SHIFT_ASR: begin
e2c5d224 CL	289	res = rshift_res;
e2c5d224 CL	290	cflag_out = rshift_cout;
bae77231 CL	291	end
bae77231 CL	292	`SHIFT_ROR: begin
e2c5d224	293	if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231 CL	294	res = {cflag_in, operand[31:1]};
bae77231 CL	295	cflag_out = operand[0];
e5fb7d86	296	end else begin
e2c5d224 CL	297	res = rshift_res;
e2c5d224 CL	298	cflag_out = rshift_cout;
bae77231 CL	299	end
bae77231 CL	300	end
26049339	301	endcase
bae77231	302	endmodule
e2c5d224 CL	303
	304	module SuckLessShifter(
	305	input [31:0] oper,
	306	input carryin,
	307	input [5:0] amt,
	308	input is_arith,
	309	input is_rot,
f61f8d6f JW	310	output wire [31:0] res,
f61f8d6f JW	311	output wire carryout
e2c5d224 CL	312	);
	313
	314	wire [32:0] stage1, stage2, stage3, stage4, stage5;
	315
e5fb7d86	316	wire pushbits = is_arith & oper[31];
e2c5d224 CL	317
	318	/* do a barrel shift */
	319	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
6c715b10 CL	320	assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
	321	assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
	322	assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
	323	assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
	324	assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
e2c5d224 CL	325
e2c5d224 CL	326	endmodule
a0c8a75c CL	327
	328	module SuckLessRotator(
	329	input [31:0] oper,
	330	input [3:0] amt,
f61f8d6f	331	output wire [31:0] res
a0c8a75c CL	332	);
	333
	334	wire [31:0] stage1, stage2, stage3;
	335	assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
	336	assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
	337	assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
	338	assign res = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
	339
	340	endmodule
96f7e6e1	341