[firearm.git] / Decode.v

`include "ARM_Constants.v"

module Decode(
	input clk,
	input [31:0] insn,
	input [31:0] inpc,
	input [31:0] incpsr,
	output reg [31:0] op0,
	output reg [31:0] op1,
	output reg [31:0] op2,
	output reg carry,

	output [3:0] read_0,
	output [3:0] read_1,
	output [3:0] read_2,
	input [31:0] rdata_0,
	input [31:0] rdata_1,
	input [31:0] rdata_2
	);

	wire [31:0] regs0, regs1, regs2, rpc;
	wire [31:0] op0_out, op1_out, op2_out;
	wire carry_out;

	/* shifter stuff */
	wire [31:0] shift_oper;
	wire [31:0] shift_res;
	wire shift_cflag_out;

	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */

	IREALLYHATEARMSHIFT blowme(.insn(insn),
	                           .operand(regs1),
	                           .reg_amt(regs2),
	                           .cflag_in(incpsr[`CPSR_C]),
	                           .res(shift_res),
	                           .cflag_out(shift_cflag_out));

	always @(*)
		casez (insn)
		32'b????000000??????????????1001????,	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
//		32'b????00001???????????????1001????,	/* Multiply long */
		32'b????00010?001111????000000000000,	/* MRS (Transfer PSR to register) */
		32'b????00010?101001111100000000????,	/* MSR (Transfer register to PSR) */
		32'b????00?10?1010001111????????????,	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		32'b????00010?00????????00001001????,	/* Atomic swap */
		32'b????000100101111111111110001????,	/* Branch and exchange */
		32'b????000??0??????????00001??1????,	/* Halfword transfer - register offset */
		32'b????000??1??????????00001??1????,	/* Halfword transfer - register offset */
		32'b????011????????????????????1????,	/* Undefined. I hate ARM */
		32'b????01??????????????????????????,	/* Single data transfer */
		32'b????100?????????????????????????,	/* Block data transfer */
		32'b????101?????????????????????????,	/* Branch */
		32'b????110?????????????????????????,	/* Coprocessor data transfer */
		32'b????1110???????????????????0????,	/* Coprocessor data op */
		32'b????1110???????????????????1????,	/* Coprocessor register transfer */
		32'b????1111????????????????????????:	/* SWI */
			rpc = inpc - 8;
		32'b????00??????????????????????????:	/* ALU */
			rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
		default:				/* X everything else out */
			rpc = 32'hxxxxxxxx;
		endcase

	always @(*) begin
		read_0 = 4'hx;
		read_1 = 4'hx;
		read_2 = 4'hx;
		
		casez (insn)
		32'b????000000??????????????1001????:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			read_0 = insn[15:12]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs */
		end
//		32'b????00001???????????????1001????,	/* Multiply long */
//			read_0 = insn[11:8]; /* Rn */
//			read_1 = insn[3:0];   /* Rm */
//			read_2 = 4'b0;       /* anyus */
		32'b????00010?001111????000000000000:	/* MRS (Transfer PSR to register) */
		begin end
		32'b????00010?101001111100000000????,	/* MSR (Transfer register to PSR) */
		32'b????00?10?1010001111????????????:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
			read_0 = insn[3:0];	/* Rm */
		32'b????00??????????????????????????:	/* ALU */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
			read_2 = insn[11:8];  /* Rs for shift */
		end
		32'b????00010?00????????00001001????:	/* Atomic swap */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
		end
		32'b????000100101111111111110001????:	/* Branch and exchange */
			read_0 = insn[3:0];   /* Rn */
		32'b????000??0??????????00001??1????:	/* Halfword transfer - register offset */
		begin
			read_0 = insn[19:16];
			read_1 = insn[3:0];
		end
		32'b????000??1??????????00001??1????:	/* Halfword transfer - immediate offset */
		begin
			read_0 = insn[19:16];
		end
		32'b????011????????????????????1????:	/* Undefined. I hate ARM */
		begin end
		32'b????01??????????????????????????:	/* Single data transfer */
		begin
			read_0 = insn[19:16]; /* Rn */
			read_1 = insn[3:0];   /* Rm */
		end
		32'b????100?????????????????????????:	/* Block data transfer */
			read_0 = insn[19:16];
		32'b????101?????????????????????????:	/* Branch */
		begin end
		32'b????110?????????????????????????:	/* Coprocessor data transfer */
			read_0 = insn[19:16];
		32'b????1110???????????????????0????:	/* Coprocessor data op */
		begin end
		32'b????1110???????????????????1????:	/* Coprocessor register transfer */
			read_0 = insn[15:12];
		32'b????1111????????????????????????:	/* SWI */
		begin end
		default:
			$display("Undecoded instruction");
		endcase
	end
	
	always @(*) begin
		op0_out = 32'hxxxxxxxx;
		op1_out = 32'hxxxxxxxx;
		op2_out = 32'hxxxxxxxx;
		carry_out = 1'bx;
		casez (insn)
		32'b????000000??????????????1001????: begin /* Multiply */
			op0_out = regs0;
			op1_out = regs1;
			op2_out = regs2;
		end
//		32'b????00001???????????????1001????: begin /* Multiply long */
//			op1_res = regs1;
//		end
		32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
		end
        	32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
        		op0_out = regs0;
        	end
                32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
                	if(insn[25]) begin     /* the constant case */
				op0_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
			end else begin
				op0_out = regs0;
			end
                end
		32'b????00??????????????????????????: begin /* ALU */
			op0_out = regs0;
			if(insn[25]) begin     /* the constant case */
				carry_out = incpsr[`CPSR_C];
				op1_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
			end else begin
				carry_out = shift_cflag_out;
				op1_out = shift_res;
			end
		end
		32'b????00010?00????????00001001????: begin /* Atomic swap */
			op0_out = regs0;
			op1_out = regs1;
		end
		32'b????000100101111111111110001????: begin /* Branch and exchange */
			op0_out = regs0;
		end
		32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
			op0_out = regs0;
			op1_out = regs1;
		end
		32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
			op0_out = regs0;
			op1_out = {24'b0, insn[11:8], insn[3:0]};
		end
		32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
			/* eat shit */
		end
		32'b????01??????????????????????????: begin /* Single data transfer */
			op0_out = regs0;
			if(insn[25]) begin
				op1_out = {20'b0, insn[11:0]};
				carry_out = incpsr[`CPSR_C];
			end else begin
				op1_out = shift_res;
				carry_out = shift_cflag_out;
			end
		end
		32'b????100?????????????????????????: begin /* Block data transfer */
			op0_out = regs0;
			op1_out = {16'b0, insn[15:0]};
		end
		32'b????101?????????????????????????: begin /* Branch */
			op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
		end
		32'b????110?????????????????????????: begin /* Coprocessor data transfer */
			op0_out = regs0;
			op1_out = {24'b0, insn[7:0]};
		end
		32'b????1110???????????????????0????: begin /* Coprocessor data op */
		end
		32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
			op0_out = regs0;
		end
		32'b????1111????????????????????????: begin /* SWI */
		end
		default: begin end
		endcase
	end

	always @ (posedge clk) begin
		op0 <= op0_out;   /* Rn - always */
		op1 <= op1_out; /* 'operand 2' - Rm */
		op2 <= op2_out;   /* thirdedge - Rs */
		carry <= carry_out;
	end

endmodule

module IREALLYHATEARMSHIFT(
	input [31:0] insn,
	input [31:0] operand,
	input [31:0] reg_amt,
	input cflag_in,
	output [31:0] res,
	output cflag_out
);
	wire [5:0] shift_amt;
	wire rshift_cout, is_arith, is_rot;
	wire [31:0] rshift_res;

	assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
	                           : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */

	SuckLessShifter biteme(.oper(operand),
	                       .carryin(cflag_in),
	                       .amt(shift_amt),
	                       .is_arith(is_arith),
	                       .is_rot(is_rot),
	                       .res(rshift_res),
	                       .carryout(rshift_cout));

	always @(*)
		case (insn[6:5])
		`SHIFT_LSL: begin
			/* meaningless */
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_LSR: begin
			is_rot = 1'b0;
			is_arith = 1'b0;
		end
		`SHIFT_ASR: begin
			is_rot = 1'b0;
			is_arith = 1'b1;
		end
		`SHIFT_ROR: begin
			is_rot = 1'b1;
			is_arith = 1'b0;
		end
		endcase

	always @(*)
		case (insn[6:5]) /* shift type */
		`SHIFT_LSL:
			{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
		`SHIFT_LSR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ASR: begin
			res = rshift_res;
			cflag_out = rshift_cout;
		end
		`SHIFT_ROR: begin
			if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
				res = {cflag_in, operand[31:1]};
				cflag_out = operand[0];
			end else begin
				res = rshift_res;
				cflag_out = rshift_cout;
			end
		end
		endcase
endmodule

module SuckLessShifter(
	input [31:0] oper,
	input carryin,
	input [5:0] amt,
	input is_arith,
	input is_rot,
	output [31:0] res,
	output carryout
);

	wire [32:0] stage1, stage2, stage3, stage4, stage5;

	wire pushbits = is_arith & oper[31];

	/* do a barrel shift */
	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
	assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[15]} : stage1;
	assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[7]} : stage2;
	assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[3]} : stage3;
	assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[1]} : stage4;
	assign {res, carryout} = amt[0] ? {is_rot ? stage5[0] : pushbits, stage5[31:1], stage5[0]} : stage5;

endmodule
Commit	Line	Data
26049339 CL	1	`include "ARM_Constants.v"
26049339 CL	2
bae77231 CL	3	module Decode(
bae77231 CL	4	input clk,
be64a9df	5	input [31:0] insn,
bae77231	6	input [31:0] inpc,
821617bb	7	input [31:0] incpsr,
bae77231 CL	8	output reg [31:0] op0,
	9	output reg [31:0] op1,
	10	output reg [31:0] op2,
42c1e610	11	output reg carry,
bae77231	12
821617bb JW	13	output [3:0] read_0,
	14	output [3:0] read_1,
	15	output [3:0] read_2,
	16	input [31:0] rdata_0,
	17	input [31:0] rdata_1,
	18	input [31:0] rdata_2
bae77231 CL	19	);
	20
	21	wire [31:0] regs0, regs1, regs2, rpc;
42c1e610 JW	22	wire [31:0] op0_out, op1_out, op2_out;
42c1e610 JW	23	wire carry_out;
bae77231 CL	24
	25	/* shifter stuff */
	26	wire [31:0] shift_oper;
	27	wire [31:0] shift_res;
	28	wire shift_cflag_out;
	29
821617bb JW	30	assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
	31	assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
	32	assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
bae77231	33
e2c5d224 CL	34	IREALLYHATEARMSHIFT blowme(.insn(insn),
	35	.operand(regs1),
	36	.reg_amt(regs2),
	37	.cflag_in(incpsr[`CPSR_C]),
	38	.res(shift_res),
	39	.cflag_out(shift_cflag_out));
	40
be64a9df JW	41	always @(*)
	42	casez (insn)
	43	32'b????000000??????????????1001????, /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	44	// 32'b????00001???????????????1001????, /* Multiply long */
	45	32'b????00010?001111????000000000000, /* MRS (Transfer PSR to register) */
	46	32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
	47	32'b????00?10?1010001111????????????, /* MSR (Transfer register or immediate to PSR, flag bits only) */
	48	32'b????00010?00????????00001001????, /* Atomic swap */
0bc7ede9	49	32'b????000100101111111111110001????, /* Branch and exchange */
be64a9df JW	50	32'b????000??0??????????00001??1????, /* Halfword transfer - register offset */
	51	32'b????000??1??????????00001??1????, /* Halfword transfer - register offset */
	52	32'b????011????????????????????1????, /* Undefined. I hate ARM */
	53	32'b????01??????????????????????????, /* Single data transfer */
	54	32'b????100?????????????????????????, /* Block data transfer */
	55	32'b????101?????????????????????????, /* Branch */
	56	32'b????110?????????????????????????, /* Coprocessor data transfer */
	57	32'b????1110???????????????????0????, /* Coprocessor data op */
	58	32'b????1110???????????????????1????, /* Coprocessor register transfer */
	59	32'b????1111????????????????????????: /* SWI */
	60	rpc = inpc - 8;
	61	32'b????00??????????????????????????: /* ALU */
	62	rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
	63	default: /* X everything else out */
	64	rpc = 32'hxxxxxxxx;
	65	endcase
bae77231	66
326fd4c3 JW	67	always @(*) begin
	68	read_0 = 4'hx;
	69	read_1 = 4'hx;
	70	read_2 = 4'hx;
	71
0bc7ede9 JW	72	casez (insn)
0bc7ede9 JW	73	32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
326fd4c3	74	begin
0bc7ede9	75	read_0 = insn[15:12]; /* Rn */
326fd4c3 JW	76	read_1 = insn[3:0]; /* Rm */
	77	read_2 = insn[11:8]; /* Rs */
	78	end
0bc7ede9 JW	79	// 32'b????00001???????????????1001????, /* Multiply long */
0bc7ede9 JW	80	// read_0 = insn[11:8]; /* Rn */
326fd4c3 JW	81	// read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	82	// read_2 = 4'b0; /* anyus */
42c1e610 JW	83	32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */
42c1e610 JW	84	begin end
0bc7ede9 JW	85	32'b????00010?101001111100000000????, /* MSR (Transfer register to PSR) */
0bc7ede9 JW	86	32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */
42c1e610	87	read_0 = insn[3:0]; /* Rm */
0bc7ede9	88	32'b????00??????????????????????????: /* ALU */
326fd4c3	89	begin
0bc7ede9	90	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	91	read_1 = insn[3:0]; /* Rm */
	92	read_2 = insn[11:8]; /* Rs for shift */
	93	end
0bc7ede9	94	32'b????00010?00????????00001001????: /* Atomic swap */
326fd4c3	95	begin
0bc7ede9	96	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	97	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	98	end
0bc7ede9 JW	99	32'b????000100101111111111110001????: /* Branch and exchange */
	100	read_0 = insn[3:0]; /* Rn */
	101	32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */
326fd4c3	102	begin
0bc7ede9	103	read_0 = insn[19:16];
326fd4c3 JW	104	read_1 = insn[3:0];
	105	end
	106	32'b????000??1??????????00001??1????: /* Halfword transfer - immediate offset */
	107	begin
0bc7ede9	108	read_0 = insn[19:16];
326fd4c3	109	end
0bc7ede9	110	32'b????011????????????????????1????: /* Undefined. I hate ARM */
326fd4c3	111	begin end
0bc7ede9	112	32'b????01??????????????????????????: /* Single data transfer */
326fd4c3	113	begin
0bc7ede9	114	read_0 = insn[19:16]; /* Rn */
326fd4c3 JW	115	read_1 = insn[3:0]; /* Rm */
326fd4c3 JW	116	end
0bc7ede9 JW	117	32'b????100?????????????????????????: /* Block data transfer */
	118	read_0 = insn[19:16];
	119	32'b????101?????????????????????????: /* Branch */
326fd4c3	120	begin end
0bc7ede9 JW	121	32'b????110?????????????????????????: /* Coprocessor data transfer */
0bc7ede9 JW	122	read_0 = insn[19:16];
42c1e610 JW	123	32'b????1110???????????????????0????: /* Coprocessor data op */
	124	begin end
	125	32'b????1110???????????????????1????: /* Coprocessor register transfer */
	126	read_0 = insn[15:12];
0bc7ede9	127	32'b????1111????????????????????????: /* SWI */
326fd4c3	128	begin end
b215c5ff	129	default:
326fd4c3	130	$display("Undecoded instruction");
b215c5ff	131	endcase
326fd4c3	132	end
b215c5ff	133
326fd4c3	134	always @(*) begin
42c1e610 JW	135	op0_out = 32'hxxxxxxxx;
	136	op1_out = 32'hxxxxxxxx;
	137	op2_out = 32'hxxxxxxxx;
	138	carry_out = 1'bx;
be64a9df	139	casez (insn)
bae77231	140	32'b????000000??????????????1001????: begin /* Multiply */
42c1e610 JW	141	op0_out = regs0;
	142	op1_out = regs1;
	143	op2_out = regs2;
bae77231	144	end
b215c5ff JW	145	// 32'b????00001???????????????1001????: begin /* Multiply long */
	146	// op1_res = regs1;
	147	// end
bae77231	148	32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
bae77231 CL	149	end
bae77231 CL	150	32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
42c1e610	151	op0_out = regs0;
bae77231	152	end
42c1e610 JW	153	32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
	154	if(insn[25]) begin /* the constant case */
	155	op0_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) \| ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
	156	end else begin
	157	op0_out = regs0;
	158	end
bae77231 CL	159	end
bae77231 CL	160	32'b????00??????????????????????????: begin /* ALU */
42c1e610	161	op0_out = regs0;
be64a9df	162	if(insn[25]) begin /* the constant case */
42c1e610 JW	163	carry_out = incpsr[`CPSR_C];
42c1e610 JW	164	op1_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) \| ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
bae77231	165	end else begin
42c1e610 JW	166	carry_out = shift_cflag_out;
42c1e610 JW	167	op1_out = shift_res;
bae77231 CL	168	end
	169	end
	170	32'b????00010?00????????00001001????: begin /* Atomic swap */
42c1e610 JW	171	op0_out = regs0;
42c1e610 JW	172	op1_out = regs1;
bae77231 CL	173	end
bae77231 CL	174	32'b????000100101111111111110001????: begin /* Branch and exchange */
42c1e610	175	op0_out = regs0;
bae77231 CL	176	end
bae77231 CL	177	32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
42c1e610 JW	178	op0_out = regs0;
42c1e610 JW	179	op1_out = regs1;
bae77231 CL	180	end
bae77231 CL	181	32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
42c1e610 JW	182	op0_out = regs0;
42c1e610 JW	183	op1_out = {24'b0, insn[11:8], insn[3:0]};
bae77231 CL	184	end
	185	32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
	186	/* eat shit */
	187	end
	188	32'b????01??????????????????????????: begin /* Single data transfer */
42c1e610	189	op0_out = regs0;
be64a9df	190	if(insn[25]) begin
42c1e610 JW	191	op1_out = {20'b0, insn[11:0]};
42c1e610 JW	192	carry_out = incpsr[`CPSR_C];
bae77231	193	end else begin
42c1e610 JW	194	op1_out = shift_res;
42c1e610 JW	195	carry_out = shift_cflag_out;
bae77231 CL	196	end
	197	end
	198	32'b????100?????????????????????????: begin /* Block data transfer */
42c1e610 JW	199	op0_out = regs0;
42c1e610 JW	200	op1_out = {16'b0, insn[15:0]};
bae77231 CL	201	end
bae77231 CL	202	32'b????101?????????????????????????: begin /* Branch */
42c1e610	203	op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
bae77231 CL	204	end
bae77231 CL	205	32'b????110?????????????????????????: begin /* Coprocessor data transfer */
42c1e610 JW	206	op0_out = regs0;
42c1e610 JW	207	op1_out = {24'b0, insn[7:0]};
bae77231 CL	208	end
bae77231 CL	209	32'b????1110???????????????????0????: begin /* Coprocessor data op */
bae77231 CL	210	end
bae77231 CL	211	32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
42c1e610	212	op0_out = regs0;
bae77231 CL	213	end
bae77231 CL	214	32'b????1111????????????????????????: begin /* SWI */
bae77231	215	end
26049339	216	default: begin end
bae77231 CL	217	endcase
	218	end
	219
	220	always @ (posedge clk) begin
42c1e610 JW	221	op0 <= op0_out; /* Rn - always */
	222	op1 <= op1_out; /* 'operand 2' - Rm */
	223	op2 <= op2_out; /* thirdedge - Rs */
	224	carry <= carry_out;
bae77231 CL	225	end
	226
	227	endmodule
	228
e2c5d224	229	module IREALLYHATEARMSHIFT(
bae77231 CL	230	input [31:0] insn,
	231	input [31:0] operand,
	232	input [31:0] reg_amt,
	233	input cflag_in,
	234	output [31:0] res,
	235	output cflag_out
	236	);
bae77231	237	wire [5:0] shift_amt;
e2c5d224 CL	238	wire rshift_cout, is_arith, is_rot;
	239	wire [31:0] rshift_res;
	240
	241	assign shift_amt = insn[4] ? {\|reg_amt[7:5], reg_amt[4:0]} /* reg-specified shift */
	242	: {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
bae77231	243
e2c5d224 CL	244	SuckLessShifter biteme(.oper(operand),
	245	.carryin(cflag_in),
	246	.amt(shift_amt),
	247	.is_arith(is_arith),
	248	.is_rot(is_rot),
	249	.res(rshift_res),
	250	.carryout(rshift_cout));
bae77231	251
821617bb	252	always @(*)
e2c5d224 CL	253	case (insn[6:5])
e2c5d224 CL	254	`SHIFT_LSL: begin
e5fb7d86	255	/* meaningless */
e2c5d224 CL	256	is_rot = 1'b0;
e2c5d224 CL	257	is_arith = 1'b0;
26049339	258	end
e2c5d224 CL	259	`SHIFT_LSR: begin
	260	is_rot = 1'b0;
	261	is_arith = 1'b0;
	262	end
	263	`SHIFT_ASR: begin
	264	is_rot = 1'b0;
	265	is_arith = 1'b1;
	266	end
	267	`SHIFT_ROR: begin
	268	is_rot = 1'b1;
	269	is_arith = 1'b0;
	270	end
	271	endcase
	272
821617bb	273	always @(*)
26049339	274	case (insn[6:5]) /* shift type */
e2c5d224 CL	275	`SHIFT_LSL:
e2c5d224 CL	276	{cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
bae77231	277	`SHIFT_LSR: begin
e2c5d224 CL	278	res = rshift_res;
e2c5d224 CL	279	cflag_out = rshift_cout;
bae77231 CL	280	end
bae77231 CL	281	`SHIFT_ASR: begin
e2c5d224 CL	282	res = rshift_res;
e2c5d224 CL	283	cflag_out = rshift_cout;
bae77231 CL	284	end
bae77231 CL	285	`SHIFT_ROR: begin
e2c5d224	286	if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
bae77231 CL	287	res = {cflag_in, operand[31:1]};
bae77231 CL	288	cflag_out = operand[0];
e5fb7d86	289	end else begin
e2c5d224 CL	290	res = rshift_res;
e2c5d224 CL	291	cflag_out = rshift_cout;
bae77231 CL	292	end
bae77231 CL	293	end
26049339	294	endcase
bae77231	295	endmodule
e2c5d224 CL	296
	297	module SuckLessShifter(
	298	input [31:0] oper,
	299	input carryin,
	300	input [5:0] amt,
	301	input is_arith,
	302	input is_rot,
	303	output [31:0] res,
	304	output carryout
	305	);
	306
	307	wire [32:0] stage1, stage2, stage3, stage4, stage5;
	308
e5fb7d86	309	wire pushbits = is_arith & oper[31];
e2c5d224 CL	310
	311	/* do a barrel shift */
	312	assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
5ad8b7c8 CL	313	assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[15]} : stage1;
	314	assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[7]} : stage2;
	315	assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[3]} : stage3;
	316	assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[1]} : stage4;
	317	assign {res, carryout} = amt[0] ? {is_rot ? stage5[0] : pushbits, stage5[31:1], stage5[0]} : stage5;
e2c5d224 CL	318
e2c5d224 CL	319	endmodule