Decode.v

   1 `include "ARM_Constants.v"
   2
   3 module Decode(
   4         input clk,
   5         input [31:0] insn,
   6         input [31:0] inpc,
   7         input [31:0] incpsr,
   8         output reg [31:0] op0,
   9         output reg [31:0] op1,
  10         output reg [31:0] op2,
  11         output reg carry,
  12
  13         output [3:0] read_0,
  14         output [3:0] read_1,
  15         output [3:0] read_2,
  16         input [31:0] rdata_0,
  17         input [31:0] rdata_1,
  18         input [31:0] rdata_2
  19         );
  20
  21         wire [31:0] regs0, regs1, regs2, rpc;
  22         wire [31:0] op0_out, op1_out, op2_out;
  23         wire carry_out;
  24
  25         /* shifter stuff */
  26         wire [31:0] shift_oper;
  27         wire [31:0] shift_res;
  28         wire shift_cflag_out;
  29
  30         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
  31         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
  32         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
  33
  34         IREALLYHATEARMSHIFT blowme(.insn(insn),
  35                                    .operand(regs1),
  36                                    .reg_amt(regs2),
  37                                    .cflag_in(incpsr[`CPSR_C]),
  38                                    .res(shift_res),
  39                                    .cflag_out(shift_cflag_out));
  40
  41         always @(*)
  42                 casez (insn)
  43                 32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  44 //              32'b????00001???????????????1001????,   /* Multiply long */
  45                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
  46                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
  47                 32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
  48                 32'b????00010?00????????00001001????,   /* Atomic swap */
  49                 32'b????000100101111111111110001????,   /* Branch and exchange */
  50                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
  51                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
  52                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
  53                 32'b????01??????????????????????????,   /* Single data transfer */
  54                 32'b????100?????????????????????????,   /* Block data transfer */
  55                 32'b????101?????????????????????????,   /* Branch */
  56                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
  57                 32'b????1110???????????????????0????,   /* Coprocessor data op */
  58                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
  59                 32'b????1111????????????????????????:   /* SWI */
  60                         rpc = inpc - 8;
  61                 32'b????00??????????????????????????:   /* ALU */
  62                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
  63                 default:                                /* X everything else out */
  64                         rpc = 32'hxxxxxxxx;
  65                 endcase
  66
  67         always @(*) begin
  68                 read_0 = 4'hx;
  69                 read_1 = 4'hx;
  70                 read_2 = 4'hx;
  71
  72                 casez (insn)
  73                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  74                 begin
  75                         read_0 = insn[15:12]; /* Rn */
  76                         read_1 = insn[3:0];   /* Rm */
  77                         read_2 = insn[11:8];  /* Rs */
  78                 end
  79 //              32'b????00001???????????????1001????,   /* Multiply long */
  80 //                      read_0 = insn[11:8]; /* Rn */
  81 //                      read_1 = insn[3:0];   /* Rm */
  82 //                      read_2 = 4'b0;       /* anyus */
  83                 32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
  84                 begin end
  85                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
  86                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
  87                         read_0 = insn[3:0];     /* Rm */
  88                 32'b????00??????????????????????????:   /* ALU */
  89                 begin
  90                         read_0 = insn[19:16]; /* Rn */
  91                         read_1 = insn[3:0];   /* Rm */
  92                         read_2 = insn[11:8];  /* Rs for shift */
  93                 end
  94                 32'b????00010?00????????00001001????:   /* Atomic swap */
  95                 begin
  96                         read_0 = insn[19:16]; /* Rn */
  97                         read_1 = insn[3:0];   /* Rm */
  98                 end
  99                 32'b????000100101111111111110001????:   /* Branch and exchange */
 100                         read_0 = insn[3:0];   /* Rn */
 101                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
 102                 begin
 103                         read_0 = insn[19:16];
 104                         read_1 = insn[3:0];
 105                 end
 106                 32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
 107                 begin
 108                         read_0 = insn[19:16];
 109                 end
 110                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
 111                 begin end
 112                 32'b????01??????????????????????????:   /* Single data transfer */
 113                 begin
 114                         read_0 = insn[19:16]; /* Rn */
 115                         read_1 = insn[3:0];   /* Rm */
 116                 end
 117                 32'b????100?????????????????????????:   /* Block data transfer */
 118                         read_0 = insn[19:16];
 119                 32'b????101?????????????????????????:   /* Branch */
 120                 begin end
 121                 32'b????110?????????????????????????:   /* Coprocessor data transfer */
 122                         read_0 = insn[19:16];
 123                 32'b????1110???????????????????0????:   /* Coprocessor data op */
 124                 begin end
 125                 32'b????1110???????????????????1????:   /* Coprocessor register transfer */
 126                         read_0 = insn[15:12];
 127                 32'b????1111????????????????????????:   /* SWI */
 128                 begin end
 129                 default:
 130                         $display("Undecoded instruction");
 131                 endcase
 132         end
 133
 134         always @(*) begin
 135                 op0_out = 32'hxxxxxxxx;
 136                 op1_out = 32'hxxxxxxxx;
 137                 op2_out = 32'hxxxxxxxx;
 138                 carry_out = 1'bx;
 139                 casez (insn)
 140                 32'b????000000??????????????1001????: begin /* Multiply */
 141                         op0_out = regs0;
 142                         op1_out = regs1;
 143                         op2_out = regs2;
 144                 end
 145 //              32'b????00001???????????????1001????: begin /* Multiply long */
 146 //                      op1_res = regs1;
 147 //              end
 148                 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
 149                 end
 150                 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
 151                         op0_out = regs0;
 152                 end
 153                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
 154                         if(insn[25]) begin     /* the constant case */
 155                                 op0_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
 156                         end else begin
 157                                 op0_out = regs0;
 158                         end
 159                 end
 160                 32'b????00??????????????????????????: begin /* ALU */
 161                         op0_out = regs0;
 162                         if(insn[25]) begin     /* the constant case */
 163                                 carry_out = incpsr[`CPSR_C];
 164                                 op1_out = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
 165                         end else begin
 166                                 carry_out = shift_cflag_out;
 167                                 op1_out = shift_res;
 168                         end
 169                 end
 170                 32'b????00010?00????????00001001????: begin /* Atomic swap */
 171                         op0_out = regs0;
 172                         op1_out = regs1;
 173                 end
 174                 32'b????000100101111111111110001????: begin /* Branch and exchange */
 175                         op0_out = regs0;
 176                 end
 177                 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
 178                         op0_out = regs0;
 179                         op1_out = regs1;
 180                 end
 181                 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
 182                         op0_out = regs0;
 183                         op1_out = {24'b0, insn[11:8], insn[3:0]};
 184                 end
 185                 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
 186                         /* eat shit */
 187                 end
 188                 32'b????01??????????????????????????: begin /* Single data transfer */
 189                         op0_out = regs0;
 190                         if(insn[25]) begin
 191                                 op1_out = {20'b0, insn[11:0]};
 192                                 carry_out = incpsr[`CPSR_C];
 193                         end else begin
 194                                 op1_out = shift_res;
 195                                 carry_out = shift_cflag_out;
 196                         end
 197                 end
 198                 32'b????100?????????????????????????: begin /* Block data transfer */
 199                         op0_out = regs0;
 200                         op1_out = {16'b0, insn[15:0]};
 201                 end
 202                 32'b????101?????????????????????????: begin /* Branch */
 203                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
 204                 end
 205                 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
 206                         op0_out = regs0;
 207                         op1_out = {24'b0, insn[7:0]};
 208                 end
 209                 32'b????1110???????????????????0????: begin /* Coprocessor data op */
 210                 end
 211                 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
 212                         op0_out = regs0;
 213                 end
 214                 32'b????1111????????????????????????: begin /* SWI */
 215                 end
 216                 default: begin end
 217                 endcase
 218         end
 219
 220         always @ (posedge clk) begin
 221                 op0 <= op0_out;   /* Rn - always */
 222                 op1 <= op1_out; /* 'operand 2' - Rm */
 223                 op2 <= op2_out;   /* thirdedge - Rs */
 224                 carry <= carry_out;
 225         end
 226
 227 endmodule
 228
 229 module IREALLYHATEARMSHIFT(
 230         input [31:0] insn,
 231         input [31:0] operand,
 232         input [31:0] reg_amt,
 233         input cflag_in,
 234         output [31:0] res,
 235         output cflag_out
 236 );
 237         wire [5:0] shift_amt;
 238         wire rshift_cout, is_arith, is_rot;
 239         wire [31:0] rshift_res;
 240
 241         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
 242                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
 243
 244         SuckLessShifter biteme(.oper(operand),
 245                                .carryin(cflag_in),
 246                                .amt(shift_amt),
 247                                .is_arith(is_arith),
 248                                .is_rot(is_rot),
 249                                .res(rshift_res),
 250                                .carryout(rshift_cout));
 251
 252         always @(*)
 253                 case (insn[6:5])
 254                 `SHIFT_LSL: begin
 255                         /* meaningless */
 256                         is_rot = 1'b0;
 257                         is_arith = 1'b0;
 258                 end
 259                 `SHIFT_LSR: begin
 260                         is_rot = 1'b0;
 261                         is_arith = 1'b0;
 262                 end
 263                 `SHIFT_ASR: begin
 264                         is_rot = 1'b0;
 265                         is_arith = 1'b1;
 266                 end
 267                 `SHIFT_ROR: begin
 268                         is_rot = 1'b1;
 269                         is_arith = 1'b0;
 270                 end
 271                 endcase
 272
 273         always @(*)
 274                 case (insn[6:5]) /* shift type */
 275                 `SHIFT_LSL:
 276                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
 277                 `SHIFT_LSR: begin
 278                         res = rshift_res;
 279                         cflag_out = rshift_cout;
 280                 end
 281                 `SHIFT_ASR: begin
 282                         res = rshift_res;
 283                         cflag_out = rshift_cout;
 284                 end
 285                 `SHIFT_ROR: begin
 286                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
 287                                 res = {cflag_in, operand[31:1]};
 288                                 cflag_out = operand[0];
 289                         end else begin
 290                                 res = rshift_res;
 291                                 cflag_out = rshift_cout;
 292                         end
 293                 end
 294                 endcase
 295 endmodule
 296
 297 module SuckLessShifter(
 298         input [31:0] oper,
 299         input carryin,
 300         input [5:0] amt,
 301         input is_arith,
 302         input is_rot,
 303         output [31:0] res,
 304         output carryout
 305 );
 306
 307         wire [32:0] stage1, stage2, stage3, stage4, stage5;
 308
 309         wire pushbits = is_arith & oper[31];
 310
 311         /* do a barrel shift */
 312         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
 313         assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[15]} : stage1;
 314         assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[7]} : stage2;
 315         assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[3]} : stage3;
 316         assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[1]} : stage4;
 317         assign {res, carryout} = amt[0] ? {is_rot ? stage5[0] : pushbits, stage5[31:1], stage5[0]} : stage5;
 318
 319 endmodule