[firearm.git] / Execute.v

module Execute(
	input clk,
	input Nrst,	/* XXX not used yet */
	
	input stall,
	input flush,
	
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] cpsr,
	input [31:0] spsr,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input carry,
	
	output reg outstall = 0,
	output reg outbubble = 1,
	output reg [31:0] outcpsr = 0,
	output reg [31:0] outspsr = 0,
	output reg outcpsrup = 0,
	output reg write_reg = 1'bx,
	output reg [3:0] write_num = 4'bxxxx,
	output reg [31:0] write_data = 32'hxxxxxxxx,
	output reg [31:0] jmppc,
	output reg jmp,
	output reg [31:0] outpc,
	output reg [31:0] outinsn,
	output reg [31:0] outop0, outop1, outop2
	);
	
	reg mult_start;
	reg [31:0] mult_acc0, mult_in0, mult_in1;
	wire mult_done;
	wire [31:0] mult_result;
	
	reg [31:0] alu_in0, alu_in1;
	reg [3:0] alu_op;
	reg alu_setflags;
	wire [31:0] alu_result, alu_outcpsr;
	wire alu_setres;
	
	reg next_outbubble;
	reg [31:0] next_outcpsr, next_outspsr;
	reg next_outcpsrup;
	reg next_write_reg;
	reg [3:0] next_write_num;

	reg [31:0] next_write_data;

	Multiplier multiplier(
		.clk(clk), .Nrst(Nrst),
		.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
		.in1(mult_in1), .done(mult_done), .result(mult_result));
	
	ALU alu(
		.clk(clk), .Nrst(Nrst),
		.in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
		.setflags(alu_setflags), .shifter_carry(carry),
		.result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));

	always @(posedge clk)
	begin
		if (!stall)
		begin
			outbubble <= next_outbubble;
			outcpsr <= next_outcpsr;
			outspsr <= next_outspsr;
			outcpsrup <= next_outcpsrup;
			write_reg <= next_write_reg;
			write_num <= next_write_num;
			write_data <= next_write_data;
			outpc <= pc;
			outinsn <= insn;
			outop0 <= op0;
			outop1 <= op1;
			outop2 <= op2;
		end
	end
	
	reg delayedflush = 0;
	always @(posedge clk)
		if (flush && outstall /* halp! I can't do it now, maybe later? */)
			delayedflush <= 1;
		else if (!outstall /* anything has been handled this time around */)
			delayedflush <= 0;

	reg prevstall = 0;
	always @(posedge clk)
		prevstall <= outstall;

	always @(*)
	begin
		outstall = stall;
		next_outbubble = inbubble | flush | delayedflush;
		next_outcpsr = cpsr;
		next_outspsr = spsr;
		next_outcpsrup = 0;
		next_write_reg = 0;
		next_write_num = 4'hx;
		next_write_data = 32'hxxxxxxxx;

		mult_start = 0;
		mult_acc0 = 32'hxxxxxxxx;
		mult_in0 = 32'hxxxxxxxx;
		mult_in1 = 32'hxxxxxxxx;

		alu_in0 = 32'hxxxxxxxx;
		alu_in1 = 32'hxxxxxxxx;
		alu_op = 4'hx;	/* hax! */
		alu_setflags = 1'bx;

		jmp = 1'b0;
		jmppc = 32'h00000000;

		casez (insn)
		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			if (!prevstall && !inbubble)
			begin
				mult_start = 1;
				mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
				mult_in0 = op1 /* Rm */;
				mult_in1 = op2 /* Rs */;
				$display("New MUL instruction");
			end
			outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
			next_outbubble = next_outbubble | !mult_done | !prevstall;
			next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
			next_outcpsrup = insn[20] /* S */;
			next_write_reg = 1;
			next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
			next_write_data = mult_result;
		end
//		`DECODE_ALU_MUL_LONG,	/* Multiply long */
		`DECODE_ALU_MRS:	/* MRS (Transfer PSR to register) */
		begin
			next_write_reg = 1;
			next_write_num = insn[15:12];
			if (insn[22] /* Ps */)
				next_write_data = spsr;
			else
				next_write_data = cpsr;
			next_outcpsrup = 1;
		end
		`DECODE_ALU_MSR,	/* MSR (Transfer register to PSR) */
		`DECODE_ALU_MSR_FLAGS:	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		begin
			if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0))	/* flags only */
			begin
				if (insn[22] /* Ps */)
					next_outspsr = {op0[31:29], spsr[28:0]};
				else
					next_outcpsr = {op0[31:29], cpsr[28:0]};
			end else begin
				if (insn[22] /* Ps */)
					next_outspsr = op0;
				else
					next_outcpsr = op0;
			end
			next_outcpsrup = 1;
		end
		`DECODE_ALU_SWP,	/* Atomic swap */
		`DECODE_ALU_BX,		/* Branch */
		`DECODE_ALU_HDATA_REG,	/* Halfword transfer - register offset */
		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
		begin end
		`DECODE_ALU:		/* ALU */
		begin
			alu_in0 = op0;
			alu_in1 = op1;
			alu_op = insn[24:21];
			alu_setflags = insn[20] /* S */;
			
			if (alu_setres) begin
				next_write_reg = 1;
				next_write_num = insn[15:12] /* Rd */;
				next_write_data = alu_result;
			end
			
			next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
			next_outcpsrup = insn[20] /* S */;
		end
		`DECODE_LDRSTR_UNDEFINED,	/* Undefined. I hate ARM */
		`DECODE_LDRSTR,		/* Single data transfer */
		`DECODE_LDMSTM:		/* Block data transfer */
		begin end
		`DECODE_BRANCH:
		begin
			if(!inbubble && !flush && !delayedflush && !outstall /* Let someone else take precedence. */) begin
				jmppc = pc + op0 + 32'h8;
				if(insn[24]) begin
					next_write_reg = 1;
					next_write_num = 4'hE; /* link register */
					next_write_data = pc + 32'h4;
				end
				jmp = 1'b1;
			end
		end                     /* Branch */
		`DECODE_LDCSTC,		/* Coprocessor data transfer */
		`DECODE_CDP,		/* Coprocessor data op */
		`DECODE_MRCMCR,		/* Coprocessor register transfer */
		`DECODE_SWI:		/* SWI */
		begin end
		default:		/* X everything else out */
		begin end
		endcase
	end
endmodule

module Multiplier(
	input clk,
	input Nrst,	/* XXX not used yet */
	
	input start,
	input [31:0] acc0,
	input [31:0] in0,
	input [31:0] in1,
	
	output reg done = 0,
	output reg [31:0] result);
	
	reg [31:0] bitfield;
	reg [31:0] multiplicand;
	reg [31:0] acc;
	
	always @(posedge clk)
	begin
		if (start) begin
			bitfield <= in0;
			multiplicand <= in1;
			acc <= acc0;
			done <= 0;
		end else begin
			bitfield <= {2'b00, bitfield[31:2]};
			multiplicand <= {multiplicand[29:0], 2'b00};
			acc <= acc +
				(bitfield[0] ? multiplicand : 0) +
				(bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
			if (bitfield == 0) begin
				result <= acc;
				done <= 1;
			end
		end
	end
endmodule

module ALU(
	input clk,
	input Nrst,	/* XXX not used yet */

	input [31:0] in0,
	input [31:0] in1,
	input [31:0] cpsr,
	input [3:0] op,
	input setflags,
	input shifter_carry,

	output reg [31:0] result,
	output reg [31:0] cpsr_out,
	output reg setres
);
	reg [31:0] res;
	reg flag_n, flag_z, flag_c, flag_v;
	wire [32:0] sum, diff, rdiff;
	wire sum_v, diff_v, rdiff_v;

	assign sum = {1'b0, in0} + {1'b0, in1};
	assign diff = {1'b0, in0} - {1'b0, in1};
	assign rdiff = {1'b0, in1} - {1'b0, in0};
	assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
	assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
	assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);

	always @(*) begin
		res = 32'hxxxxxxxx;
		setres = 1'bx;
		flag_c = cpsr[`CPSR_C];
		flag_v = cpsr[`CPSR_V];
		case(op)
		`ALU_AND: begin
			result = in0 & in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_EOR: begin
			result = in0 ^ in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_SUB: begin
			{flag_c, result} = diff;
			flag_c = !flag_c;
			flag_v = diff_v;
			setres = 1'b1;
		end
		`ALU_RSB: begin
			{flag_c, result} = rdiff;
			flag_c = !flag_c;
			flag_v = rdiff_v;
			setres = 1'b1;
		end
		`ALU_ADD: begin
			{flag_c, result} = sum;
			flag_v = sum_v;
			setres = 1'b1;
		end
		`ALU_ADC: begin
			{flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
			flag_v = sum_v | (~sum[31] & result[31]);
			setres = 1'b1;
		end
		`ALU_SBC: begin
			{flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
			flag_c = !flag_c;
			flag_v = diff_v | (diff[31] & ~result[31]);
			setres = 1'b1;
		end
		`ALU_RSC: begin
			{flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
			flag_c = !flag_c;
			flag_v = rdiff_v | (rdiff[31] & ~result[31]);
			setres = 1'b1;
		end
		`ALU_TST: begin
			result = in0 & in1;
			flag_c = shifter_carry;
			setres = 1'b0;
		end
		`ALU_TEQ: begin
			result = in0 ^ in1;
			flag_c = shifter_carry;
			setres = 1'b0;
		end
		`ALU_CMP: begin
			{flag_c, result} = diff;
			flag_c = !flag_c;
			flag_v = diff_v;
			setres = 1'b0;
		end
		`ALU_CMN: begin
			{flag_c, result} = sum;
			flag_v = sum_v;
			setres = 1'b0;
		end
		`ALU_ORR: begin
			result = in0 | in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_MOV: begin
			result = in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_BIC: begin
			result = in0 & (~in1);
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_MVN: begin
			result = ~in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		endcase
		
		flag_z = (result == 0);
		flag_n = result[31];
		
		cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
	end
endmodule
Commit	Line	Data
5b3daee2 JW	1	module Execute(
	2	input clk,
	3	input Nrst, /* XXX not used yet */
	4
	5	input stall,
	6	input flush,
	7
	8	input inbubble,
	9	input [31:0] pc,
	10	input [31:0] insn,
	11	input [31:0] cpsr,
cb0428b6	12	input [31:0] spsr,
3f5cefe1 JW	13	input [31:0] op0,
	14	input [31:0] op1,
	15	input [31:0] op2,
	16	input carry,
5b3daee2 JW	17
5b3daee2 JW	18	output reg outstall = 0,
bc572c5f	19	output reg outbubble = 1,
6e3dfd79	20	output reg [31:0] outcpsr = 0,
cb0428b6	21	output reg [31:0] outspsr = 0,
fdecc897	22	output reg outcpsrup = 0,
bc572c5f JW	23	output reg write_reg = 1'bx,
bc572c5f JW	24	output reg [3:0] write_num = 4'bxxxx,
314dac21	25	output reg [31:0] write_data = 32'hxxxxxxxx,
149bcd1a	26	output reg [31:0] jmppc,
2393422a JW	27	output reg jmp,
2393422a JW	28	output reg [31:0] outpc,
c65110a8 JW	29	output reg [31:0] outinsn,
c65110a8 JW	30	output reg [31:0] outop0, outop1, outop2
5b3daee2	31	);
5b3daee2	32
bc572c5f JW	33	reg mult_start;
	34	reg [31:0] mult_acc0, mult_in0, mult_in1;
	35	wire mult_done;
	36	wire [31:0] mult_result;
	37
2b091cd4 JW	38	reg [31:0] alu_in0, alu_in1;
	39	reg [3:0] alu_op;
	40	reg alu_setflags;
6e3dfd79	41	wire [31:0] alu_result, alu_outcpsr;
732b7730 JW	42	wire alu_setres;
	43
	44	reg next_outbubble;
cb0428b6	45	reg [31:0] next_outcpsr, next_outspsr;
fdecc897	46	reg next_outcpsrup;
732b7730 JW	47	reg next_write_reg;
732b7730 JW	48	reg [3:0] next_write_num;
149bcd1a	49
732b7730	50	reg [31:0] next_write_data;
149bcd1a	51
bc572c5f JW	52	Multiplier multiplier(
	53	.clk(clk), .Nrst(Nrst),
	54	.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
	55	.in1(mult_in1), .done(mult_done), .result(mult_result));
6e3dfd79 JW	56
	57	ALU alu(
	58	.clk(clk), .Nrst(Nrst),
	59	.in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
	60	.setflags(alu_setflags), .shifter_carry(carry),
732b7730	61	.result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
b770ec9a	62
732b7730 JW	63	always @(posedge clk)
	64	begin
	65	if (!stall)
	66	begin
	67	outbubble <= next_outbubble;
	68	outcpsr <= next_outcpsr;
cb0428b6	69	outspsr <= next_outspsr;
fdecc897	70	outcpsrup <= next_outcpsrup;
732b7730 JW	71	write_reg <= next_write_reg;
	72	write_num <= next_write_num;
	73	write_data <= next_write_data;
2393422a JW	74	outpc <= pc;
2393422a JW	75	outinsn <= insn;
c65110a8 JW	76	outop0 <= op0;
	77	outop1 <= op1;
	78	outop2 <= op2;
732b7730 JW	79	end
732b7730 JW	80	end
b770ec9a JW	81
	82	reg delayedflush = 0;
	83	always @(posedge clk)
	84	if (flush && outstall /* halp! I can't do it now, maybe later? */)
	85	delayedflush <= 1;
	86	else if (!outstall /* anything has been handled this time around */)
	87	delayedflush <= 0;
2b091cd4	88
af096d96 JW	89	reg prevstall = 0;
	90	always @(posedge clk)
	91	prevstall <= outstall;
	92
2b091cd4	93	always @(*)
732b7730 JW	94	begin
732b7730 JW	95	outstall = stall;
b770ec9a	96	next_outbubble = inbubble \| flush \| delayedflush;
732b7730	97	next_outcpsr = cpsr;
cb0428b6	98	next_outspsr = spsr;
fdecc897	99	next_outcpsrup = 0;
732b7730 JW	100	next_write_reg = 0;
	101	next_write_num = 4'hx;
	102	next_write_data = 32'hxxxxxxxx;
149bcd1a	103
af096d96 JW	104	mult_start = 0;
	105	mult_acc0 = 32'hxxxxxxxx;
	106	mult_in0 = 32'hxxxxxxxx;
	107	mult_in1 = 32'hxxxxxxxx;
149bcd1a	108
732b7730 JW	109	alu_in0 = 32'hxxxxxxxx;
	110	alu_in1 = 32'hxxxxxxxx;
	111	alu_op = 4'hx; /* hax! */
	112	alu_setflags = 1'bx;
149bcd1a CL	113
149bcd1a CL	114	jmp = 1'b0;
ab7ee9fc	115	jmppc = 32'h00000000;
149bcd1a	116
2b091cd4	117	casez (insn)
af096d96 JW	118	`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	119	begin
	120	if (!prevstall && !inbubble)
	121	begin
	122	mult_start = 1;
	123	mult_acc0 = insn[21] /* A / ? op0 / Rn */ : 32'h0;
	124	mult_in0 = op1 /* Rm */;
	125	mult_in1 = op2 /* Rs */;
	126	$display("New MUL instruction");
	127	end
81a01a2b JW	128	outstall = outstall \| ((!prevstall \| !mult_done) && !inbubble);
81a01a2b JW	129	next_outbubble = next_outbubble \| !mult_done \| !prevstall;
af096d96	130	next_outcpsr = insn[20] /* S / ? {mult_result[31] / N /, mult_result == 0 / Z /, 1'b0 / C /, cpsr[28] / V */, cpsr[27:0]} : cpsr;
fdecc897	131	next_outcpsrup = insn[20] /* S */;
af096d96 JW	132	next_write_reg = 1;
	133	next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
	134	next_write_data = mult_result;
	135	end
2b091cd4	136	// `DECODE_ALU_MUL_LONG, /* Multiply long */
cb0428b6 JW	137	`DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
	138	begin
	139	next_write_reg = 1;
	140	next_write_num = insn[15:12];
	141	if (insn[22] /* Ps */)
	142	next_write_data = spsr;
	143	else
	144	next_write_data = cpsr;
fdecc897	145	next_outcpsrup = 1;
cb0428b6	146	end
2b091cd4	147	`DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
cb0428b6	148	`DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
fdecc897	149	begin
cb0428b6 JW	150	if ((cpsr[4:0] == `MODE_USR) \|\| (insn[16] /* that random bit / == 1'b0)) / flags only */
	151	begin
	152	if (insn[22] /* Ps */)
	153	next_outspsr = {op0[31:29], spsr[28:0]};
	154	else
	155	next_outcpsr = {op0[31:29], cpsr[28:0]};
	156	end else begin
	157	if (insn[22] /* Ps */)
	158	next_outspsr = op0;
	159	else
	160	next_outcpsr = op0;
	161	end
fdecc897 JW	162	next_outcpsrup = 1;
fdecc897 JW	163	end
2b091cd4 JW	164	`DECODE_ALU_SWP, /* Atomic swap */
	165	`DECODE_ALU_BX, /* Branch */
	166	`DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
732b7730 JW	167	`DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
	168	begin end
	169	`DECODE_ALU: /* ALU */
	170	begin
	171	alu_in0 = op0;
	172	alu_in1 = op1;
	173	alu_op = insn[24:21];
cb0428b6	174	alu_setflags = insn[20] /* S */;
732b7730 JW	175
	176	if (alu_setres) begin
	177	next_write_reg = 1;
	178	next_write_num = insn[15:12] /* Rd */;
	179	next_write_data = alu_result;
	180	end
	181
cb0428b6	182	next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
fdecc897	183	next_outcpsrup = insn[20] /* S */;
732b7730	184	end
2b091cd4 JW	185	`DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
2b091cd4 JW	186	`DECODE_LDRSTR, /* Single data transfer */
314dac21 CL	187	`DECODE_LDMSTM: /* Block data transfer */
	188	begin end
	189	`DECODE_BRANCH:
	190	begin
04281f32	191	if(!inbubble && !flush && !delayedflush && !outstall /* Let someone else take precedence. */) begin
f8bf38ca CL	192	jmppc = pc + op0 + 32'h8;
	193	if(insn[24]) begin
	194	next_write_reg = 1;
	195	next_write_num = 4'hE; /* link register */
dbf45af6	196	next_write_data = pc + 32'h4;
f8bf38ca CL	197	end
f8bf38ca CL	198	jmp = 1'b1;
314dac21 CL	199	end
314dac21 CL	200	end /* Branch */
2b091cd4 JW	201	`DECODE_LDCSTC, /* Coprocessor data transfer */
	202	`DECODE_CDP, /* Coprocessor data op */
	203	`DECODE_MRCMCR, /* Coprocessor register transfer */
	204	`DECODE_SWI: /* SWI */
	205	begin end
	206	default: /* X everything else out */
	207	begin end
	208	endcase
732b7730	209	end
5b3daee2	210	endmodule
07fbfa80 JW	211
	212	module Multiplier(
	213	input clk,
	214	input Nrst, /* XXX not used yet */
	215
	216	input start,
	217	input [31:0] acc0,
	218	input [31:0] in0,
	219	input [31:0] in1,
	220
	221	output reg done = 0,
	222	output reg [31:0] result);
	223
	224	reg [31:0] bitfield;
	225	reg [31:0] multiplicand;
	226	reg [31:0] acc;
	227
	228	always @(posedge clk)
	229	begin
	230	if (start) begin
	231	bitfield <= in0;
	232	multiplicand <= in1;
	233	acc <= acc0;
	234	done <= 0;
	235	end else begin
	236	bitfield <= {2'b00, bitfield[31:2]};
	237	multiplicand <= {multiplicand[29:0], 2'b00};
	238	acc <= acc +
	239	(bitfield[0] ? multiplicand : 0) +
	240	(bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
	241	if (bitfield == 0) begin
	242	result <= acc;
	243	done <= 1;
	244	end
	245	end
	246	end
	247	endmodule
879a3986	248
879a3986 CL	249	module ALU(
	250	input clk,
	251	input Nrst, /* XXX not used yet */
	252
	253	input [31:0] in0,
	254	input [31:0] in1,
	255	input [31:0] cpsr,
	256	input [3:0] op,
	257	input setflags,
	258	input shifter_carry,
	259
	260	output reg [31:0] result,
	261	output reg [31:0] cpsr_out,
732b7730	262	output reg setres
879a3986	263	);
7947b9c7 JW	264	reg [31:0] res;
7947b9c7 JW	265	reg flag_n, flag_z, flag_c, flag_v;
879a3986	266	wire [32:0] sum, diff, rdiff;
793482e9	267	wire sum_v, diff_v, rdiff_v;
879a3986 CL	268
	269	assign sum = {1'b0, in0} + {1'b0, in1};
	270	assign diff = {1'b0, in0} - {1'b0, in1};
a4c270c7	271	assign rdiff = {1'b0, in1} - {1'b0, in0};
793482e9 CL	272	assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
	273	assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
	274	assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
879a3986	275
879a3986 CL	276	always @(*) begin
	277	res = 32'hxxxxxxxx;
	278	setres = 1'bx;
	279	flag_c = cpsr[`CPSR_C];
	280	flag_v = cpsr[`CPSR_V];
	281	case(op)
	282	`ALU_AND: begin
732b7730	283	result = in0 & in1;
879a3986 CL	284	flag_c = shifter_carry;
	285	setres = 1'b1;
	286	end
	287	`ALU_EOR: begin
732b7730	288	result = in0 ^ in1;
879a3986 CL	289	flag_c = shifter_carry;
	290	setres = 1'b1;
	291	end
	292	`ALU_SUB: begin
732b7730	293	{flag_c, result} = diff;
1bc060d9	294	flag_c = !flag_c;
793482e9	295	flag_v = diff_v;
879a3986 CL	296	setres = 1'b1;
	297	end
	298	`ALU_RSB: begin
732b7730	299	{flag_c, result} = rdiff;
1bc060d9	300	flag_c = !flag_c;
793482e9	301	flag_v = rdiff_v;
879a3986 CL	302	setres = 1'b1;
	303	end
	304	`ALU_ADD: begin
732b7730	305	{flag_c, result} = sum;
793482e9	306	flag_v = sum_v;
879a3986 CL	307	setres = 1'b1;
	308	end
	309	`ALU_ADC: begin
732b7730	310	{flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
793482e9	311	flag_v = sum_v \| (~sum[31] & result[31]);
879a3986 CL	312	setres = 1'b1;
	313	end
	314	`ALU_SBC: begin
732b7730	315	{flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
1bc060d9	316	flag_c = !flag_c;
793482e9	317	flag_v = diff_v \| (diff[31] & ~result[31]);
879a3986 CL	318	setres = 1'b1;
	319	end
	320	`ALU_RSC: begin
732b7730	321	{flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
1bc060d9	322	flag_c = !flag_c;
793482e9	323	flag_v = rdiff_v \| (rdiff[31] & ~result[31]);
879a3986 CL	324	setres = 1'b1;
	325	end
	326	`ALU_TST: begin
732b7730	327	result = in0 & in1;
879a3986 CL	328	flag_c = shifter_carry;
	329	setres = 1'b0;
	330	end
	331	`ALU_TEQ: begin
732b7730	332	result = in0 ^ in1;
879a3986 CL	333	flag_c = shifter_carry;
	334	setres = 1'b0;
	335	end
	336	`ALU_CMP: begin
732b7730	337	{flag_c, result} = diff;
1bc060d9	338	flag_c = !flag_c;
793482e9	339	flag_v = diff_v;
879a3986 CL	340	setres = 1'b0;
	341	end
	342	`ALU_CMN: begin
732b7730	343	{flag_c, result} = sum;
793482e9	344	flag_v = sum_v;
879a3986 CL	345	setres = 1'b0;
	346	end
	347	`ALU_ORR: begin
732b7730	348	result = in0 \| in1;
879a3986 CL	349	flag_c = shifter_carry;
	350	setres = 1'b1;
	351	end
	352	`ALU_MOV: begin
732b7730	353	result = in1;
879a3986 CL	354	flag_c = shifter_carry;
	355	setres = 1'b1;
	356	end
	357	`ALU_BIC: begin
732b7730	358	result = in0 & (~in1);
879a3986 CL	359	flag_c = shifter_carry;
	360	setres = 1'b1;
	361	end
	362	`ALU_MVN: begin
732b7730	363	result = ~in1;
879a3986 CL	364	flag_c = shifter_carry;
	365	setres = 1'b1;
	366	end
	367	endcase
732b7730 JW	368
	369	flag_z = (result == 0);
	370	flag_n = result[31];
	371
	372	cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
879a3986	373	end
879a3986	374	endmodule