[firearm.git] / Execute.v

module Execute(
	input clk,
	input Nrst,	/* XXX not used yet */
	
	input stall,
	input flush,
	
	input inbubble,
	input [31:0] pc,
	input [31:0] insn,
	input [31:0] cpsr,
	input [31:0] op0,
	input [31:0] op1,
	input [31:0] op2,
	input carry,
	
	output reg outstall = 0,
	output reg outbubble = 1,
	output reg [31:0] outcpsr = 0,
	output reg write_reg = 1'bx,
	output reg [3:0] write_num = 4'bxxxx,
	output reg [31:0] write_data = 32'hxxxxxxxx
	);
	
	reg mult_start;
	reg [31:0] mult_acc0, mult_in0, mult_in1;
	wire mult_done;
	wire [31:0] mult_result;
	
	reg [31:0] alu_in0, alu_in1;
	reg [3:0] alu_op;
	reg alu_setflags;
	wire [31:0] alu_result, alu_outcpsr;
	wire alu_setres;
	
	reg next_outbubble;
	reg [31:0] next_outcpsr;
	reg next_write_reg;
	reg [3:0] next_write_num;
	reg [31:0] next_write_data;
	
	Multiplier multiplier(
		.clk(clk), .Nrst(Nrst),
		.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
		.in1(mult_in1), .done(mult_done), .result(mult_result));
	
	ALU alu(
		.clk(clk), .Nrst(Nrst),
		.in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
		.setflags(alu_setflags), .shifter_carry(carry),
		.result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
	
	always @(posedge clk)
	begin
		if (!stall)
		begin
			outbubble <= next_outbubble;
			outcpsr <= next_outcpsr;
			write_reg <= next_write_reg;
			write_num <= next_write_num;
			write_data <= next_write_data;
		end
	end

	reg prevstall = 0;
	always @(posedge clk)
		prevstall <= outstall;

	always @(*)
	begin
		outstall = stall;
		next_outbubble = inbubble;
		next_outcpsr = cpsr;
		next_write_reg = 0;
		next_write_num = 4'hx;
		next_write_data = 32'hxxxxxxxx;
	
		mult_start = 0;
		mult_acc0 = 32'hxxxxxxxx;
		mult_in0 = 32'hxxxxxxxx;
		mult_in1 = 32'hxxxxxxxx;
	
		alu_in0 = 32'hxxxxxxxx;
		alu_in1 = 32'hxxxxxxxx;
		alu_op = 4'hx;	/* hax! */
		alu_setflags = 1'bx;
		
		casez (insn)
		`DECODE_ALU_MULT:	/* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
		begin
			if (!prevstall && !inbubble)
			begin
				mult_start = 1;
				mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
				mult_in0 = op1 /* Rm */;
				mult_in1 = op2 /* Rs */;
				$display("New MUL instruction");
			end
			outstall = stall | ((!prevstall | !mult_done) && !inbubble);
			next_outbubble = inbubble | !mult_done | !prevstall;
			next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
			next_write_reg = 1;
			next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
			next_write_data = mult_result;
		end
//		`DECODE_ALU_MUL_LONG,	/* Multiply long */
		`DECODE_ALU_MRS,	/* MRS (Transfer PSR to register) */
		`DECODE_ALU_MSR,	/* MSR (Transfer register to PSR) */
		`DECODE_ALU_MSR_FLAGS,	/* MSR (Transfer register or immediate to PSR, flag bits only) */
		`DECODE_ALU_SWP,	/* Atomic swap */
		`DECODE_ALU_BX,		/* Branch */
		`DECODE_ALU_HDATA_REG,	/* Halfword transfer - register offset */
		`DECODE_ALU_HDATA_IMM:	/* Halfword transfer - immediate offset */
		begin end
		`DECODE_ALU:		/* ALU */
		begin
			alu_in0 = op0;
			alu_in1 = op1;
			alu_op = insn[24:21];
			alu_setflags = insn[20] /* I */;
			
			if (alu_setres) begin
				next_write_reg = 1;
				next_write_num = insn[15:12] /* Rd */;
				next_write_data = alu_result;
			end
			
			next_outcpsr = alu_outcpsr;
		end
		`DECODE_LDRSTR_UNDEFINED,	/* Undefined. I hate ARM */
		`DECODE_LDRSTR,		/* Single data transfer */
		`DECODE_LDMSTM,		/* Block data transfer */
		`DECODE_BRANCH,		/* Branch */
		`DECODE_LDCSTC,		/* Coprocessor data transfer */
		`DECODE_CDP,		/* Coprocessor data op */
		`DECODE_MRCMCR,		/* Coprocessor register transfer */
		`DECODE_SWI:		/* SWI */
		begin end
		default:		/* X everything else out */
		begin end
		endcase
	end
endmodule

module Multiplier(
	input clk,
	input Nrst,	/* XXX not used yet */
	
	input start,
	input [31:0] acc0,
	input [31:0] in0,
	input [31:0] in1,
	
	output reg done = 0,
	output reg [31:0] result);
	
	reg [31:0] bitfield;
	reg [31:0] multiplicand;
	reg [31:0] acc;
	
	always @(posedge clk)
	begin
		if (start) begin
			bitfield <= in0;
			multiplicand <= in1;
			acc <= acc0;
			done <= 0;
		end else begin
			bitfield <= {2'b00, bitfield[31:2]};
			multiplicand <= {multiplicand[29:0], 2'b00};
			acc <= acc +
				(bitfield[0] ? multiplicand : 0) +
				(bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
			if (bitfield == 0) begin
				result <= acc;
				done <= 1;
			end
		end
	end
endmodule

/* XXX is the interface correct? */
module ALU(
	input clk,
	input Nrst,	/* XXX not used yet */

	input [31:0] in0,
	input [31:0] in1,
	input [31:0] cpsr,
	input [3:0] op,
	input setflags,
	input shifter_carry,

	output reg [31:0] result,
	output reg [31:0] cpsr_out,
	output reg setres
);
	wire [31:0] res;
	wire flag_n, flag_z, flag_c, flag_v, setres;
	wire [32:0] sum, diff, rdiff;

	assign sum = {1'b0, in0} + {1'b0, in1};
	assign diff = {1'b0, in0} - {1'b0, in1};
	assign rdiff = {1'b0, in1} + {1'b0, in0};

	/* TODO XXX flag_v not set correctly */
	always @(*) begin
		res = 32'hxxxxxxxx;
		setres = 1'bx;
		flag_c = cpsr[`CPSR_C];
		flag_v = cpsr[`CPSR_V];
		case(op)
		`ALU_AND: begin
			result = in0 & in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_EOR: begin
			result = in0 ^ in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_SUB: begin
			{flag_c, result} = diff;
			setres = 1'b1;
		end
		`ALU_RSB: begin
			{flag_c, result} = rdiff;
			setres = 1'b1;
		end
		`ALU_ADD: begin
			{flag_c, result} = sum;
			setres = 1'b1;
		end
		`ALU_ADC: begin
			{flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
			setres = 1'b1;
		end
		`ALU_SBC: begin
			{flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
			setres = 1'b1;
		end
		`ALU_RSC: begin
			{flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
			setres = 1'b1;
		end
		`ALU_TST: begin
			result = in0 & in1;
			flag_c = shifter_carry;
			setres = 1'b0;
		end
		`ALU_TEQ: begin
			result = in0 ^ in1;
			flag_c = shifter_carry;
			setres = 1'b0;
		end
		`ALU_CMP: begin
			{flag_c, result} = diff;
			setres = 1'b0;
		end
		`ALU_CMN: begin
			{flag_c, result} = sum;
			setres = 1'b0;
		end
		`ALU_ORR: begin
			result = in0 | in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_MOV: begin
			result = in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_BIC: begin
			result = in0 & (~in1);
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		`ALU_MVN: begin
			result = ~in1;
			flag_c = shifter_carry;
			setres = 1'b1;
		end
		endcase
		
		flag_z = (result == 0);
		flag_n = result[31];
		
		cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
	end
endmodule
Commit	Line	Data
5b3daee2 JW	1	module Execute(
	2	input clk,
	3	input Nrst, /* XXX not used yet */
	4
	5	input stall,
	6	input flush,
	7
	8	input inbubble,
	9	input [31:0] pc,
	10	input [31:0] insn,
	11	input [31:0] cpsr,
3f5cefe1 JW	12	input [31:0] op0,
	13	input [31:0] op1,
	14	input [31:0] op2,
	15	input carry,
5b3daee2 JW	16
5b3daee2 JW	17	output reg outstall = 0,
bc572c5f	18	output reg outbubble = 1,
6e3dfd79	19	output reg [31:0] outcpsr = 0,
bc572c5f JW	20	output reg write_reg = 1'bx,
	21	output reg [3:0] write_num = 4'bxxxx,
	22	output reg [31:0] write_data = 32'hxxxxxxxx
5b3daee2	23	);
5b3daee2	24
bc572c5f JW	25	reg mult_start;
	26	reg [31:0] mult_acc0, mult_in0, mult_in1;
	27	wire mult_done;
	28	wire [31:0] mult_result;
	29
2b091cd4 JW	30	reg [31:0] alu_in0, alu_in1;
	31	reg [3:0] alu_op;
	32	reg alu_setflags;
6e3dfd79	33	wire [31:0] alu_result, alu_outcpsr;
732b7730 JW	34	wire alu_setres;
	35
	36	reg next_outbubble;
	37	reg [31:0] next_outcpsr;
	38	reg next_write_reg;
	39	reg [3:0] next_write_num;
	40	reg [31:0] next_write_data;
6e3dfd79	41
bc572c5f JW	42	Multiplier multiplier(
	43	.clk(clk), .Nrst(Nrst),
	44	.start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
	45	.in1(mult_in1), .done(mult_done), .result(mult_result));
6e3dfd79 JW	46
	47	ALU alu(
	48	.clk(clk), .Nrst(Nrst),
	49	.in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
	50	.setflags(alu_setflags), .shifter_carry(carry),
732b7730 JW	51	.result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
	52
	53	always @(posedge clk)
	54	begin
	55	if (!stall)
	56	begin
	57	outbubble <= next_outbubble;
	58	outcpsr <= next_outcpsr;
	59	write_reg <= next_write_reg;
	60	write_num <= next_write_num;
	61	write_data <= next_write_data;
	62	end
	63	end
2b091cd4	64
af096d96 JW	65	reg prevstall = 0;
	66	always @(posedge clk)
	67	prevstall <= outstall;
	68
2b091cd4	69	always @(*)
732b7730 JW	70	begin
	71	outstall = stall;
	72	next_outbubble = inbubble;
	73	next_outcpsr = cpsr;
	74	next_write_reg = 0;
	75	next_write_num = 4'hx;
	76	next_write_data = 32'hxxxxxxxx;
	77
af096d96 JW	78	mult_start = 0;
	79	mult_acc0 = 32'hxxxxxxxx;
	80	mult_in0 = 32'hxxxxxxxx;
	81	mult_in1 = 32'hxxxxxxxx;
	82
732b7730 JW	83	alu_in0 = 32'hxxxxxxxx;
	84	alu_in1 = 32'hxxxxxxxx;
	85	alu_op = 4'hx; /* hax! */
	86	alu_setflags = 1'bx;
	87
2b091cd4	88	casez (insn)
af096d96 JW	89	`DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
	90	begin
	91	if (!prevstall && !inbubble)
	92	begin
	93	mult_start = 1;
	94	mult_acc0 = insn[21] /* A / ? op0 / Rn */ : 32'h0;
	95	mult_in0 = op1 /* Rm */;
	96	mult_in1 = op2 /* Rs */;
	97	$display("New MUL instruction");
	98	end
	99	outstall = stall \| ((!prevstall \| !mult_done) && !inbubble);
	100	next_outbubble = inbubble \| !mult_done \| !prevstall;
	101	next_outcpsr = insn[20] /* S / ? {mult_result[31] / N /, mult_result == 0 / Z /, 1'b0 / C /, cpsr[28] / V */, cpsr[27:0]} : cpsr;
	102	next_write_reg = 1;
	103	next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
	104	next_write_data = mult_result;
	105	end
2b091cd4 JW	106	// `DECODE_ALU_MUL_LONG, /* Multiply long */
	107	`DECODE_ALU_MRS, /* MRS (Transfer PSR to register) */
	108	`DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
	109	`DECODE_ALU_MSR_FLAGS, /* MSR (Transfer register or immediate to PSR, flag bits only) */
	110	`DECODE_ALU_SWP, /* Atomic swap */
	111	`DECODE_ALU_BX, /* Branch */
	112	`DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
732b7730 JW	113	`DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
	114	begin end
	115	`DECODE_ALU: /* ALU */
	116	begin
	117	alu_in0 = op0;
	118	alu_in1 = op1;
	119	alu_op = insn[24:21];
	120	alu_setflags = insn[20] /* I */;
	121
	122	if (alu_setres) begin
	123	next_write_reg = 1;
	124	next_write_num = insn[15:12] /* Rd */;
	125	next_write_data = alu_result;
	126	end
	127
	128	next_outcpsr = alu_outcpsr;
	129	end
2b091cd4 JW	130	`DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
	131	`DECODE_LDRSTR, /* Single data transfer */
	132	`DECODE_LDMSTM, /* Block data transfer */
	133	`DECODE_BRANCH, /* Branch */
	134	`DECODE_LDCSTC, /* Coprocessor data transfer */
	135	`DECODE_CDP, /* Coprocessor data op */
	136	`DECODE_MRCMCR, /* Coprocessor register transfer */
	137	`DECODE_SWI: /* SWI */
	138	begin end
	139	default: /* X everything else out */
	140	begin end
	141	endcase
732b7730	142	end
5b3daee2	143	endmodule
07fbfa80 JW	144
	145	module Multiplier(
	146	input clk,
	147	input Nrst, /* XXX not used yet */
	148
	149	input start,
	150	input [31:0] acc0,
	151	input [31:0] in0,
	152	input [31:0] in1,
	153
	154	output reg done = 0,
	155	output reg [31:0] result);
	156
	157	reg [31:0] bitfield;
	158	reg [31:0] multiplicand;
	159	reg [31:0] acc;
	160
	161	always @(posedge clk)
	162	begin
	163	if (start) begin
	164	bitfield <= in0;
	165	multiplicand <= in1;
	166	acc <= acc0;
	167	done <= 0;
	168	end else begin
	169	bitfield <= {2'b00, bitfield[31:2]};
	170	multiplicand <= {multiplicand[29:0], 2'b00};
	171	acc <= acc +
	172	(bitfield[0] ? multiplicand : 0) +
	173	(bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
	174	if (bitfield == 0) begin
	175	result <= acc;
	176	done <= 1;
	177	end
	178	end
	179	end
	180	endmodule
879a3986 CL	181
	182	/* XXX is the interface correct? */
	183	module ALU(
	184	input clk,
	185	input Nrst, /* XXX not used yet */
	186
	187	input [31:0] in0,
	188	input [31:0] in1,
	189	input [31:0] cpsr,
	190	input [3:0] op,
	191	input setflags,
	192	input shifter_carry,
	193
	194	output reg [31:0] result,
	195	output reg [31:0] cpsr_out,
732b7730	196	output reg setres
879a3986 CL	197	);
	198	wire [31:0] res;
	199	wire flag_n, flag_z, flag_c, flag_v, setres;
	200	wire [32:0] sum, diff, rdiff;
	201
	202	assign sum = {1'b0, in0} + {1'b0, in1};
	203	assign diff = {1'b0, in0} - {1'b0, in1};
	204	assign rdiff = {1'b0, in1} + {1'b0, in0};
	205
	206	/* TODO XXX flag_v not set correctly */
	207	always @(*) begin
	208	res = 32'hxxxxxxxx;
	209	setres = 1'bx;
	210	flag_c = cpsr[`CPSR_C];
	211	flag_v = cpsr[`CPSR_V];
	212	case(op)
	213	`ALU_AND: begin
732b7730	214	result = in0 & in1;
879a3986 CL	215	flag_c = shifter_carry;
	216	setres = 1'b1;
	217	end
	218	`ALU_EOR: begin
732b7730	219	result = in0 ^ in1;
879a3986 CL	220	flag_c = shifter_carry;
	221	setres = 1'b1;
	222	end
	223	`ALU_SUB: begin
732b7730	224	{flag_c, result} = diff;
879a3986 CL	225	setres = 1'b1;
	226	end
	227	`ALU_RSB: begin
732b7730	228	{flag_c, result} = rdiff;
879a3986 CL	229	setres = 1'b1;
	230	end
	231	`ALU_ADD: begin
732b7730	232	{flag_c, result} = sum;
879a3986 CL	233	setres = 1'b1;
	234	end
	235	`ALU_ADC: begin
732b7730	236	{flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
879a3986 CL	237	setres = 1'b1;
	238	end
	239	`ALU_SBC: begin
732b7730	240	{flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
879a3986 CL	241	setres = 1'b1;
	242	end
	243	`ALU_RSC: begin
732b7730	244	{flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
879a3986 CL	245	setres = 1'b1;
	246	end
	247	`ALU_TST: begin
732b7730	248	result = in0 & in1;
879a3986 CL	249	flag_c = shifter_carry;
	250	setres = 1'b0;
	251	end
	252	`ALU_TEQ: begin
732b7730	253	result = in0 ^ in1;
879a3986 CL	254	flag_c = shifter_carry;
	255	setres = 1'b0;
	256	end
	257	`ALU_CMP: begin
732b7730	258	{flag_c, result} = diff;
879a3986 CL	259	setres = 1'b0;
	260	end
	261	`ALU_CMN: begin
732b7730	262	{flag_c, result} = sum;
879a3986 CL	263	setres = 1'b0;
	264	end
	265	`ALU_ORR: begin
732b7730	266	result = in0 \| in1;
879a3986 CL	267	flag_c = shifter_carry;
	268	setres = 1'b1;
	269	end
	270	`ALU_MOV: begin
732b7730	271	result = in1;
879a3986 CL	272	flag_c = shifter_carry;
	273	setres = 1'b1;
	274	end
	275	`ALU_BIC: begin
732b7730	276	result = in0 & (~in1);
879a3986 CL	277	flag_c = shifter_carry;
	278	setres = 1'b1;
	279	end
	280	`ALU_MVN: begin
732b7730	281	result = ~in1;
879a3986 CL	282	flag_c = shifter_carry;
	283	setres = 1'b1;
	284	end
	285	endcase
732b7730 JW	286
	287	flag_z = (result == 0);
	288	flag_n = result[31];
	289
	290	cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
879a3986	291	end
879a3986	292	endmodule