st_data -> op2
[firearm.git] / Execute.v
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5b3daee2
JW
1module Execute(
2 input clk,
3 input Nrst, /* XXX not used yet */
4
5 input stall,
6 input flush,
7
8 input inbubble,
9 input [31:0] pc,
10 input [31:0] insn,
11 input [31:0] cpsr,
cb0428b6 12 input [31:0] spsr,
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13 input [31:0] op0,
14 input [31:0] op1,
15 input [31:0] op2,
16 input carry,
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17
18 output reg outstall = 0,
bc572c5f 19 output reg outbubble = 1,
6e3dfd79 20 output reg [31:0] outcpsr = 0,
cb0428b6 21 output reg [31:0] outspsr = 0,
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22 output reg write_reg = 1'bx,
23 output reg [3:0] write_num = 4'bxxxx,
314dac21 24 output reg [31:0] write_data = 32'hxxxxxxxx,
149bcd1a 25 output reg [31:0] jmppc,
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26 output reg jmp,
27 output reg [31:0] outpc,
28 output reg [31:0] outinsn
5b3daee2 29 );
5b3daee2 30
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31 reg mult_start;
32 reg [31:0] mult_acc0, mult_in0, mult_in1;
33 wire mult_done;
34 wire [31:0] mult_result;
35
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36 reg [31:0] alu_in0, alu_in1;
37 reg [3:0] alu_op;
38 reg alu_setflags;
6e3dfd79 39 wire [31:0] alu_result, alu_outcpsr;
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40 wire alu_setres;
41
42 reg next_outbubble;
cb0428b6 43 reg [31:0] next_outcpsr, next_outspsr;
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44 reg next_write_reg;
45 reg [3:0] next_write_num;
149bcd1a 46
732b7730 47 reg [31:0] next_write_data;
149bcd1a 48
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49 Multiplier multiplier(
50 .clk(clk), .Nrst(Nrst),
51 .start(mult_start), .acc0(mult_acc0), .in0(mult_in0),
52 .in1(mult_in1), .done(mult_done), .result(mult_result));
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53
54 ALU alu(
55 .clk(clk), .Nrst(Nrst),
56 .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
57 .setflags(alu_setflags), .shifter_carry(carry),
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58 .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
59
60 always @(posedge clk)
61 begin
62 if (!stall)
63 begin
64 outbubble <= next_outbubble;
65 outcpsr <= next_outcpsr;
cb0428b6 66 outspsr <= next_outspsr;
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67 write_reg <= next_write_reg;
68 write_num <= next_write_num;
69 write_data <= next_write_data;
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70 outpc <= pc;
71 outinsn <= insn;
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72 end
73 end
2b091cd4 74
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75 reg prevstall = 0;
76 always @(posedge clk)
77 prevstall <= outstall;
78
2b091cd4 79 always @(*)
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80 begin
81 outstall = stall;
149bcd1a 82 next_outbubble = inbubble | flush;
732b7730 83 next_outcpsr = cpsr;
cb0428b6 84 next_outspsr = spsr;
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85 next_write_reg = 0;
86 next_write_num = 4'hx;
87 next_write_data = 32'hxxxxxxxx;
149bcd1a 88
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89 mult_start = 0;
90 mult_acc0 = 32'hxxxxxxxx;
91 mult_in0 = 32'hxxxxxxxx;
92 mult_in1 = 32'hxxxxxxxx;
149bcd1a 93
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94 alu_in0 = 32'hxxxxxxxx;
95 alu_in1 = 32'hxxxxxxxx;
96 alu_op = 4'hx; /* hax! */
97 alu_setflags = 1'bx;
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CL
98
99 jmp = 1'b0;
100 jmppc = 32'hxxxxxxxx;
101
2b091cd4 102 casez (insn)
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103 `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
104 begin
105 if (!prevstall && !inbubble)
106 begin
107 mult_start = 1;
108 mult_acc0 = insn[21] /* A */ ? op0 /* Rn */ : 32'h0;
109 mult_in0 = op1 /* Rm */;
110 mult_in1 = op2 /* Rs */;
111 $display("New MUL instruction");
112 end
113 outstall = stall | ((!prevstall | !mult_done) && !inbubble);
114 next_outbubble = inbubble | !mult_done | !prevstall;
115 next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
116 next_write_reg = 1;
117 next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
118 next_write_data = mult_result;
119 end
2b091cd4 120// `DECODE_ALU_MUL_LONG, /* Multiply long */
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121 `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */
122 begin
123 next_write_reg = 1;
124 next_write_num = insn[15:12];
125 if (insn[22] /* Ps */)
126 next_write_data = spsr;
127 else
128 next_write_data = cpsr;
129 end
2b091cd4 130 `DECODE_ALU_MSR, /* MSR (Transfer register to PSR) */
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131 `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */
132 if ((cpsr[4:0] == `MODE_USR) || (insn[16] /* that random bit */ == 1'b0)) /* flags only */
133 begin
134 if (insn[22] /* Ps */)
135 next_outspsr = {op0[31:29], spsr[28:0]};
136 else
137 next_outcpsr = {op0[31:29], cpsr[28:0]};
138 end else begin
139 if (insn[22] /* Ps */)
140 next_outspsr = op0;
141 else
142 next_outcpsr = op0;
143 end
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144 `DECODE_ALU_SWP, /* Atomic swap */
145 `DECODE_ALU_BX, /* Branch */
146 `DECODE_ALU_HDATA_REG, /* Halfword transfer - register offset */
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147 `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */
148 begin end
149 `DECODE_ALU: /* ALU */
150 begin
151 alu_in0 = op0;
152 alu_in1 = op1;
153 alu_op = insn[24:21];
cb0428b6 154 alu_setflags = insn[20] /* S */;
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155
156 if (alu_setres) begin
157 next_write_reg = 1;
158 next_write_num = insn[15:12] /* Rd */;
159 next_write_data = alu_result;
160 end
161
cb0428b6 162 next_outcpsr = ((insn[15:12] == 4'b1111) && insn[20]) ? spsr : alu_outcpsr;
732b7730 163 end
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164 `DECODE_LDRSTR_UNDEFINED, /* Undefined. I hate ARM */
165 `DECODE_LDRSTR, /* Single data transfer */
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CL
166 `DECODE_LDMSTM: /* Block data transfer */
167 begin end
168 `DECODE_BRANCH:
169 begin
7947b9c7 170 if(!inbubble) begin
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CL
171 jmppc = pc + op0 + 32'h8;
172 if(insn[24]) begin
173 next_write_reg = 1;
174 next_write_num = 4'hE; /* link register */
7947b9c7 175 next_write_data = pc - 32'h4;
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CL
176 end
177 jmp = 1'b1;
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CL
178 end
179 end /* Branch */
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180 `DECODE_LDCSTC, /* Coprocessor data transfer */
181 `DECODE_CDP, /* Coprocessor data op */
182 `DECODE_MRCMCR, /* Coprocessor register transfer */
183 `DECODE_SWI: /* SWI */
184 begin end
185 default: /* X everything else out */
186 begin end
187 endcase
732b7730 188 end
5b3daee2 189endmodule
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190
191module Multiplier(
192 input clk,
193 input Nrst, /* XXX not used yet */
194
195 input start,
196 input [31:0] acc0,
197 input [31:0] in0,
198 input [31:0] in1,
199
200 output reg done = 0,
201 output reg [31:0] result);
202
203 reg [31:0] bitfield;
204 reg [31:0] multiplicand;
205 reg [31:0] acc;
206
207 always @(posedge clk)
208 begin
209 if (start) begin
210 bitfield <= in0;
211 multiplicand <= in1;
212 acc <= acc0;
213 done <= 0;
214 end else begin
215 bitfield <= {2'b00, bitfield[31:2]};
216 multiplicand <= {multiplicand[29:0], 2'b00};
217 acc <= acc +
218 (bitfield[0] ? multiplicand : 0) +
219 (bitfield[1] ? {multiplicand[30:0], 1'b0} : 0);
220 if (bitfield == 0) begin
221 result <= acc;
222 done <= 1;
223 end
224 end
225 end
226endmodule
879a3986 227
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CL
228module ALU(
229 input clk,
230 input Nrst, /* XXX not used yet */
231
232 input [31:0] in0,
233 input [31:0] in1,
234 input [31:0] cpsr,
235 input [3:0] op,
236 input setflags,
237 input shifter_carry,
238
239 output reg [31:0] result,
240 output reg [31:0] cpsr_out,
732b7730 241 output reg setres
879a3986 242);
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243 reg [31:0] res;
244 reg flag_n, flag_z, flag_c, flag_v;
879a3986 245 wire [32:0] sum, diff, rdiff;
793482e9 246 wire sum_v, diff_v, rdiff_v;
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247
248 assign sum = {1'b0, in0} + {1'b0, in1};
249 assign diff = {1'b0, in0} - {1'b0, in1};
250 assign rdiff = {1'b0, in1} + {1'b0, in0};
793482e9
CL
251 assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
252 assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
253 assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);
879a3986 254
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CL
255 always @(*) begin
256 res = 32'hxxxxxxxx;
257 setres = 1'bx;
258 flag_c = cpsr[`CPSR_C];
259 flag_v = cpsr[`CPSR_V];
260 case(op)
261 `ALU_AND: begin
732b7730 262 result = in0 & in1;
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263 flag_c = shifter_carry;
264 setres = 1'b1;
265 end
266 `ALU_EOR: begin
732b7730 267 result = in0 ^ in1;
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268 flag_c = shifter_carry;
269 setres = 1'b1;
270 end
271 `ALU_SUB: begin
732b7730 272 {flag_c, result} = diff;
793482e9 273 flag_v = diff_v;
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274 setres = 1'b1;
275 end
276 `ALU_RSB: begin
732b7730 277 {flag_c, result} = rdiff;
793482e9 278 flag_v = rdiff_v;
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279 setres = 1'b1;
280 end
281 `ALU_ADD: begin
732b7730 282 {flag_c, result} = sum;
793482e9 283 flag_v = sum_v;
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284 setres = 1'b1;
285 end
286 `ALU_ADC: begin
732b7730 287 {flag_c, result} = sum + {32'b0, cpsr[`CPSR_C]};
793482e9 288 flag_v = sum_v | (~sum[31] & result[31]);
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289 setres = 1'b1;
290 end
291 `ALU_SBC: begin
732b7730 292 {flag_c, result} = diff - {32'b0, (~cpsr[`CPSR_C])};
793482e9 293 flag_v = diff_v | (diff[31] & ~result[31]);
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294 setres = 1'b1;
295 end
296 `ALU_RSC: begin
732b7730 297 {flag_c, result} = rdiff - {32'b0, (~cpsr[`CPSR_C])};
793482e9 298 flag_v = rdiff_v | (rdiff[31] & ~result[31]);
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CL
299 setres = 1'b1;
300 end
301 `ALU_TST: begin
732b7730 302 result = in0 & in1;
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CL
303 flag_c = shifter_carry;
304 setres = 1'b0;
305 end
306 `ALU_TEQ: begin
732b7730 307 result = in0 ^ in1;
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CL
308 flag_c = shifter_carry;
309 setres = 1'b0;
310 end
311 `ALU_CMP: begin
732b7730 312 {flag_c, result} = diff;
793482e9 313 flag_v = diff_v;
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CL
314 setres = 1'b0;
315 end
316 `ALU_CMN: begin
732b7730 317 {flag_c, result} = sum;
793482e9 318 flag_v = sum_v;
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319 setres = 1'b0;
320 end
321 `ALU_ORR: begin
732b7730 322 result = in0 | in1;
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323 flag_c = shifter_carry;
324 setres = 1'b1;
325 end
326 `ALU_MOV: begin
732b7730 327 result = in1;
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328 flag_c = shifter_carry;
329 setres = 1'b1;
330 end
331 `ALU_BIC: begin
732b7730 332 result = in0 & (~in1);
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333 flag_c = shifter_carry;
334 setres = 1'b1;
335 end
336 `ALU_MVN: begin
732b7730 337 result = ~in1;
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338 flag_c = shifter_carry;
339 setres = 1'b1;
340 end
341 endcase
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342
343 flag_z = (result == 0);
344 flag_n = result[31];
345
346 cpsr_out = setflags ? {flag_n, flag_z, flag_c, flag_v, cpsr[27:0]} : cpsr;
879a3986 347 end
879a3986 348endmodule
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