ich2/smi.c

   1 /* smi.c
   2  * System management interrupt dispatch routines for ICH2 southbridge
   3  * NetWatch system management mode administration console
   4  *
   5  * Copyright (c) 2008 Jacob Potter and Joshua Wise.  All rights reserved.
   6  * This program is free software; you can redistribute and/or modify it under
   7  * the terms found in the file LICENSE in the root of this source tree.
   8  *
   9  */
  10
  11
  12 #include <smi.h>
  13 #include <pci.h>
  14 #include <io.h>
  15 #include <stdint.h>
  16 #include <vga-overlay.h>
  17 #include <reg-82801b.h>
  18 #include <output.h>
  19
  20 static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
  21
  22 static uint16_t _get_PMBASE()
  23 {
  24         static long pmbase = -1;
  25
  26         if (pmbase == -1)       /* Memoize it so that we don't have to hit PCI so often. */
  27                 pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
  28
  29         return pmbase;
  30 }
  31
  32 void smi_disable()
  33 {
  34         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  35         outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
  36 }
  37
  38 void smi_enable()
  39 {
  40         unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
  41         outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
  42 }
  43
  44 unsigned long smi_status()
  45 {
  46         unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
  47         return inl(smi_sts);
  48 }
  49
  50 void smi_poll()
  51 {
  52         unsigned long sts = smi_status();
  53
  54         if (sts & ICH2_SMI_STS_BIOS_STS)
  55         {
  56                 if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
  57                         output("Unhandled: BIOS_STS");
  58                 else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
  59                         _handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
  60                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
  61         }
  62
  63         if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
  64         {
  65                 output("Unhandled: LEGACY_USB_STS");
  66                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
  67         }
  68
  69         if (sts & ICH2_SMI_STS_SLP_SMI_STS)
  70         {
  71                 output("Unhandled: SLP_SMI_STS");
  72                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
  73         }
  74
  75         if (sts & ICH2_SMI_STS_APM_STS)
  76         {
  77                 output("Unhandled: APM_STS");
  78                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
  79         }
  80
  81         if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)   // Ack it, then request another.
  82         {
  83                 if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
  84                         output("Unhandled: SWSMI_TMR_STS");
  85                 else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
  86                         _handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
  87                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
  88         }
  89
  90         if (sts & ICH2_SMI_STS_PM1_STS_REG)
  91         {
  92                 unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
  93                 unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
  94
  95                 pm1_sts &= pm1_en;
  96                 if (pm1_sts & ICH2_PM1_STS_RTC_STS)
  97                 {
  98                         output("Unhandled: PM1_STS: RTC_STS");
  99                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
 100                 }
 101
 102                 if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
 103                 {
 104                         output("Unhandled: PM1_STS: PWRBTN_STS");
 105                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
 106                 }
 107
 108                 if (pm1_sts & ICH2_PM1_STS_GBL_STS)
 109                 {
 110                         output("Unhandled: PM1_STS: GBL_STS");
 111                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
 112                 }
 113
 114                 if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
 115                 {
 116                         output("Unhandled: PM1_STS: TMROF_STS");
 117                         outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
 118                 }
 119
 120                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
 121         }
 122
 123         if (sts & ICH2_SMI_STS_GPE0_STS)
 124         {
 125                 /* XXX -- trawl through GPE0_STS to see what happened */
 126                 output("XXX Unhandled: GPE0_STS (expect lockup)");
 127         }
 128
 129         if (sts & ICH2_SMI_STS_GPE1_STS)
 130         {
 131                 /* XXX -- trawl through GPE1_STS to see what happened */
 132                 output("XXX Unhandled: GPE1_STS (expect lockup)");
 133         }
 134
 135         if (sts & ICH2_SMI_STS_MCSMI_STS)
 136         {
 137                 output("Unhandled: MCSMI_STS");
 138                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
 139         }
 140
 141         if (sts & ICH2_SMI_STS_DEVMON_STS)
 142         {
 143                 unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 144                 unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 145                 unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 146
 147                 if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
 148                 {
 149                         if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
 150                                 output("Unhandled: DEVACT_KBC_ACT_STS");
 151                         else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
 152                                 _handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
 153                         outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
 154                 }
 155
 156                 /* Refresh register cache so that we can print unhandleds as needed. */
 157                 mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
 158                 devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
 159                 devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
 160
 161                 if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
 162                         outputf("Unhandled: MON_SMI (%04x)", mon_smi);
 163                 if (devact_sts & devtrap_en)
 164                         outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
 165         }
 166
 167         if (sts & ICH2_SMI_STS_TCO_STS)
 168         {
 169                 output("Unhandled: TCO_STS");
 170                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
 171         }
 172
 173         if (sts & ICH2_SMI_STS_PERIODIC_STS)
 174         {
 175                 output("Unhandled: PERIODIC_STS");
 176                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
 177         }
 178
 179         if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
 180         {
 181                 output("Unhandled: SERIRQ_SMI_STS");
 182                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
 183         }
 184
 185         if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
 186         {
 187                 output("Unhandled: SMBUS_SMI_STS");
 188                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
 189         }
 190
 191         if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)   /* Either the chipset is buggy, or we are. */
 192                 outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
 193
 194         outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 195                 inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 196                         ICH2_SMI_EN_EOS |
 197                         ICH2_SMI_EN_GBL_SMI_EN);
 198 }
 199
 200 int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
 201 {
 202         if (ev >= SMI_EVENT_MAX)
 203                 return -1;
 204         _handlers[ev] = hnd;
 205         return 0;
 206 }
 207
 208 int smi_enable_event(smi_event_t ev)
 209 {
 210         switch(ev)
 211         {
 212         case SMI_EVENT_FAST_TIMER:
 213                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 214                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 215                                 ICH2_SMI_EN_SWSMI_TMR_EN);
 216                 return 0;
 217         case SMI_EVENT_DEVTRAP_KBC:
 218                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 219                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
 220                                 ICH2_DEVTRAP_EN_KBC_TRP_EN);
 221                 return 0;
 222         case SMI_EVENT_GBL_RLS:
 223                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 224                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
 225                                 ICH2_SMI_EN_BIOS_EN);
 226                 return 0;
 227         default:
 228                 return -1;
 229         }
 230 }
 231
 232 int smi_disable_event(smi_event_t ev)
 233 {
 234         switch(ev)
 235         {
 236         case SMI_EVENT_FAST_TIMER:
 237                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 238                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 239                                 ~ICH2_SMI_EN_SWSMI_TMR_EN);
 240                 return 0;
 241         case SMI_EVENT_DEVTRAP_KBC:
 242                 outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
 243                         inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
 244                                 ~ICH2_DEVTRAP_EN_KBC_TRP_EN);
 245                 return 0;
 246         case SMI_EVENT_GBL_RLS:
 247                 outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
 248                         inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
 249                                 ~ICH2_SMI_EN_BIOS_EN);
 250                 return 0;
 251         default:
 252                 return -1;
 253         }
 254 }