[netwatch.git] / ich2 / smi.c

/* smi.c
 * System management interrupt dispatch routines for ICH2 southbridge
 * NetWatch system management mode administration console
 *
 * Copyright (c) 2008 Jacob Potter and Joshua Wise.  All rights reserved.
 * This program is free software; you can redistribute and/or modify it under
 * the terms found in the file LICENSE in the root of this source tree. 
 *
 */


#include <smi.h>
#include <pci.h>
#include <io.h>
#include <stdint.h>
#include <vga-overlay.h>
#include <reg-82801b.h>
#include <output.h>

static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};

static uint16_t _get_PMBASE()
{
	static long pmbase = -1;
	
	if (pmbase == -1)	/* Memoize it so that we don't have to hit PCI so often. */
		pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
	
	return pmbase;
}

void smi_disable()
{
	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
	outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
}

void smi_enable()
{
	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
	outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
}

unsigned long smi_status()
{
	unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
	return inl(smi_sts);
}

void smi_poll()
{
	unsigned long sts = smi_status();
	
	if (sts & ICH2_SMI_STS_BIOS_STS)
	{
		if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
			output("Unhandled: BIOS_STS");
		else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
			_handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
	}
	
	if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
	{
		output("Unhandled: LEGACY_USB_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
	}
	
	if (sts & ICH2_SMI_STS_SLP_SMI_STS)
	{
		output("Unhandled: SLP_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_APM_STS)
	{
		output("Unhandled: APM_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
	}
	
	if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)	// Ack it, then request another.
	{
		if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
			output("Unhandled: SWSMI_TMR_STS");
		else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
			_handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
	}
	
	if (sts & ICH2_SMI_STS_PM1_STS_REG)
	{
		unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
		unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
		
		pm1_sts &= pm1_en;
		if (pm1_sts & ICH2_PM1_STS_RTC_STS)
		{
			output("Unhandled: PM1_STS: RTC_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
		{
			output("Unhandled: PM1_STS: PWRBTN_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_GBL_STS)
		{
			output("Unhandled: PM1_STS: GBL_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
		{
			output("Unhandled: PM1_STS: TMROF_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
		}
		
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
	}
	
	if (sts & ICH2_SMI_STS_GPE0_STS)
	{
		/* XXX -- trawl through GPE0_STS to see what happened */
		output("XXX Unhandled: GPE0_STS (expect lockup)");
	}
	
	if (sts & ICH2_SMI_STS_GPE1_STS)
	{
		/* XXX -- trawl through GPE1_STS to see what happened */
		output("XXX Unhandled: GPE1_STS (expect lockup)");
	}
	
	if (sts & ICH2_SMI_STS_MCSMI_STS)
	{
		output("Unhandled: MCSMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_DEVMON_STS)
	{
		unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
		unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
		unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
		
		if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
		{
			if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
				output("Unhandled: DEVACT_KBC_ACT_STS");
			else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
				_handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
			outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
		}
		
		/* Refresh register cache so that we can print unhandleds as needed. */
		mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
		devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
		devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
		
		if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
			outputf("Unhandled: MON_SMI (%04x)", mon_smi);
		if (devact_sts & devtrap_en)
			outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
	}
	
	if (sts & ICH2_SMI_STS_TCO_STS)
	{
		output("Unhandled: TCO_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
	}
	
	if (sts & ICH2_SMI_STS_PERIODIC_STS)
	{
		output("Unhandled: PERIODIC_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
	}
	
	if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
	{
		output("Unhandled: SERIRQ_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
	{
		output("Unhandled: SMBUS_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
	}
	
	if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)	/* Either the chipset is buggy, or we are. */
		outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
	
	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
		inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
			ICH2_SMI_EN_EOS |
			ICH2_SMI_EN_GBL_SMI_EN);
}

int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
{
	if (ev >= SMI_EVENT_MAX)
		return -1;
	_handlers[ev] = hnd;
	return 0;
}

int smi_enable_event(smi_event_t ev)
{
	switch(ev)
	{
	case SMI_EVENT_FAST_TIMER:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
				ICH2_SMI_EN_SWSMI_TMR_EN);
		return 0;
	case SMI_EVENT_DEVTRAP_KBC:
		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
				ICH2_DEVTRAP_EN_KBC_TRP_EN);
		return 0;
	case SMI_EVENT_GBL_RLS:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
				ICH2_SMI_EN_BIOS_EN);
		return 0;
	default:
		return -1;
	}
}

int smi_disable_event(smi_event_t ev)
{
	switch(ev)
	{
	case SMI_EVENT_FAST_TIMER:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
				~ICH2_SMI_EN_SWSMI_TMR_EN);
		return 0;
	case SMI_EVENT_DEVTRAP_KBC:
		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
				~ICH2_DEVTRAP_EN_KBC_TRP_EN);
		return 0;
	case SMI_EVENT_GBL_RLS:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
				~ICH2_SMI_EN_BIOS_EN);
		return 0;
	default:
		return -1;
	}
}
Commit	Line	Data
f1584bb0 JW	1	/* smi.c
	2	* System management interrupt dispatch routines for ICH2 southbridge
	3	* NetWatch system management mode administration console
	4	*
	5	* Copyright (c) 2008 Jacob Potter and Joshua Wise. All rights reserved.
	6	* This program is free software; you can redistribute and/or modify it under
	7	* the terms found in the file LICENSE in the root of this source tree.
	8	*
	9	*/
	10
	11
85bc8ca6 JW	12	#include <smi.h>
	13	#include <pci.h>
	14	#include <io.h>
	15	#include <stdint.h>
4fb81ad0	16	#include <vga-overlay.h>
cc80dccf	17	#include <reg-82801b.h>
efea5b4e	18	#include <output.h>
85bc8ca6	19
07d1dd26 JW	20	static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
07d1dd26 JW	21
9cfcd0ca	22	static uint16_t _get_PMBASE()
85bc8ca6	23	{
199c2b1b JW	24	static long pmbase = -1;
	25
	26	if (pmbase == -1) /* Memoize it so that we don't have to hit PCI so often. */
	27	pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
	28
	29	return pmbase;
85bc8ca6 JW	30	}
	31
	32	void smi_disable()
	33	{
cc80dccf JW	34	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
cc80dccf JW	35	outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
85bc8ca6 JW	36	}
	37
	38	void smi_enable()
	39	{
cc80dccf JW	40	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
cc80dccf JW	41	outl(smi_en, inl(smi_en) \| ICH2_SMI_EN_GBL_SMI_EN);
85bc8ca6 JW	42	}
	43
	44	unsigned long smi_status()
	45	{
cc80dccf	46	unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
85bc8ca6 JW	47	return inl(smi_sts);
85bc8ca6 JW	48	}
d71d9872	49
4fb81ad0 JW	50	void smi_poll()
	51	{
	52	unsigned long sts = smi_status();
	53
	54	if (sts & ICH2_SMI_STS_BIOS_STS)
	55	{
73fb9b4c JW	56	if (_handlers[SMI_EVENT_GBL_RLS] == SMI_HANDLER_NONE)
	57	output("Unhandled: BIOS_STS");
	58	else if (_handlers[SMI_EVENT_GBL_RLS] != SMI_HANDLER_IGNORE)
	59	_handlers[SMI_EVENT_GBL_RLS](SMI_EVENT_GBL_RLS);
4fb81ad0 JW	60	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
	61	}
	62
	63	if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
	64	{
efea5b4e	65	output("Unhandled: LEGACY_USB_STS");
4fb81ad0 JW	66	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
	67	}
	68
	69	if (sts & ICH2_SMI_STS_SLP_SMI_STS)
	70	{
efea5b4e	71	output("Unhandled: SLP_SMI_STS");
4fb81ad0 JW	72	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
	73	}
	74
	75	if (sts & ICH2_SMI_STS_APM_STS)
	76	{
efea5b4e	77	output("Unhandled: APM_STS");
199c2b1b	78	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
4fb81ad0 JW	79	}
	80
	81	if (sts & ICH2_SMI_STS_SWSMI_TMR_STS) // Ack it, then request another.
	82	{
07d1dd26 JW	83	if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
	84	output("Unhandled: SWSMI_TMR_STS");
	85	else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
	86	_handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
199c2b1b	87	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
4fb81ad0 JW	88	}
	89
	90	if (sts & ICH2_SMI_STS_PM1_STS_REG)
	91	{
199c2b1b JW	92	unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
	93	unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
	94
	95	pm1_sts &= pm1_en;
	96	if (pm1_sts & ICH2_PM1_STS_RTC_STS)
	97	{
efea5b4e	98	output("Unhandled: PM1_STS: RTC_STS");
199c2b1b JW	99	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
	100	}
	101
	102	if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
	103	{
efea5b4e	104	output("Unhandled: PM1_STS: PWRBTN_STS");
199c2b1b JW	105	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
	106	}
	107
	108	if (pm1_sts & ICH2_PM1_STS_GBL_STS)
	109	{
efea5b4e	110	output("Unhandled: PM1_STS: GBL_STS");
199c2b1b JW	111	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
	112	}
	113
	114	if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
	115	{
efea5b4e	116	output("Unhandled: PM1_STS: TMROF_STS");
199c2b1b JW	117	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
	118	}
	119
	120	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
4fb81ad0 JW	121	}
	122
	123	if (sts & ICH2_SMI_STS_GPE0_STS)
	124	{
	125	/* XXX -- trawl through GPE0_STS to see what happened */
efea5b4e	126	output("XXX Unhandled: GPE0_STS (expect lockup)");
199c2b1b JW	127	}
	128
	129	if (sts & ICH2_SMI_STS_GPE1_STS)
	130	{
	131	/* XXX -- trawl through GPE1_STS to see what happened */
efea5b4e	132	output("XXX Unhandled: GPE1_STS (expect lockup)");
4fb81ad0 JW	133	}
	134
	135	if (sts & ICH2_SMI_STS_MCSMI_STS)
	136	{
efea5b4e	137	output("Unhandled: MCSMI_STS");
4fb81ad0 JW	138	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
	139	}
	140
	141	if (sts & ICH2_SMI_STS_DEVMON_STS)
	142	{
199c2b1b JW	143	unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
	144	unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
	145	unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
8a677ebb JW	146
	147	if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
	148	{
	149	if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
	150	output("Unhandled: DEVACT_KBC_ACT_STS");
	151	else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
	152	_handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
	153	outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
	154	}
	155
	156	/* Refresh register cache so that we can print unhandleds as needed. */
	157	mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
	158	devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
	159	devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
	160
199c2b1b	161	if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
efea5b4e	162	outputf("Unhandled: MON_SMI (%04x)", mon_smi);
199c2b1b	163	if (devact_sts & devtrap_en)
efea5b4e	164	outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
4fb81ad0 JW	165	}
	166
	167	if (sts & ICH2_SMI_STS_TCO_STS)
	168	{
efea5b4e	169	output("Unhandled: TCO_STS");
4fb81ad0 JW	170	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
	171	}
	172
	173	if (sts & ICH2_SMI_STS_PERIODIC_STS)
	174	{
efea5b4e	175	output("Unhandled: PERIODIC_STS");
4fb81ad0 JW	176	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
	177	}
	178
	179	if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
	180	{
efea5b4e	181	output("Unhandled: SERIRQ_SMI_STS");
4fb81ad0 JW	182	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
	183	}
	184
	185	if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
	186	{
efea5b4e	187	output("Unhandled: SMBUS_SMI_STS");
4fb81ad0 JW	188	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
	189	}
	190
199c2b1b	191	if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG) /* Either the chipset is buggy, or we are. */
efea5b4e	192	outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
4fb81ad0 JW	193
	194	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	195	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	196	ICH2_SMI_EN_EOS \|
	197	ICH2_SMI_EN_GBL_SMI_EN);
	198	}
07d1dd26 JW	199
	200	int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
	201	{
	202	if (ev >= SMI_EVENT_MAX)
	203	return -1;
	204	_handlers[ev] = hnd;
	205	return 0;
	206	}
	207
	208	int smi_enable_event(smi_event_t ev)
	209	{
	210	switch(ev)
	211	{
	212	case SMI_EVENT_FAST_TIMER:
	213	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	214	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	215	ICH2_SMI_EN_SWSMI_TMR_EN);
	216	return 0;
8a677ebb JW	217	case SMI_EVENT_DEVTRAP_KBC:
	218	outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
	219	inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) \|
	220	ICH2_DEVTRAP_EN_KBC_TRP_EN);
	221	return 0;
73fb9b4c JW	222	case SMI_EVENT_GBL_RLS:
	223	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	224	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	225	ICH2_SMI_EN_BIOS_EN);
	226	return 0;
07d1dd26 JW	227	default:
	228	return -1;
	229	}
	230	}
	231
	232	int smi_disable_event(smi_event_t ev)
	233	{
	234	switch(ev)
	235	{
	236	case SMI_EVENT_FAST_TIMER:
	237	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	238	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
	239	~ICH2_SMI_EN_SWSMI_TMR_EN);
	240	return 0;
8a677ebb JW	241	case SMI_EVENT_DEVTRAP_KBC:
	242	outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
	243	inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
	244	~ICH2_DEVTRAP_EN_KBC_TRP_EN);
	245	return 0;
73fb9b4c JW	246	case SMI_EVENT_GBL_RLS:
	247	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	248	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
	249	~ICH2_SMI_EN_BIOS_EN);
	250	return 0;
07d1dd26 JW	251	default:
	252	return -1;
	253	}
	254	}