[netwatch.git] / ich2 / smi.c

#include <smi.h>
#include <pci.h>
#include <io.h>
#include <stdint.h>
#include <vga-overlay.h>
#include <reg-82801b.h>
#include <output.h>

static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};

static uint16_t _get_PMBASE()
{
	static long pmbase = -1;
	
	if (pmbase == -1)	/* Memoize it so that we don't have to hit PCI so often. */
		pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
	
	return pmbase;
}

void smi_disable()
{
	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
	outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
}

void smi_enable()
{
	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
	outl(smi_en, inl(smi_en) | ICH2_SMI_EN_GBL_SMI_EN);
}

unsigned long smi_status()
{
	unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
	return inl(smi_sts);
}

void smi_poll()
{
	unsigned long sts = smi_status();
	
	if (sts & ICH2_SMI_STS_BIOS_STS)
	{
		output("Unhandled: BIOS_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
	}
	
	if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
	{
		output("Unhandled: LEGACY_USB_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
	}
	
	if (sts & ICH2_SMI_STS_SLP_SMI_STS)
	{
		output("Unhandled: SLP_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_APM_STS)
	{
		output("Unhandled: APM_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
	}
	
	if (sts & ICH2_SMI_STS_SWSMI_TMR_STS)	// Ack it, then request another.
	{
		if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
			output("Unhandled: SWSMI_TMR_STS");
		else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
			_handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
	}
	
	if (sts & ICH2_SMI_STS_PM1_STS_REG)
	{
		unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
		unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
		
		pm1_sts &= pm1_en;
		if (pm1_sts & ICH2_PM1_STS_RTC_STS)
		{
			output("Unhandled: PM1_STS: RTC_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
		{
			output("Unhandled: PM1_STS: PWRBTN_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_GBL_STS)
		{
			output("Unhandled: PM1_STS: GBL_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
		}
		
		if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
		{
			output("Unhandled: PM1_STS: TMROF_STS");
			outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
		}
		
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
	}
	
	if (sts & ICH2_SMI_STS_GPE0_STS)
	{
		/* XXX -- trawl through GPE0_STS to see what happened */
		output("XXX Unhandled: GPE0_STS (expect lockup)");
	}
	
	if (sts & ICH2_SMI_STS_GPE1_STS)
	{
		/* XXX -- trawl through GPE1_STS to see what happened */
		output("XXX Unhandled: GPE1_STS (expect lockup)");
	}
	
	if (sts & ICH2_SMI_STS_MCSMI_STS)
	{
		output("Unhandled: MCSMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_DEVMON_STS)
	{
		unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
		unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
		unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
		
		if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
		{
			if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
				output("Unhandled: DEVACT_KBC_ACT_STS");
			else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
				_handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
			outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
		}
		
		/* Refresh register cache so that we can print unhandleds as needed. */
		mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
		devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
		devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
		
		if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
			outputf("Unhandled: MON_SMI (%04x)", mon_smi);
		if (devact_sts & devtrap_en)
			outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
	}
	
	if (sts & ICH2_SMI_STS_TCO_STS)
	{
		output("Unhandled: TCO_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
	}
	
	if (sts & ICH2_SMI_STS_PERIODIC_STS)
	{
		output("Unhandled: PERIODIC_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
	}
	
	if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
	{
		output("Unhandled: SERIRQ_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
	}
	
	if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
	{
		output("Unhandled: SMBUS_SMI_STS");
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
	}
	
	if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG)	/* Either the chipset is buggy, or we are. */
		outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
	
	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
		inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
			ICH2_SMI_EN_EOS |
			ICH2_SMI_EN_GBL_SMI_EN);
}

int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
{
	if (ev >= SMI_EVENT_MAX)
		return -1;
	_handlers[ev] = hnd;
	return 0;
}

int smi_enable_event(smi_event_t ev)
{
	switch(ev)
	{
	case SMI_EVENT_FAST_TIMER:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) |
				ICH2_SMI_EN_SWSMI_TMR_EN);
		return 0;
	case SMI_EVENT_DEVTRAP_KBC:
		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) |
				ICH2_DEVTRAP_EN_KBC_TRP_EN);
		return 0;
	default:
		return -1;
	}
}

int smi_disable_event(smi_event_t ev)
{
	switch(ev)
	{
	case SMI_EVENT_FAST_TIMER:
		outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
				~ICH2_SMI_EN_SWSMI_TMR_EN);
		return 0;
	case SMI_EVENT_DEVTRAP_KBC:
		outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
			inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
				~ICH2_DEVTRAP_EN_KBC_TRP_EN);
		return 0;
	default:
		return -1;
	}
}
Commit	Line	Data
85bc8ca6 JW	1	#include <smi.h>
	2	#include <pci.h>
	3	#include <io.h>
	4	#include <stdint.h>
4fb81ad0	5	#include <vga-overlay.h>
cc80dccf	6	#include <reg-82801b.h>
efea5b4e	7	#include <output.h>
85bc8ca6	8
07d1dd26 JW	9	static smi_handler_t _handlers[SMI_EVENT_MAX] = {0};
07d1dd26 JW	10
9cfcd0ca	11	static uint16_t _get_PMBASE()
85bc8ca6	12	{
199c2b1b JW	13	static long pmbase = -1;
	14
	15	if (pmbase == -1) /* Memoize it so that we don't have to hit PCI so often. */
	16	pmbase = pci_read32(ICH2_LPC_BUS, ICH2_LPC_DEV, ICH2_LPC_FN, ICH2_LPC_PCI_PMBASE) & ICH2_PMBASE_MASK;
	17
	18	return pmbase;
85bc8ca6 JW	19	}
	20
	21	void smi_disable()
	22	{
cc80dccf JW	23	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
cc80dccf JW	24	outl(smi_en, inl(smi_en) & ~ICH2_SMI_EN_GBL_SMI_EN);
85bc8ca6 JW	25	}
	26
	27	void smi_enable()
	28	{
cc80dccf JW	29	unsigned short smi_en = _get_PMBASE() + ICH2_PMBASE_SMI_EN;
cc80dccf JW	30	outl(smi_en, inl(smi_en) \| ICH2_SMI_EN_GBL_SMI_EN);
85bc8ca6 JW	31	}
	32
	33	unsigned long smi_status()
	34	{
cc80dccf	35	unsigned short smi_sts = _get_PMBASE() + ICH2_PMBASE_SMI_STS;
85bc8ca6 JW	36	return inl(smi_sts);
85bc8ca6 JW	37	}
d71d9872	38
4fb81ad0 JW	39	void smi_poll()
	40	{
	41	unsigned long sts = smi_status();
	42
	43	if (sts & ICH2_SMI_STS_BIOS_STS)
	44	{
efea5b4e	45	output("Unhandled: BIOS_STS");
4fb81ad0 JW	46	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_BIOS_STS);
	47	}
	48
	49	if (sts & ICH2_SMI_STS_LEGACY_USB_STS)
	50	{
efea5b4e	51	output("Unhandled: LEGACY_USB_STS");
4fb81ad0 JW	52	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_LEGACY_USB_STS);
	53	}
	54
	55	if (sts & ICH2_SMI_STS_SLP_SMI_STS)
	56	{
efea5b4e	57	output("Unhandled: SLP_SMI_STS");
4fb81ad0 JW	58	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SLP_SMI_STS);
	59	}
	60
	61	if (sts & ICH2_SMI_STS_APM_STS)
	62	{
efea5b4e	63	output("Unhandled: APM_STS");
199c2b1b	64	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_APM_STS);
4fb81ad0 JW	65	}
	66
	67	if (sts & ICH2_SMI_STS_SWSMI_TMR_STS) // Ack it, then request another.
	68	{
07d1dd26 JW	69	if (_handlers[SMI_EVENT_FAST_TIMER] == SMI_HANDLER_NONE)
	70	output("Unhandled: SWSMI_TMR_STS");
	71	else if (_handlers[SMI_EVENT_FAST_TIMER] != SMI_HANDLER_IGNORE)
	72	_handlers[SMI_EVENT_FAST_TIMER](SMI_EVENT_FAST_TIMER);
199c2b1b	73	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SWSMI_TMR_STS);
4fb81ad0 JW	74	}
	75
	76	if (sts & ICH2_SMI_STS_PM1_STS_REG)
	77	{
199c2b1b JW	78	unsigned short pm1_sts = inw(_get_PMBASE() + ICH2_PMBASE_PM1_STS);
	79	unsigned short pm1_en = inw(_get_PMBASE() + ICH2_PMBASE_PM1_EN);
	80
	81	pm1_sts &= pm1_en;
	82	if (pm1_sts & ICH2_PM1_STS_RTC_STS)
	83	{
efea5b4e	84	output("Unhandled: PM1_STS: RTC_STS");
199c2b1b JW	85	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_RTC_STS);
	86	}
	87
	88	if (pm1_sts & ICH2_PM1_STS_PWRBTN_STS)
	89	{
efea5b4e	90	output("Unhandled: PM1_STS: PWRBTN_STS");
199c2b1b JW	91	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_PWRBTN_STS);
	92	}
	93
	94	if (pm1_sts & ICH2_PM1_STS_GBL_STS)
	95	{
efea5b4e	96	output("Unhandled: PM1_STS: GBL_STS");
199c2b1b JW	97	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_GBL_STS);
	98	}
	99
	100	if (pm1_sts & ICH2_PM1_STS_TMROF_STS)
	101	{
efea5b4e	102	output("Unhandled: PM1_STS: TMROF_STS");
199c2b1b JW	103	outw(_get_PMBASE() + ICH2_PMBASE_PM1_STS, ICH2_PM1_STS_TMROF_STS);
	104	}
	105
	106	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PM1_STS_REG);
4fb81ad0 JW	107	}
	108
	109	if (sts & ICH2_SMI_STS_GPE0_STS)
	110	{
	111	/* XXX -- trawl through GPE0_STS to see what happened */
efea5b4e	112	output("XXX Unhandled: GPE0_STS (expect lockup)");
199c2b1b JW	113	}
	114
	115	if (sts & ICH2_SMI_STS_GPE1_STS)
	116	{
	117	/* XXX -- trawl through GPE1_STS to see what happened */
efea5b4e	118	output("XXX Unhandled: GPE1_STS (expect lockup)");
4fb81ad0 JW	119	}
	120
	121	if (sts & ICH2_SMI_STS_MCSMI_STS)
	122	{
efea5b4e	123	output("Unhandled: MCSMI_STS");
4fb81ad0 JW	124	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_MCSMI_STS);
	125	}
	126
	127	if (sts & ICH2_SMI_STS_DEVMON_STS)
	128	{
199c2b1b JW	129	unsigned short mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
	130	unsigned long devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
	131	unsigned long devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
8a677ebb JW	132
	133	if (devact_sts & ICH2_DEVACT_STS_KBC_ACT_STS)
	134	{
	135	if (_handlers[SMI_EVENT_DEVTRAP_KBC] == SMI_HANDLER_NONE)
	136	output("Unhandled: DEVACT_KBC_ACT_STS");
	137	else if (_handlers[SMI_EVENT_DEVTRAP_KBC] != SMI_HANDLER_IGNORE)
	138	_handlers[SMI_EVENT_DEVTRAP_KBC](SMI_EVENT_DEVTRAP_KBC);
	139	outl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS, ICH2_DEVACT_STS_KBC_ACT_STS);
	140	}
	141
	142	/* Refresh register cache so that we can print unhandleds as needed. */
	143	mon_smi = inw(_get_PMBASE() + ICH2_PMBASE_MON_SMI);
	144	devact_sts = inl(_get_PMBASE() + ICH2_PMBASE_DEVACT_STS);
	145	devtrap_en = inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN);
	146
199c2b1b	147	if (((mon_smi & 0x0F00) >> 8) & ((mon_smi & 0xF000) >> 12))
efea5b4e	148	outputf("Unhandled: MON_SMI (%04x)", mon_smi);
199c2b1b	149	if (devact_sts & devtrap_en)
efea5b4e	150	outputf("Unhandled: DEVTRAP (%08x)", devact_sts & devtrap_en);
4fb81ad0 JW	151	}
	152
	153	if (sts & ICH2_SMI_STS_TCO_STS)
	154	{
efea5b4e	155	output("Unhandled: TCO_STS");
4fb81ad0 JW	156	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_TCO_STS);
	157	}
	158
	159	if (sts & ICH2_SMI_STS_PERIODIC_STS)
	160	{
efea5b4e	161	output("Unhandled: PERIODIC_STS");
4fb81ad0 JW	162	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_PERIODIC_STS);
	163	}
	164
	165	if (sts & ICH2_SMI_STS_SERIRQ_SMI_STS)
	166	{
efea5b4e	167	output("Unhandled: SERIRQ_SMI_STS");
4fb81ad0 JW	168	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SERIRQ_SMI_STS);
	169	}
	170
	171	if (sts & ICH2_SMI_STS_SMBUS_SMI_STS)
	172	{
efea5b4e	173	output("Unhandled: SMBUS_SMI_STS");
4fb81ad0 JW	174	outl(_get_PMBASE() + ICH2_PMBASE_SMI_STS, ICH2_SMI_STS_SMBUS_SMI_STS);
	175	}
	176
199c2b1b	177	if (smi_status() & ~ICH2_SMI_STS_PM1_STS_REG) /* Either the chipset is buggy, or we are. */
efea5b4e	178	outputf("WARN: couldn't clear SMI_STS! (%08x)", smi_status());
4fb81ad0 JW	179
	180	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	181	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	182	ICH2_SMI_EN_EOS \|
	183	ICH2_SMI_EN_GBL_SMI_EN);
	184	}
07d1dd26 JW	185
	186	int smi_register_handler(smi_event_t ev, smi_handler_t hnd)
	187	{
	188	if (ev >= SMI_EVENT_MAX)
	189	return -1;
	190	_handlers[ev] = hnd;
	191	return 0;
	192	}
	193
	194	int smi_enable_event(smi_event_t ev)
	195	{
	196	switch(ev)
	197	{
	198	case SMI_EVENT_FAST_TIMER:
	199	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	200	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) \|
	201	ICH2_SMI_EN_SWSMI_TMR_EN);
	202	return 0;
8a677ebb JW	203	case SMI_EVENT_DEVTRAP_KBC:
	204	outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
	205	inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) \|
	206	ICH2_DEVTRAP_EN_KBC_TRP_EN);
	207	return 0;
07d1dd26 JW	208	default:
	209	return -1;
	210	}
	211	}
	212
	213	int smi_disable_event(smi_event_t ev)
	214	{
	215	switch(ev)
	216	{
	217	case SMI_EVENT_FAST_TIMER:
	218	outl(_get_PMBASE() + ICH2_PMBASE_SMI_EN,
	219	inl(_get_PMBASE() + ICH2_PMBASE_SMI_EN) &
	220	~ICH2_SMI_EN_SWSMI_TMR_EN);
	221	return 0;
8a677ebb JW	222	case SMI_EVENT_DEVTRAP_KBC:
	223	outl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN,
	224	inl(_get_PMBASE() + ICH2_PMBASE_DEVTRAP_EN) &
	225	~ICH2_DEVTRAP_EN_KBC_TRP_EN);
	226	return 0;
07d1dd26 JW	227	default:
	228	return -1;
	229	}
	230	}