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Be more quiet about this whole transmit and receive business. This time, we actually...
[netwatch.git] / net / 3c90x.c
CommitLineData
748534f4
JP		 1/*
2 * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
3 * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
4 * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
5 *
6 * This program Copyright (C) 1999 LightSys Technology Services, Inc.
7 * Portions Copyright (C) 1999 Steve Smith
8 *
9 * This program may be re-distributed in source or binary form, modified,
10 * sold, or copied for any purpose, provided that the above copyright message
11 * and this text are included with all source copies or derivative works, and
12 * provided that the above copyright message and this text are included in the
13 * documentation of any binary-only distributions. This program is distributed
14 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
15 * PURPOSE or MERCHANTABILITY. Please read the associated documentation
16 * "3c90x.txt" before compiling and using this driver.
17 *
18 * --------
19 *
20 * Program written with the assistance of the 3com documentation for
21 * the 3c905B-TX card, as well as with some assistance from the 3c59x
22 * driver Donald Becker wrote for the Linux kernel, and with some assistance
23 * from the remainder of the Etherboot distribution.
24 *
25 * REVISION HISTORY:
26 *
27 * v0.10 1-26-1998 GRB Initial implementation.
28 * v0.90 1-27-1998 GRB System works.
29 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31 * Re-wrote poll and transmit for
32 * better error recovery and heavy
33 * network traffic operation
34 * v2.01 5-26-2003 NN Fixed driver alignment issue which
35 * caused system lockups if driver structures
36 * not 8-byte aligned.
37 *
38 */
39
40#include "etherboot-compat.h"
42125f27 41#include "net.h"
748534f4
JP		 42#include <timer.h>
43#include <io.h>
44#include <pci.h>
7a914840 45#include <pci-bother.h>
748534f4
JP		 46#include <minilib.h>
47#include <output.h>
68beefa8 48#include <paging.h>
748534f4
JP		 49
50#define XCVR_MAGIC (0x5A00)
51/** any single transmission fails after 16 collisions or other errors
52 ** this is the number of times to retry the transmission -- this should
53 ** be plenty
54 **/
c25f3f39 55#define XMIT_RETRIES 5
748534f4
JP		 56
57/*** Register definitions for the 3c905 ***/
58enum Registers
59 {
60 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
61 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
62 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
63 regDebugControl_w = 0x74, /** 905B Revision Only **/
64 regDebugData_l = 0x70, /** 905B Revision Only **/
65 regRealTimeCnt_l = 0x40, /** Universal **/
66 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
67 regUpPoll_b = 0x3d, /** 905B Revision Only **/
68 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
69 regUpListPtr_l = 0x38, /** Universal **/
70 regCountdown_w = 0x36, /** Universal **/
71 regFreeTimer_w = 0x34, /** Universal **/
72 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
73 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
74 regDnPoll_b = 0x2d, /** 905B Revision Only **/
75 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
76 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
77 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
78 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
79 /** **/
80 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
81 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
82 regTimer_b = 0x1a, /** Universal **/
83 regTxPktId_b = 0x18, /** 905B Revision Only **/
84 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
85 };
86
87/** following are windowed registers **/
88enum Registers7
89 {
90 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
91 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
92 regVlanMask_7_w = 0x00, /** 905B Revision Only **/
93 };
94
95enum Registers6
96 {
97 regBytesXmittedOk_6_w = 0x0c, /** Universal **/
98 regBytesRcvdOk_6_w = 0x0a, /** Universal **/
99 regUpperFramesOk_6_b = 0x09, /** Universal **/
100 regFramesDeferred_6_b = 0x08, /** Universal **/
101 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
102 regFramesXmittedOk_6_b = 0x06, /** Universal **/
103 regRxOverruns_6_b = 0x05, /** Universal **/
104 regLateCollisions_6_b = 0x04, /** Universal **/
105 regSingleCollisions_6_b = 0x03, /** Universal **/
106 regMultipleCollisions_6_b = 0x02, /** Universal **/
107 regSqeErrors_6_b = 0x01, /** Universal **/
108 regCarrierLost_6_b = 0x00, /** Universal **/
109 };
110
111enum Registers5
112 {
113 regIndicationEnable_5_w = 0x0c, /** Universal **/
114 regInterruptEnable_5_w = 0x0a, /** Universal **/
115 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
116 regRxFilter_5_b = 0x08, /** Universal **/
117 regRxEarlyThresh_5_w = 0x06, /** Universal **/
118 regTxStartThresh_5_w = 0x00, /** Universal **/
119 };
120
121enum Registers4
122 {
123 regUpperBytesOk_4_b = 0x0d, /** Universal **/
124 regBadSSD_4_b = 0x0c, /** Universal **/
125 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
126 regPhysicalMgmt_4_w = 0x08, /** Universal **/
127 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
128 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
129 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
130 };
131
132enum Registers3
133 {
134 regTxFree_3_w = 0x0c, /** Universal **/
135 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
136 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
137 /** Reset Options on Non-B Revision **/
138 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
139 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
140 regInternalConfig_3_l = 0x00, /** Universal, different bit **/
141 /** definitions, pg 59 **/
142 };
143
144enum Registers2
145 {
146 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
147 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
148 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
149 };
150
151enum Registers1
152 {
153 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
154 };
155
156enum Registers0
157 {
158 regEepromData_0_w = 0x0c, /** Universal **/
159 regEepromCommand_0_w = 0x0a, /** Universal **/
160 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
161 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
162 };
163
164
165/*** The names for the eight register windows ***/
166enum Windows
167 {
168 winPowerVlan7 = 0x07,
169 winStatistics6 = 0x06,
170 winTxRxControl5 = 0x05,
171 winDiagnostics4 = 0x04,
172 winTxRxOptions3 = 0x03,
173 winAddressing2 = 0x02,
174 winUnused1 = 0x01,
175 winEepromBios0 = 0x00,
176 };
177
178
179/*** Command definitions for the 3c90X ***/
180enum Commands
181 {
182 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
183 cmdSelectRegisterWindow = 0x01, /** Universal **/
184 cmdEnableDcConverter = 0x02, /** **/
185 cmdRxDisable = 0x03, /** **/
186 cmdRxEnable = 0x04, /** Universal **/
187 cmdRxReset = 0x05, /** Universal **/
188 cmdStallCtl = 0x06, /** Universal **/
189 cmdTxEnable = 0x09, /** Universal **/
190 cmdTxDisable = 0x0A, /** **/
191 cmdTxReset = 0x0B, /** Universal **/
192 cmdRequestInterrupt = 0x0C, /** **/
193 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
194 cmdSetInterruptEnable = 0x0E, /** Universal **/
195 cmdSetIndicationEnable = 0x0F, /** Universal **/
196 cmdSetRxFilter = 0x10, /** Universal **/
197 cmdSetRxEarlyThresh = 0x11, /** **/
198 cmdSetTxStartThresh = 0x13, /** **/
199 cmdStatisticsEnable = 0x15, /** **/
200 cmdStatisticsDisable = 0x16, /** **/
201 cmdDisableDcConverter = 0x17, /** **/
202 cmdSetTxReclaimThresh = 0x18, /** **/
203 cmdSetHashFilterBit = 0x19, /** **/
204 };
205
206
207/*** Values for int status register bitmask **/
208#define INT_INTERRUPTLATCH (1<<0)
209#define INT_HOSTERROR (1<<1)
210#define INT_TXCOMPLETE (1<<2)
211#define INT_RXCOMPLETE (1<<4)
212#define INT_RXEARLY (1<<5)
213#define INT_INTREQUESTED (1<<6)
214#define INT_UPDATESTATS (1<<7)
215#define INT_LINKEVENT (1<<8)
216#define INT_DNCOMPLETE (1<<9)
217#define INT_UPCOMPLETE (1<<10)
218#define INT_CMDINPROGRESS (1<<12)
219#define INT_WINDOWNUMBER (7<<13)
220
9c86d6da
JW		 221/* These structures are all 64-bit aligned, as needed for bus-mastering I/O. */
222typedef struct {
223 unsigned int addr;
224 unsigned int len;
225} segment_t __attribute__ ((aligned(8)));
226
227typedef struct {
228 unsigned int next;
229 unsigned int hdr;
230 segment_t segments[64 /* XXX magic */];
231} txdesc_t __attribute__ ((aligned(8)));
748534f4
JP		 232
233/*** RX descriptor ***/
9c86d6da
JW		 234typedef struct {
235 unsigned int next;
236 unsigned int status;
237 segment_t segments[64];
238} rxdesc_t __attribute__ ((aligned(8)));
748534f4
JP		 239
240/*** Global variables ***/
241static struct
242 {
243 unsigned int is3c556;
244 unsigned char isBrev;
245 unsigned char CurrentWindow;
246 unsigned int IOAddr;
247 unsigned char HWAddr[ETH_ALEN];
748534f4
JP		 248 }
249 INF_3C90X;
9c86d6da 250
7a914840 251static struct nic nic;
9c86d6da
JW		 252static txdesc_t txdesc;
253static rxdesc_t rxdesc;
80c7c8bf 254static struct pbuf *currecv;
9c86d6da 255
748534f4 256
c2e34447
JW		 257#define _outl(v,a) outl((a),(v))
258#define _outw(v,a) outw((a),(v))
259#define _outb(v,a) outb((a),(v))
748534f4 260
31ddf9b3
JW		 261static int _issue_command(int ioaddr, int cmd, int param)
262{
263 outw(ioaddr + regCommandIntStatus_w, (cmd << 11) | param);
748534f4 264
31ddf9b3
JW		 265 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
266 ;
748534f4 267
31ddf9b3
JW		 268 return 0;
269}
748534f4
JP		 270
271
272/*** a3c90x_internal_SetWindow: selects a register window set.
273 ***/
31ddf9b3
JW		 274static int _set_window(int ioaddr, int window)
275{
276 if (INF_3C90X.CurrentWindow == window)
277 return 0;
748534f4 278
31ddf9b3 279 _issue_command(ioaddr, cmdSelectRegisterWindow, window);
748534f4
JP		 280 INF_3C90X.CurrentWindow = window;
281
31ddf9b3
JW		 282 return 0;
283}
748534f4
JP		 284
285
286/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
287 ***/
288static unsigned short
289a3c90x_internal_ReadEeprom(int ioaddr, int address)
c2e34447
JW		 290{
291 unsigned short val;
748534f4
JP		 292
293 /** Select correct window **/
31ddf9b3 294 _set_window(INF_3C90X.IOAddr, winEepromBios0);
748534f4
JP		 295
296 /** Make sure the eeprom isn't busy **/
c2e34447
JW		 297 do
298 {
299 int i;
300 for (i = 0; i < 165; i++)
301 inb(0x80); /* wait 165 usec */
302 }
303 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
748534f4
JP		 304
305 /** Read the value. **/
306 if (INF_3C90X.is3c556)
c2e34447 307 _outw(address + (0x230), ioaddr + regEepromCommand_0_w);
748534f4 308 else
c2e34447 309 _outw(address + 0x80, ioaddr + regEepromCommand_0_w);
748534f4 310
c2e34447
JW		 311 do
312 {
313 int i;
314 for (i = 0; i < 165; i++)
315 inb(0x80); /* wait 165 usec */
316 }
317 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
318 val = inw(ioaddr + regEepromData_0_w);
319
320 return val;
321}
748534f4
JP		 322
323
324#ifdef CFG_3C90X_BOOTROM_FIX
325/*** a3c90x_internal_WriteEepromWord - write a physical word of
326 *** data to the onboard serial eeprom (not the BIOS prom, but the
327 *** nvram in the card that stores, among other things, the MAC
328 *** address).
329 ***/
330static int
331a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
332 {
333 /** Select register window **/
31ddf9b3 334 _set_window(ioaddr, winEepromBios0);
748534f4
JP		 335
336 /** Verify Eeprom not busy **/
337 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
338
339 /** Issue WriteEnable, and wait for completion. **/
c2e34447 340 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 341 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
342
343 /** Issue EraseRegister, and wait for completion. **/
c2e34447 344 _outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 345 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
346
347 /** Send the new data to the eeprom, and wait for completion. **/
c2e34447
JW		 348 _outw(value, ioaddr + regEepromData_0_w);
349 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 350 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
351
352 /** Burn the new data into the eeprom, and wait for completion. **/
c2e34447 353 _outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 354 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
355
356 return 0;
357 }
358#endif
359
360#ifdef CFG_3C90X_BOOTROM_FIX
361/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
362 *** and re-compute the eeprom checksum.
363 ***/
364static int
365a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
366 {
367 int cksum = 0,v;
368 int i;
369 int maxAddress, cksumAddress;
370
371 if (INF_3C90X.isBrev)
372 {
373 maxAddress=0x1f;
374 cksumAddress=0x20;
375 }
376 else
377 {
378 maxAddress=0x16;
379 cksumAddress=0x17;
380 }
381
382 /** Write the value. **/
383 if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
384 return -1;
385
386 /** Recompute the checksum. **/
387 for(i=0;i<=maxAddress;i++)
388 {
389 v = a3c90x_internal_ReadEeprom(ioaddr, i);
390 cksum ^= (v & 0xFF);
391 cksum ^= ((v>>8) & 0xFF);
392 }
393 /** Write the checksum to the location in the eeprom **/
394 if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
395 return -1;
396
397 return 0;
398 }
399#endif
400
401/*** a3c90x_reset: exported function that resets the card to its default
402 *** state. This is so the Linux driver can re-set the card up the way
403 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
404 *** not alter the selected transceiver that we used to download the boot
405 *** image.
406 ***/
407static void a3c90x_reset(void)
408 {
748534f4 409 /** Send the reset command to the card **/
99182958 410 outputf("3c90x: issuing RESET");
31ddf9b3 411 _issue_command(INF_3C90X.IOAddr, cmdGlobalReset, 0);
748534f4
JP		 412
413 /** global reset command resets station mask, non-B revision cards
414 ** require explicit reset of values
415 **/
31ddf9b3 416 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 417 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
418 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
419 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4 420
748534f4 421 /** Issue transmit reset, wait for command completion **/
31ddf9b3 422 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 423 if (! INF_3C90X.isBrev)
c2e34447 424 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
31ddf9b3 425 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 426
427 /**
428 ** reset of the receiver on B-revision cards re-negotiates the link
429 ** takes several seconds (a computer eternity)
430 **/
431 if (INF_3C90X.isBrev)
31ddf9b3 432 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 433 else
31ddf9b3
JW		 434 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
435 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
436 ;
437 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4 438
31ddf9b3 439 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
748534f4 440 /** enable rxComplete and txComplete **/
31ddf9b3 441 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
748534f4 442 /** acknowledge any pending status flags **/
31ddf9b3 443 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 444
445 return;
446 }
447
448
449
450/*** a3c90x_transmit: exported function that transmits a packet. Does not
451 *** return any particular status. Parameters are:
452 *** dest_addr[6] - destination address, ethernet;
453 *** proto - protocol type (ARP, IP, etc);
454 *** size - size of the non-header part of the packet that needs transmitted;
455 *** pkt - the pointer to the packet data itself.
456 ***/
bc9e1044 457static void _transmit(struct pbuf *p)
31ddf9b3 458{
31ddf9b3 459 unsigned char status;
057f0bb9 460 static struct pbuf *oldpbuf = NULL;
54d4b877 461 unsigned int n, len;
f8903fdd 462
057f0bb9 463 if (oldpbuf)
f8903fdd
JW		 464 {
465 while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE) && oneshot_running())
466 ;
467 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE))
468 {
469 outputf("3c90x: tx timeout? txstat %02x", inb(INF_3C90X.IOAddr + regTxStatus_b));
470 outputf("3c90x: Gen sts %04x", inw(INF_3C90X.IOAddr + regCommandIntStatus_w));
471 }
472 status = inb(INF_3C90X.IOAddr + regTxStatus_b);
473 outb(INF_3C90X.IOAddr + regTxStatus_b, 0x00);
057f0bb9
JW		 474 pbuf_free(oldpbuf);
475 oldpbuf = NULL;
f8903fdd 476 }
3dd054cf 477
037ce545
JW		 478 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 2 /* Stall download */);
479
480 /** Setup the DPD (download descriptor) **/
9c86d6da 481 txdesc.next = 0;
54d4b877
JW		 482 len = 0;
483 n = 0;
057f0bb9 484 oldpbuf = p;
54d4b877
JW		 485 for (; p; p = p->next)
486 {
9c86d6da
JW		 487 txdesc.segments[n].addr = v2p(p->payload);
488 txdesc.segments[n].len = p->len | (p->next ? 0 : (1 << 31));
54d4b877 489 len += p->len;
057f0bb9 490 pbuf_ref(p);
54d4b877
JW		 491 n++;
492 }
037ce545 493 /** set notification for transmission completion (bit 15) **/
9c86d6da 494 txdesc.hdr = (len) | 0x8000;
037ce545
JW		 495
496 /** Send the packet **/
9c86d6da 497 outl(INF_3C90X.IOAddr + regDnListPtr_l, v2p(&txdesc));
037ce545 498 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 3 /* Unstall download */);
31ddf9b3 499
037ce545
JW		 500 oneshot_start_ms(10);
501 while((inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0) && oneshot_running())
502 ;
503 if (!oneshot_running())
504 {
505 outputf("3c90x: Download engine pointer timeout");
506 return;
507 }
3dd054cf 508
3dd054cf 509#if 0
037ce545
JW		 510 /** successful completion (sans "interrupt Requested" bit) **/
511 if ((status & 0xbf) == 0x80)
512 return;
31ddf9b3 513
037ce545
JW		 514 outputf("3c90x: Status (%hhX)", status);
515 /** check error codes **/
516 if (status & 0x02)
517 {
518 outputf("3c90x: Tx Reclaim Error (%hhX)", status);
519 a3c90x_reset();
520 } else if (status & 0x04) {
521 outputf("3c90x: Tx Status Overflow (%hhX)", status);
522 for (i=0; i<32; i++)
523 _outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
524 /** must re-enable after max collisions before re-issuing tx **/
525 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
526 } else if (status & 0x08) {
527 outputf("3c90x: Tx Max Collisions (%hhX)", status);
528 /** must re-enable after max collisions before re-issuing tx **/
529 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
530 } else if (status & 0x10) {
531 outputf("3c90x: Tx Underrun (%hhX)", status);
532 a3c90x_reset();
533 } else if (status & 0x20) {
534 outputf("3c90x: Tx Jabber (%hhX)", status);
535 a3c90x_reset();
536 } else if ((status & 0x80) != 0x80) {
537 outputf("3c90x: Internal Error - Incomplete Transmission (%hhX)", status);
538 a3c90x_reset();
748534f4 539 }
037ce545 540#endif
31ddf9b3 541}
748534f4 542
80c7c8bf
JW		 543/* _setup_recv allocates and sets a pbuf from lwIP as the active receive
544 * packet chain for the 3c90x. The 3c90x must not be trying to receive
545 * when _setup_recv is being called.
546 */
547static void _setup_recv(struct nic *nic)
9c86d6da 548{
9c86d6da 549 struct pbuf *p, *q;
80c7c8bf 550 int i;
9c86d6da 551
80c7c8bf 552 rxdesc.status = 0; /* Clear it out in the very beginning. */
9c86d6da
JW		 553
554 p = pbuf_alloc(PBUF_RAW, 1536 /* XXX magic Max len */, PBUF_POOL);
555 if (!p)
748534f4 556 {
9c86d6da 557 outputf("3c90x: out of memory for packet?");
80c7c8bf
JW		 558 currecv = p;
559 return;
748534f4 560 }
80c7c8bf 561
9c86d6da
JW		 562 rxdesc.next = 0;
563 rxdesc.status = 0;
564 for (i = 0, q = p; q; q = q->next, i++)
748534f4 565 {
9c86d6da
JW		 566 rxdesc.segments[i].addr = v2p(q->payload);
567 rxdesc.segments[i].len = q->len | (q->next ? 0 : (1 << 31));
748534f4 568 }
80c7c8bf 569
9c86d6da 570 outl(INF_3C90X.IOAddr + regUpListPtr_l, v2p(&rxdesc));
80c7c8bf
JW		 571
572 currecv = p;
573}
748534f4 574
80c7c8bf
JW		 575/*** a3c90x_poll: exported routine that waits for a certain length of time
576 *** for a packet, and if it sees none, returns 0. This routine should
577 *** copy the packet to nic->packet if it gets a packet and set the size
578 *** in nic->packetlen. Return 1 if a packet was found.
579 ***/
bc9e1044 580static struct pbuf * _recv(struct nic *nic)
80c7c8bf
JW		 581{
582 int errcode;
583 struct pbuf *p;
584
585 if (!currecv)
586 _setup_recv(nic);
587
588 /* Nothing to do? */
589 if ((rxdesc.status & ((1<<14) | (1<<15))) == 0)
590 return NULL;
591
592 p = currecv;
593
9c86d6da
JW		 594 /** Check for Error (else we have good packet) **/
595 if (rxdesc.status & (1<<14))
596 {
597 errcode = rxdesc.status;
598 if (errcode & (1<<16))
599 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);
600 else if (errcode & (1<<17))
601 outputf("3C90X: Runt Frame (%hX)",errcode>>16);
602 else if (errcode & (1<<18))
603 outputf("3C90X: Alignment Error (%hX)",errcode>>16);
604 else if (errcode & (1<<19))
605 outputf("3C90X: CRC Error (%hX)",errcode>>16);
606 else if (errcode & (1<<20))
607 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);
608 else
609 outputf("3C90X: Packet error (%hX)",errcode>>16);
80c7c8bf
JW		 610
611 pbuf_free(p); /* Bounce the old one before setting it up again. */
612 _setup_recv(nic);
9c86d6da
JW		 613 return NULL;
614 }
748534f4 615
80c7c8bf
JW		 616 pbuf_realloc(p, rxdesc.status & 0x1FFF); /* Resize the packet to how large it actually is. */
617 _setup_recv(nic); /* ..and light the NIC up again. */
9c86d6da
JW		 618
619 return p;
620}
748534f4
JP		 621
622/*** a3c90x_disable: exported routine to disable the card. What's this for?
623 *** the eepro100.c driver didn't have one, so I just left this one empty too.
624 *** Ideas anyone?
625 *** Must turn off receiver at least so stray packets will not corrupt memory
626 *** [Ken]
627 ***/
628void a3c90x_disable(struct dev *dev)
629{
630 /* reset and disable merge */
631 a3c90x_reset();
632 /* Disable the receiver and transmitter. */
c2e34447
JW		 633 _outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
634 _outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
748534f4
JP		 635}
636
637
638/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
639 *** initialization. If this routine is called, the pci functions did find the
640 *** card. We just have to init it here.
641 ***/
642static int a3c90x_probe(struct pci_dev * pci, void * data)
643{
748534f4
JP		 644 INF_3C90X.is3c556 = (pci->did == 0x6055);
645
646 int i, c;
c2e34447 647 unsigned short eeprom[0x100];
748534f4
JP		 648 unsigned int cfg;
649 unsigned int mopt;
650 unsigned int mstat;
651 unsigned short linktype;
652#define HWADDR_OFFSET 10
653
654 unsigned long ioaddr = 0;
655 for (i = 0; i < 6; i++) {
656 if (pci->bars[i].type == PCI_BAR_IO) {
657 ioaddr = pci->bars[i].addr;
658 break;
659 }
660 }
661
662 if (ioaddr == 0)
c2e34447
JW		 663 {
664 outputf("3c90x: Unable to find I/O address");
665 return 0;
666 }
667
668 /* Power it on */
669 pci_write16(pci->bus, pci->dev, pci->fn, 0xE0,
670 pci_read16(pci->bus, pci->dev, pci->fn, 0xE0) & ~0x3);
671
672 outputf("3c90x: Picked I/O address %04x", ioaddr);
047916ed 673 pci_bother_add(pci);
42125f27
JP		 674 nic.ioaddr = ioaddr & ~3;
675 nic.irqno = 0;
748534f4 676
c2e34447 677 INF_3C90X.IOAddr = ioaddr;
748534f4
JP		 678 INF_3C90X.CurrentWindow = 255;
679 switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
680 {
681 case 0x9000: /** 10 Base TPO **/
682 case 0x9001: /** 10/100 T4 **/
683 case 0x9050: /** 10/100 TPO **/
684 case 0x9051: /** 10 Base Combo **/
685 INF_3C90X.isBrev = 0;
686 break;
687
688 case 0x9004: /** 10 Base TPO **/
689 case 0x9005: /** 10 Base Combo **/
690 case 0x9006: /** 10 Base TPO and Base2 **/
691 case 0x900A: /** 10 Base FL **/
692 case 0x9055: /** 10/100 TPO **/
693 case 0x9056: /** 10/100 T4 **/
694 case 0x905A: /** 10 Base FX **/
695 default:
696 INF_3C90X.isBrev = 1;
697 break;
698 }
699
700 /** Load the EEPROM contents **/
701 if (INF_3C90X.isBrev)
702 {
c2e34447 703 for(i=0;i<=/*0x20*/0x7F;i++)
748534f4
JP		 704 {
705 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
706 }
707
708#ifdef CFG_3C90X_BOOTROM_FIX
709 /** Set xcvrSelect in InternalConfig in eeprom. **/
710 /* only necessary for 3c905b revision cards with boot PROM bug!!! */
711 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
712#endif
713
714#ifdef CFG_3C90X_XCVR
715 if (CFG_3C90X_XCVR == 255)
716 {
717 /** Clear the LanWorks register **/
718 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
719 }
720 else
721 {
722 /** Set the selected permanent-xcvrSelect in the
723 ** LanWorks register
724 **/
725 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
726 XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
727 }
728#endif
729 }
730 else
731 {
c2e34447 732 for(i=0;i<=/*0x17*/0x7F;i++)
748534f4
JP		 733 {
734 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
735 }
736 }
737
738 /** Print identification message **/
739#ifdef CFG_3C90X_BOOTROM_FIX
740 if (INF_3C90X.isBrev)
741 {
742 outputf("NOTE: 3c905b bootrom fix enabled; has side "
743 "effects. See 3c90x.txt for info.");
744 }
745#endif
746
747 /** Retrieve the Hardware address and print it on the screen. **/
748 INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
749 INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
750 INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
751 INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
752 INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
753 INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
c2e34447
JW		 754 outputf("MAC Address = %02x:%02x:%02x:%02x:%02x:%02x",
755 INF_3C90X.HWAddr[0],
756 INF_3C90X.HWAddr[1],
757 INF_3C90X.HWAddr[2],
758 INF_3C90X.HWAddr[3],
759 INF_3C90X.HWAddr[4],
760 INF_3C90X.HWAddr[5]);
748534f4
JP		 761
762 /** 3C556: Invert MII power **/
763 if (INF_3C90X.is3c556) {
764 unsigned int tmp;
31ddf9b3 765 _set_window(INF_3C90X.IOAddr, winAddressing2);
748534f4
JP		 766 tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
767 tmp |= 0x4000;
c2e34447 768 _outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
748534f4
JP		 769 }
770
771 /* Test if the link is good, if not continue */
31ddf9b3 772 _set_window(INF_3C90X.IOAddr, winDiagnostics4);
748534f4
JP		 773 mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
774 if((mstat & (1<<11)) == 0) {
775 outputf("Valid link not established");
776 return 0;
777 }
778
779 /** Program the MAC address into the station address registers **/
31ddf9b3 780 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 781 _outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
782 _outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
783 _outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
784 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
785 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
786 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 787
788 /** Fill in our entry in the etherboot arp table **/
789/* XXX ? for lwip?
790 for(i=0;i<ETH_ALEN;i++)
42125f27 791 nic.node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
748534f4
JP		 792*/
793
794 /** Read the media options register, print a message and set default
795 ** xcvr.
796 **
797 ** Uses Media Option command on B revision, Reset Option on non-B
798 ** revision cards -- same register address
799 **/
31ddf9b3 800 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 801 mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
802
803 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
804 if (! INF_3C90X.isBrev)
805 {
806 mopt &= 0x7F;
807 }
808
809 outputf("Connectors present: ");
810 c = 0;
811 linktype = 0x0008;
812 if (mopt & 0x01)
813 {
80c7c8bf 814 outputf(" 100Base-T4");
748534f4
JP		 815 linktype = 0x0006;
816 }
817 if (mopt & 0x04)
818 {
80c7c8bf 819 outputf(" 100Base-FX");
748534f4
JP		 820 linktype = 0x0005;
821 }
822 if (mopt & 0x10)
823 {
80c7c8bf 824 outputf(" 10Base-2");
748534f4
JP		 825 linktype = 0x0003;
826 }
827 if (mopt & 0x20)
828 {
80c7c8bf 829 outputf(" AUI");
748534f4
JP		 830 linktype = 0x0001;
831 }
832 if (mopt & 0x40)
833 {
80c7c8bf 834 outputf(" MII");
748534f4
JP		 835 linktype = 0x0006;
836 }
837 if ((mopt & 0xA) == 0xA)
838 {
80c7c8bf 839 outputf(" 10Base-T / 100Base-TX");
748534f4
JP		 840 linktype = 0x0008;
841 }
842 else if ((mopt & 0xA) == 0x2)
843 {
80c7c8bf 844 outputf(" 100Base-TX");
748534f4
JP		 845 linktype = 0x0008;
846 }
847 else if ((mopt & 0xA) == 0x8)
848 {
80c7c8bf 849 outputf(" 10Base-T");
748534f4
JP		 850 linktype = 0x0008;
851 }
748534f4
JP		 852
853 /** Determine transceiver type to use, depending on value stored in
854 ** eeprom 0x16
855 **/
856 if (INF_3C90X.isBrev)
857 {
858 if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
859 {
860 /** User-defined **/
861 linktype = eeprom[0x16] & 0x000F;
862 }
863 }
864 else
865 {
866#ifdef CFG_3C90X_XCVR
867 if (CFG_3C90X_XCVR != 255)
868 linktype = CFG_3C90X_XCVR;
869#endif /* CFG_3C90X_XCVR */
870
871 /** I don't know what MII MAC only mode is!!! **/
872 if (linktype == 0x0009)
873 {
874 if (INF_3C90X.isBrev)
875 outputf("WARNING: MII External MAC Mode only supported on B-revision "
876 "cards!!!!\nFalling Back to MII Mode\n");
877 linktype = 0x0006;
878 }
879 }
880
881 /** enable DC converter for 10-Base-T **/
882 if (linktype == 0x0003)
883 {
31ddf9b3 884 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 885 }
886
887 /** Set the link to the type we just determined. **/
31ddf9b3 888 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 889 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
890 cfg &= ~(0xF<<20);
891 cfg |= (linktype<<20);
c2e34447 892 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 893
894 /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
31ddf9b3 895 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 896 if (!INF_3C90X.isBrev)
c2e34447 897 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
748534f4 898
31ddf9b3 899 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 900
901 /**
902 ** reset of the receiver on B-revision cards re-negotiates the link
903 ** takes several seconds (a computer eternity)
904 **/
905 if (INF_3C90X.isBrev)
31ddf9b3 906 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 907 else
31ddf9b3 908 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
748534f4
JP		 909
910 /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
31ddf9b3
JW		 911 _issue_command(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
912 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
80c7c8bf
JW		 913
914 /* Now stick a packet in the queue. */
915 _setup_recv(&nic);
748534f4
JP		 916
917 /**
918 ** set Indication and Interrupt flags , acknowledge any IRQ's
919 **/
31ddf9b3
JW		 920 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
921 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
922 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 923
924 /* * Set our exported functions **/
bc9e1044
JW		 925 nic.recv = _recv;
926 nic.transmit = _transmit;
47c41031 927 memcpy(nic.hwaddr, INF_3C90X.HWAddr, 6);
c2e34447 928 eth_register(&nic);
748534f4
JP		 929
930 return 1;
931}
932
933static struct pci_id a3c90x_nics[] = {
934/* Original 90x revisions: */
935PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
936PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
937PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
938PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
939PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
940/* Newer 90xB revisions: */
941PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
942PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
943PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
944PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
945PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
946PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
947PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
948PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
949/* Newer 90xC revision: */
950PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
951PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
952PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
953PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
954PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
955PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
956PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
957PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
958PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
959};
960
961struct pci_driver a3c90x_driver = {
962 .name = "3C90X",
963 .probe = a3c90x_probe,
964 .ids = a3c90x_nics,
965 .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
966};
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