]> Joshua Wise's Git repositories - netwatch.git/blame - net/3c90x.c
git.joshuawise.com / netwatch.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Actually invoke the 3c90x driver load routine.
[netwatch.git] / net / 3c90x.c
CommitLineData
748534f4
JP		 1/*
2 * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
3 * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
4 * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
5 *
6 * This program Copyright (C) 1999 LightSys Technology Services, Inc.
7 * Portions Copyright (C) 1999 Steve Smith
8 *
9 * This program may be re-distributed in source or binary form, modified,
10 * sold, or copied for any purpose, provided that the above copyright message
11 * and this text are included with all source copies or derivative works, and
12 * provided that the above copyright message and this text are included in the
13 * documentation of any binary-only distributions. This program is distributed
14 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
15 * PURPOSE or MERCHANTABILITY. Please read the associated documentation
16 * "3c90x.txt" before compiling and using this driver.
17 *
18 * --------
19 *
20 * Program written with the assistance of the 3com documentation for
21 * the 3c905B-TX card, as well as with some assistance from the 3c59x
22 * driver Donald Becker wrote for the Linux kernel, and with some assistance
23 * from the remainder of the Etherboot distribution.
24 *
25 * REVISION HISTORY:
26 *
27 * v0.10 1-26-1998 GRB Initial implementation.
28 * v0.90 1-27-1998 GRB System works.
29 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31 * Re-wrote poll and transmit for
32 * better error recovery and heavy
33 * network traffic operation
34 * v2.01 5-26-2003 NN Fixed driver alignment issue which
35 * caused system lockups if driver structures
36 * not 8-byte aligned.
37 *
38 */
39
40#include "etherboot-compat.h"
42125f27 41#include "net.h"
748534f4
JP		 42#include <timer.h>
43#include <io.h>
44#include <pci.h>
7a914840 45#include <pci-bother.h>
748534f4
JP		 46#include <minilib.h>
47#include <output.h>
48
49#define XCVR_MAGIC (0x5A00)
50/** any single transmission fails after 16 collisions or other errors
51 ** this is the number of times to retry the transmission -- this should
52 ** be plenty
53 **/
54#define XMIT_RETRIES 250
55
56/*** Register definitions for the 3c905 ***/
57enum Registers
58 {
59 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
60 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
61 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
62 regDebugControl_w = 0x74, /** 905B Revision Only **/
63 regDebugData_l = 0x70, /** 905B Revision Only **/
64 regRealTimeCnt_l = 0x40, /** Universal **/
65 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
66 regUpPoll_b = 0x3d, /** 905B Revision Only **/
67 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
68 regUpListPtr_l = 0x38, /** Universal **/
69 regCountdown_w = 0x36, /** Universal **/
70 regFreeTimer_w = 0x34, /** Universal **/
71 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
72 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
73 regDnPoll_b = 0x2d, /** 905B Revision Only **/
74 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
75 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
76 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
77 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
78 /** **/
79 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
80 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
81 regTimer_b = 0x1a, /** Universal **/
82 regTxPktId_b = 0x18, /** 905B Revision Only **/
83 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
84 };
85
86/** following are windowed registers **/
87enum Registers7
88 {
89 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
90 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
91 regVlanMask_7_w = 0x00, /** 905B Revision Only **/
92 };
93
94enum Registers6
95 {
96 regBytesXmittedOk_6_w = 0x0c, /** Universal **/
97 regBytesRcvdOk_6_w = 0x0a, /** Universal **/
98 regUpperFramesOk_6_b = 0x09, /** Universal **/
99 regFramesDeferred_6_b = 0x08, /** Universal **/
100 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
101 regFramesXmittedOk_6_b = 0x06, /** Universal **/
102 regRxOverruns_6_b = 0x05, /** Universal **/
103 regLateCollisions_6_b = 0x04, /** Universal **/
104 regSingleCollisions_6_b = 0x03, /** Universal **/
105 regMultipleCollisions_6_b = 0x02, /** Universal **/
106 regSqeErrors_6_b = 0x01, /** Universal **/
107 regCarrierLost_6_b = 0x00, /** Universal **/
108 };
109
110enum Registers5
111 {
112 regIndicationEnable_5_w = 0x0c, /** Universal **/
113 regInterruptEnable_5_w = 0x0a, /** Universal **/
114 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
115 regRxFilter_5_b = 0x08, /** Universal **/
116 regRxEarlyThresh_5_w = 0x06, /** Universal **/
117 regTxStartThresh_5_w = 0x00, /** Universal **/
118 };
119
120enum Registers4
121 {
122 regUpperBytesOk_4_b = 0x0d, /** Universal **/
123 regBadSSD_4_b = 0x0c, /** Universal **/
124 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
125 regPhysicalMgmt_4_w = 0x08, /** Universal **/
126 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
127 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
128 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
129 };
130
131enum Registers3
132 {
133 regTxFree_3_w = 0x0c, /** Universal **/
134 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
135 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
136 /** Reset Options on Non-B Revision **/
137 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
138 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
139 regInternalConfig_3_l = 0x00, /** Universal, different bit **/
140 /** definitions, pg 59 **/
141 };
142
143enum Registers2
144 {
145 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
146 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
147 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
148 };
149
150enum Registers1
151 {
152 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
153 };
154
155enum Registers0
156 {
157 regEepromData_0_w = 0x0c, /** Universal **/
158 regEepromCommand_0_w = 0x0a, /** Universal **/
159 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
160 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
161 };
162
163
164/*** The names for the eight register windows ***/
165enum Windows
166 {
167 winPowerVlan7 = 0x07,
168 winStatistics6 = 0x06,
169 winTxRxControl5 = 0x05,
170 winDiagnostics4 = 0x04,
171 winTxRxOptions3 = 0x03,
172 winAddressing2 = 0x02,
173 winUnused1 = 0x01,
174 winEepromBios0 = 0x00,
175 };
176
177
178/*** Command definitions for the 3c90X ***/
179enum Commands
180 {
181 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
182 cmdSelectRegisterWindow = 0x01, /** Universal **/
183 cmdEnableDcConverter = 0x02, /** **/
184 cmdRxDisable = 0x03, /** **/
185 cmdRxEnable = 0x04, /** Universal **/
186 cmdRxReset = 0x05, /** Universal **/
187 cmdStallCtl = 0x06, /** Universal **/
188 cmdTxEnable = 0x09, /** Universal **/
189 cmdTxDisable = 0x0A, /** **/
190 cmdTxReset = 0x0B, /** Universal **/
191 cmdRequestInterrupt = 0x0C, /** **/
192 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
193 cmdSetInterruptEnable = 0x0E, /** Universal **/
194 cmdSetIndicationEnable = 0x0F, /** Universal **/
195 cmdSetRxFilter = 0x10, /** Universal **/
196 cmdSetRxEarlyThresh = 0x11, /** **/
197 cmdSetTxStartThresh = 0x13, /** **/
198 cmdStatisticsEnable = 0x15, /** **/
199 cmdStatisticsDisable = 0x16, /** **/
200 cmdDisableDcConverter = 0x17, /** **/
201 cmdSetTxReclaimThresh = 0x18, /** **/
202 cmdSetHashFilterBit = 0x19, /** **/
203 };
204
205
206/*** Values for int status register bitmask **/
207#define INT_INTERRUPTLATCH (1<<0)
208#define INT_HOSTERROR (1<<1)
209#define INT_TXCOMPLETE (1<<2)
210#define INT_RXCOMPLETE (1<<4)
211#define INT_RXEARLY (1<<5)
212#define INT_INTREQUESTED (1<<6)
213#define INT_UPDATESTATS (1<<7)
214#define INT_LINKEVENT (1<<8)
215#define INT_DNCOMPLETE (1<<9)
216#define INT_UPCOMPLETE (1<<10)
217#define INT_CMDINPROGRESS (1<<12)
218#define INT_WINDOWNUMBER (7<<13)
219
220
221/*** TX descriptor ***/
222typedef struct
223 {
224 unsigned int DnNextPtr;
225 unsigned int FrameStartHeader;
226 unsigned int HdrAddr;
227 unsigned int HdrLength;
228 unsigned int DataAddr;
229 unsigned int DataLength;
230 }
231 TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
232
233/*** RX descriptor ***/
234typedef struct
235 {
236 unsigned int UpNextPtr;
237 unsigned int UpPktStatus;
238 unsigned int DataAddr;
239 unsigned int DataLength;
240 }
241 RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
242
243/*** Global variables ***/
244static struct
245 {
246 unsigned int is3c556;
247 unsigned char isBrev;
248 unsigned char CurrentWindow;
249 unsigned int IOAddr;
250 unsigned char HWAddr[ETH_ALEN];
251 TXD TransmitDPD;
252 RXD ReceiveUPD;
253 }
254 INF_3C90X;
7a914840 255static struct nic nic;
748534f4
JP		 256
257
258/*** a3c90x_internal_IssueCommand: sends a command to the 3c90x card
259 ***/
260static int
261a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param)
262 {
263 unsigned int val;
264
265 /** Build the cmd. **/
266 val = cmd;
267 val <<= 11;
268 val |= param;
269
270 /** Send the cmd to the cmd register **/
271 outw(val, ioaddr + regCommandIntStatus_w);
272
273 /** Wait for the cmd to complete, if necessary **/
274 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
275
276 return 0;
277 }
278
279
280/*** a3c90x_internal_SetWindow: selects a register window set.
281 ***/
282static int
283a3c90x_internal_SetWindow(int ioaddr, int window)
284 {
285
286 /** Window already as set? **/
287 if (INF_3C90X.CurrentWindow == window) return 0;
288
289 /** Issue the window command. **/
290 a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window);
291 INF_3C90X.CurrentWindow = window;
292
293 return 0;
294 }
295
296
297/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
298 ***/
299static unsigned short
300a3c90x_internal_ReadEeprom(int ioaddr, int address)
301 {
302 unsigned short val;
303
304 /** Select correct window **/
305 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winEepromBios0);
306
307 /** Make sure the eeprom isn't busy **/
308 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
309
310 /** Read the value. **/
311 if (INF_3C90X.is3c556)
312 {
313 outw(address + (0x230), ioaddr + regEepromCommand_0_w);
314 }
315 else
316 {
317 outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w);
318 }
319
320 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
321 val = inw(ioaddr + regEepromData_0_w);
322
323 return val;
324 }
325
326
327#ifdef CFG_3C90X_BOOTROM_FIX
328/*** a3c90x_internal_WriteEepromWord - write a physical word of
329 *** data to the onboard serial eeprom (not the BIOS prom, but the
330 *** nvram in the card that stores, among other things, the MAC
331 *** address).
332 ***/
333static int
334a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
335 {
336 /** Select register window **/
337 a3c90x_internal_SetWindow(ioaddr, winEepromBios0);
338
339 /** Verify Eeprom not busy **/
340 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
341
342 /** Issue WriteEnable, and wait for completion. **/
343 outw(0x30, ioaddr + regEepromCommand_0_w);
344 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
345
346 /** Issue EraseRegister, and wait for completion. **/
347 outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
348 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
349
350 /** Send the new data to the eeprom, and wait for completion. **/
351 outw(value, ioaddr + regEepromData_0_w);
352 outw(0x30, ioaddr + regEepromCommand_0_w);
353 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
354
355 /** Burn the new data into the eeprom, and wait for completion. **/
356 outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
357 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
358
359 return 0;
360 }
361#endif
362
363#ifdef CFG_3C90X_BOOTROM_FIX
364/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
365 *** and re-compute the eeprom checksum.
366 ***/
367static int
368a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
369 {
370 int cksum = 0,v;
371 int i;
372 int maxAddress, cksumAddress;
373
374 if (INF_3C90X.isBrev)
375 {
376 maxAddress=0x1f;
377 cksumAddress=0x20;
378 }
379 else
380 {
381 maxAddress=0x16;
382 cksumAddress=0x17;
383 }
384
385 /** Write the value. **/
386 if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
387 return -1;
388
389 /** Recompute the checksum. **/
390 for(i=0;i<=maxAddress;i++)
391 {
392 v = a3c90x_internal_ReadEeprom(ioaddr, i);
393 cksum ^= (v & 0xFF);
394 cksum ^= ((v>>8) & 0xFF);
395 }
396 /** Write the checksum to the location in the eeprom **/
397 if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
398 return -1;
399
400 return 0;
401 }
402#endif
403
404/*** a3c90x_reset: exported function that resets the card to its default
405 *** state. This is so the Linux driver can re-set the card up the way
406 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
407 *** not alter the selected transceiver that we used to download the boot
408 *** image.
409 ***/
410static void a3c90x_reset(void)
411 {
412#ifdef CFG_3C90X_PRESERVE_XCVR
413 int cfg;
414 /** Read the current InternalConfig value. **/
415 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
416 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
417#endif
418
419 /** Send the reset command to the card **/
420 outputf("Issuing RESET:");
421 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdGlobalReset, 0);
422
423 /** wait for reset command to complete **/
424 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
425
426 /** global reset command resets station mask, non-B revision cards
427 ** require explicit reset of values
428 **/
429 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
430 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
431 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
432 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
433
434#ifdef CFG_3C90X_PRESERVE_XCVR
435 /** Re-set the original InternalConfig value from before reset **/
436 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
437 outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
438
439 /** enable DC converter for 10-Base-T **/
440 if ((cfg&0x0300) == 0x0300)
441 {
442 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
443 }
444#endif
445
446 /** Issue transmit reset, wait for command completion **/
447 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0);
448 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
449 ;
450 if (! INF_3C90X.isBrev)
451 outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
452 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
453
454 /**
455 ** reset of the receiver on B-revision cards re-negotiates the link
456 ** takes several seconds (a computer eternity)
457 **/
458 if (INF_3C90X.isBrev)
459 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
460 else
461 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
462 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
463 ;
464 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
465
466 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
467 cmdSetInterruptEnable, 0);
468 /** enable rxComplete and txComplete **/
469 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
470 cmdSetIndicationEnable, 0x0014);
471 /** acknowledge any pending status flags **/
472 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
473 cmdAcknowledgeInterrupt, 0x661);
474
475 return;
476 }
477
478
479
480/*** a3c90x_transmit: exported function that transmits a packet. Does not
481 *** return any particular status. Parameters are:
482 *** dest_addr[6] - destination address, ethernet;
483 *** proto - protocol type (ARP, IP, etc);
484 *** size - size of the non-header part of the packet that needs transmitted;
485 *** pkt - the pointer to the packet data itself.
486 ***/
487static void
488a3c90x_transmit(const char *dest_addr, unsigned int proto,
489 unsigned int size, const char *pkt)
490 {
491
492 struct eth_hdr
493 {
494 unsigned char dst_addr[ETH_ALEN];
495 unsigned char src_addr[ETH_ALEN];
496 unsigned short type;
497 } hdr;
498
499 unsigned char status;
500 unsigned i, retries;
501
502 for (retries=0; retries < XMIT_RETRIES ; retries++)
503 {
504 /** Stall the download engine **/
505 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 2);
506
507 /** Make sure the card is not waiting on us **/
508 inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
509 inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
510
511 while (inw(INF_3C90X.IOAddr+regCommandIntStatus_w) &
512 INT_CMDINPROGRESS)
513 ;
514
515 /** Set the ethernet packet type **/
516 hdr.type = htons(proto);
517
518 /** Copy the destination address **/
519 memcpy(hdr.dst_addr, dest_addr, ETH_ALEN);
520
521 /** Copy our MAC address **/
522 memcpy(hdr.src_addr, INF_3C90X.HWAddr, ETH_ALEN);
523
524 /** Setup the DPD (download descriptor) **/
525 INF_3C90X.TransmitDPD.DnNextPtr = 0;
526 /** set notification for transmission completion (bit 15) **/
527 INF_3C90X.TransmitDPD.FrameStartHeader = (size + sizeof(hdr)) | 0x8000;
528 INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr);
529 INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr);
530 INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(pkt);
531 INF_3C90X.TransmitDPD.DataLength = size + (1<<31);
532
533 /** Send the packet **/
534 outl(virt_to_bus(&(INF_3C90X.TransmitDPD)),
535 INF_3C90X.IOAddr + regDnListPtr_l);
536
537 /** End Stall and Wait for upload to complete. **/
538 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 3);
539 while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
540 ;
541
542 /** Wait for NIC Transmit to Complete **/
543 oneshot_start_ms(10); /* Give it 10 ms */
544 while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) &&
545 oneshot_running())
546 ;
547
548 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004))
549 {
550 outputf("3C90X: Tx Timeout");
551 continue;
552 }
553
554 status = inb(INF_3C90X.IOAddr + regTxStatus_b);
555
556 /** acknowledge transmit interrupt by writing status **/
557 outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
558
559 /** successful completion (sans "interrupt Requested" bit) **/
560 if ((status & 0xbf) == 0x80)
561 return;
562
563 outputf("3C90X: Status (%hhX)", status);
564 /** check error codes **/
565 if (status & 0x02)
566 {
567 outputf("3C90X: Tx Reclaim Error (%hhX)", status);
568 a3c90x_reset();
569 }
570 else if (status & 0x04)
571 {
572 outputf("3C90X: Tx Status Overflow (%hhX)", status);
573 for (i=0; i<32; i++)
574 outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
575 /** must re-enable after max collisions before re-issuing tx **/
576 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
577 }
578 else if (status & 0x08)
579 {
580 outputf("3C90X: Tx Max Collisions (%hhX)", status);
581 /** must re-enable after max collisions before re-issuing tx **/
582 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
583 }
584 else if (status & 0x10)
585 {
586 outputf("3C90X: Tx Underrun (%hhX)", status);
587 a3c90x_reset();
588 }
589 else if (status & 0x20)
590 {
591 outputf("3C90X: Tx Jabber (%hhX)", status);
592 a3c90x_reset();
593 }
594 else if ((status & 0x80) != 0x80)
595 {
596 outputf("3C90X: Internal Error - Incomplete Transmission (%hhX)",
597 status);
598 a3c90x_reset();
599 }
600 }
601
602 /** failed after RETRY attempts **/
603 outputf("Failed to send after %d retries", retries);
604 return;
605
606 }
607
608
609
610/*** a3c90x_poll: exported routine that waits for a certain length of time
611 *** for a packet, and if it sees none, returns 0. This routine should
612 *** copy the packet to nic->packet if it gets a packet and set the size
613 *** in nic->packetlen. Return 1 if a packet was found.
614 ***/
615static int
616a3c90x_poll(struct nic *nic, int retrieve)
617 {
618 int i, errcode;
619
620 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
621 {
622 return 0;
623 }
624
625 if ( ! retrieve ) return 1;
626
627 /** we don't need to acknowledge rxComplete -- the upload engine
628 ** does it for us.
629 **/
630
631 /** Build the up-load descriptor **/
632 INF_3C90X.ReceiveUPD.UpNextPtr = 0;
633 INF_3C90X.ReceiveUPD.UpPktStatus = 0;
634 INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet);
635 INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
636
637 /** Submit the upload descriptor to the NIC **/
638 outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)),
639 INF_3C90X.IOAddr + regUpListPtr_l);
640
641 /** Wait for upload completion (upComplete(15) or upError (14)) **/
642 for(i=0;i<40000;i++);
643 while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
644 for(i=0;i<40000;i++);
645
646 /** Check for Error (else we have good packet) **/
647 if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
648 {
649 errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
650 if (errcode & (1<<16))
651 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);
652 else if (errcode & (1<<17))
653 outputf("3C90X: Runt Frame (%hX)",errcode>>16);
654 else if (errcode & (1<<18))
655 outputf("3C90X: Alignment Error (%hX)",errcode>>16);
656 else if (errcode & (1<<19))
657 outputf("3C90X: CRC Error (%hX)",errcode>>16);
658 else if (errcode & (1<<20))
659 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);
660 else
661 outputf("3C90X: Packet error (%hX)",errcode>>16);
662 return 0;
663 }
664
665 /** Ok, got packet. Set length in nic->packetlen. **/
666 nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
667
668 return 1;
669 }
670
671
672
673/*** a3c90x_disable: exported routine to disable the card. What's this for?
674 *** the eepro100.c driver didn't have one, so I just left this one empty too.
675 *** Ideas anyone?
676 *** Must turn off receiver at least so stray packets will not corrupt memory
677 *** [Ken]
678 ***/
679void a3c90x_disable(struct dev *dev)
680{
681 /* reset and disable merge */
682 a3c90x_reset();
683 /* Disable the receiver and transmitter. */
684 outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
685 outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
686}
687
688
689/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
690 *** initialization. If this routine is called, the pci functions did find the
691 *** card. We just have to init it here.
692 ***/
693static int a3c90x_probe(struct pci_dev * pci, void * data)
694{
748534f4
JP		 695 INF_3C90X.is3c556 = (pci->did == 0x6055);
696
697 int i, c;
698 unsigned short eeprom[0x21];
699 unsigned int cfg;
700 unsigned int mopt;
701 unsigned int mstat;
702 unsigned short linktype;
703#define HWADDR_OFFSET 10
704
705 unsigned long ioaddr = 0;
706 for (i = 0; i < 6; i++) {
707 if (pci->bars[i].type == PCI_BAR_IO) {
708 ioaddr = pci->bars[i].addr;
709 break;
710 }
711 }
712
713 if (ioaddr == 0)
714 return 0;
715/*
716 adjust_pci_dev(pci);
717*/
7a914840 718 pci_bother_add(pci);
42125f27
JP		 719 nic.ioaddr = ioaddr & ~3;
720 nic.irqno = 0;
748534f4
JP		 721
722 INF_3C90X.IOAddr = ioaddr & ~3;
723 INF_3C90X.CurrentWindow = 255;
724 switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
725 {
726 case 0x9000: /** 10 Base TPO **/
727 case 0x9001: /** 10/100 T4 **/
728 case 0x9050: /** 10/100 TPO **/
729 case 0x9051: /** 10 Base Combo **/
730 INF_3C90X.isBrev = 0;
731 break;
732
733 case 0x9004: /** 10 Base TPO **/
734 case 0x9005: /** 10 Base Combo **/
735 case 0x9006: /** 10 Base TPO and Base2 **/
736 case 0x900A: /** 10 Base FL **/
737 case 0x9055: /** 10/100 TPO **/
738 case 0x9056: /** 10/100 T4 **/
739 case 0x905A: /** 10 Base FX **/
740 default:
741 INF_3C90X.isBrev = 1;
742 break;
743 }
744
745 /** Load the EEPROM contents **/
746 if (INF_3C90X.isBrev)
747 {
748 for(i=0;i<=0x20;i++)
749 {
750 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
751 }
752
753#ifdef CFG_3C90X_BOOTROM_FIX
754 /** Set xcvrSelect in InternalConfig in eeprom. **/
755 /* only necessary for 3c905b revision cards with boot PROM bug!!! */
756 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
757#endif
758
759#ifdef CFG_3C90X_XCVR
760 if (CFG_3C90X_XCVR == 255)
761 {
762 /** Clear the LanWorks register **/
763 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
764 }
765 else
766 {
767 /** Set the selected permanent-xcvrSelect in the
768 ** LanWorks register
769 **/
770 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
771 XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
772 }
773#endif
774 }
775 else
776 {
777 for(i=0;i<=0x17;i++)
778 {
779 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
780 }
781 }
782
783 /** Print identification message **/
784#ifdef CFG_3C90X_BOOTROM_FIX
785 if (INF_3C90X.isBrev)
786 {
787 outputf("NOTE: 3c905b bootrom fix enabled; has side "
788 "effects. See 3c90x.txt for info.");
789 }
790#endif
791
792 /** Retrieve the Hardware address and print it on the screen. **/
793 INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
794 INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
795 INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
796 INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
797 INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
798 INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
799 outputf("MAC Address = %!", INF_3C90X.HWAddr);
800
801 /** 3C556: Invert MII power **/
802 if (INF_3C90X.is3c556) {
803 unsigned int tmp;
804 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
805 tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
806 tmp |= 0x4000;
807 outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
808 }
809
810 /* Test if the link is good, if not continue */
811 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winDiagnostics4);
812 mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
813 if((mstat & (1<<11)) == 0) {
814 outputf("Valid link not established");
815 return 0;
816 }
817
818 /** Program the MAC address into the station address registers **/
819 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
820 outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
821 outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
822 outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
823 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
824 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
825 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
826
827 /** Fill in our entry in the etherboot arp table **/
828/* XXX ? for lwip?
829 for(i=0;i<ETH_ALEN;i++)
42125f27 830 nic.node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
748534f4
JP		 831*/
832
833 /** Read the media options register, print a message and set default
834 ** xcvr.
835 **
836 ** Uses Media Option command on B revision, Reset Option on non-B
837 ** revision cards -- same register address
838 **/
839 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
840 mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
841
842 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
843 if (! INF_3C90X.isBrev)
844 {
845 mopt &= 0x7F;
846 }
847
848 outputf("Connectors present: ");
849 c = 0;
850 linktype = 0x0008;
851 if (mopt & 0x01)
852 {
853 outputf("%s100Base-T4",(c++)?", ":"");
854 linktype = 0x0006;
855 }
856 if (mopt & 0x04)
857 {
858 outputf("%s100Base-FX",(c++)?", ":"");
859 linktype = 0x0005;
860 }
861 if (mopt & 0x10)
862 {
863 outputf("%s10Base-2",(c++)?", ":"");
864 linktype = 0x0003;
865 }
866 if (mopt & 0x20)
867 {
868 outputf("%sAUI",(c++)?", ":"");
869 linktype = 0x0001;
870 }
871 if (mopt & 0x40)
872 {
873 outputf("%sMII",(c++)?", ":"");
874 linktype = 0x0006;
875 }
876 if ((mopt & 0xA) == 0xA)
877 {
878 outputf("%s10Base-T / 100Base-TX",(c++)?", ":"");
879 linktype = 0x0008;
880 }
881 else if ((mopt & 0xA) == 0x2)
882 {
883 outputf("%s100Base-TX",(c++)?", ":"");
884 linktype = 0x0008;
885 }
886 else if ((mopt & 0xA) == 0x8)
887 {
888 outputf("%s10Base-T",(c++)?", ":"");
889 linktype = 0x0008;
890 }
891 outputf(".");
892
893 /** Determine transceiver type to use, depending on value stored in
894 ** eeprom 0x16
895 **/
896 if (INF_3C90X.isBrev)
897 {
898 if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
899 {
900 /** User-defined **/
901 linktype = eeprom[0x16] & 0x000F;
902 }
903 }
904 else
905 {
906#ifdef CFG_3C90X_XCVR
907 if (CFG_3C90X_XCVR != 255)
908 linktype = CFG_3C90X_XCVR;
909#endif /* CFG_3C90X_XCVR */
910
911 /** I don't know what MII MAC only mode is!!! **/
912 if (linktype == 0x0009)
913 {
914 if (INF_3C90X.isBrev)
915 outputf("WARNING: MII External MAC Mode only supported on B-revision "
916 "cards!!!!\nFalling Back to MII Mode\n");
917 linktype = 0x0006;
918 }
919 }
920
921 /** enable DC converter for 10-Base-T **/
922 if (linktype == 0x0003)
923 {
924 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
925 }
926
927 /** Set the link to the type we just determined. **/
928 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
929 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
930 cfg &= ~(0xF<<20);
931 cfg |= (linktype<<20);
932 outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
933
934 /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
935 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0x00);
936 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
937 ;
938
939 if (!INF_3C90X.isBrev)
940 outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
941
942 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
943
944 /**
945 ** reset of the receiver on B-revision cards re-negotiates the link
946 ** takes several seconds (a computer eternity)
947 **/
948 if (INF_3C90X.isBrev)
949 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
950 else
951 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
952 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
953 ;
954
955 /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
956 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
957 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
958
959
960 /**
961 ** set Indication and Interrupt flags , acknowledge any IRQ's
962 **/
963 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
964 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
965 cmdSetIndicationEnable, 0x0014);
966 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
967 cmdAcknowledgeInterrupt, 0x661);
968
969 /* * Set our exported functions **/
42125f27
JP		 970 nic.poll = a3c90x_poll;
971 nic.transmit = a3c90x_transmit;
748534f4
JP		 972
973 return 1;
974}
975
976static struct pci_id a3c90x_nics[] = {
977/* Original 90x revisions: */
978PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
979PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
980PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
981PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
982PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
983/* Newer 90xB revisions: */
984PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
985PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
986PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
987PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
988PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
989PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
990PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
991PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
992/* Newer 90xC revision: */
993PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
994PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
995PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
996PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
997PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
998PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
999PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
1000PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
1001PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
1002};
1003
1004struct pci_driver a3c90x_driver = {
1005 .name = "3C90X",
1006 .probe = a3c90x_probe,
1007 .ids = a3c90x_nics,
1008 .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
1009};
NetWatch system management mode lights out box
This page took 0.125727 seconds and 4 git commands to generate.