]>
Commit | Line | Data |
---|---|---|
748534f4 JP |
1 | /* |
2 | * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written | |
3 | * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith, | |
4 | * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net). | |
5 | * | |
6 | * This program Copyright (C) 1999 LightSys Technology Services, Inc. | |
7 | * Portions Copyright (C) 1999 Steve Smith | |
8 | * | |
9 | * This program may be re-distributed in source or binary form, modified, | |
10 | * sold, or copied for any purpose, provided that the above copyright message | |
11 | * and this text are included with all source copies or derivative works, and | |
12 | * provided that the above copyright message and this text are included in the | |
13 | * documentation of any binary-only distributions. This program is distributed | |
14 | * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR | |
15 | * PURPOSE or MERCHANTABILITY. Please read the associated documentation | |
16 | * "3c90x.txt" before compiling and using this driver. | |
17 | * | |
18 | * -------- | |
19 | * | |
20 | * Program written with the assistance of the 3com documentation for | |
21 | * the 3c905B-TX card, as well as with some assistance from the 3c59x | |
22 | * driver Donald Becker wrote for the Linux kernel, and with some assistance | |
23 | * from the remainder of the Etherboot distribution. | |
24 | * | |
25 | * REVISION HISTORY: | |
26 | * | |
27 | * v0.10 1-26-1998 GRB Initial implementation. | |
28 | * v0.90 1-27-1998 GRB System works. | |
29 | * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed. | |
30 | * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code) | |
31 | * Re-wrote poll and transmit for | |
32 | * better error recovery and heavy | |
33 | * network traffic operation | |
34 | * v2.01 5-26-2003 NN Fixed driver alignment issue which | |
35 | * caused system lockups if driver structures | |
36 | * not 8-byte aligned. | |
37 | * | |
38 | */ | |
39 | ||
40 | #include "etherboot-compat.h" | |
42125f27 | 41 | #include "net.h" |
748534f4 JP |
42 | #include <timer.h> |
43 | #include <io.h> | |
44 | #include <pci.h> | |
45 | #include <minilib.h> | |
46 | #include <output.h> | |
47 | ||
48 | #define XCVR_MAGIC (0x5A00) | |
49 | /** any single transmission fails after 16 collisions or other errors | |
50 | ** this is the number of times to retry the transmission -- this should | |
51 | ** be plenty | |
52 | **/ | |
53 | #define XMIT_RETRIES 250 | |
54 | ||
55 | /*** Register definitions for the 3c905 ***/ | |
56 | enum Registers | |
57 | { | |
58 | regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/ | |
59 | regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/ | |
60 | regDnMaxBurst_w = 0x78, /** 905B Revision Only **/ | |
61 | regDebugControl_w = 0x74, /** 905B Revision Only **/ | |
62 | regDebugData_l = 0x70, /** 905B Revision Only **/ | |
63 | regRealTimeCnt_l = 0x40, /** Universal **/ | |
64 | regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/ | |
65 | regUpPoll_b = 0x3d, /** 905B Revision Only **/ | |
66 | regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/ | |
67 | regUpListPtr_l = 0x38, /** Universal **/ | |
68 | regCountdown_w = 0x36, /** Universal **/ | |
69 | regFreeTimer_w = 0x34, /** Universal **/ | |
70 | regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/ | |
71 | regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/ | |
72 | regDnPoll_b = 0x2d, /** 905B Revision Only **/ | |
73 | regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/ | |
74 | regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/ | |
75 | regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/ | |
76 | regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/ | |
77 | /** **/ | |
78 | regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/ | |
79 | regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/ | |
80 | regTimer_b = 0x1a, /** Universal **/ | |
81 | regTxPktId_b = 0x18, /** 905B Revision Only **/ | |
82 | regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/ | |
83 | }; | |
84 | ||
85 | /** following are windowed registers **/ | |
86 | enum Registers7 | |
87 | { | |
88 | regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/ | |
89 | regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/ | |
90 | regVlanMask_7_w = 0x00, /** 905B Revision Only **/ | |
91 | }; | |
92 | ||
93 | enum Registers6 | |
94 | { | |
95 | regBytesXmittedOk_6_w = 0x0c, /** Universal **/ | |
96 | regBytesRcvdOk_6_w = 0x0a, /** Universal **/ | |
97 | regUpperFramesOk_6_b = 0x09, /** Universal **/ | |
98 | regFramesDeferred_6_b = 0x08, /** Universal **/ | |
99 | regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/ | |
100 | regFramesXmittedOk_6_b = 0x06, /** Universal **/ | |
101 | regRxOverruns_6_b = 0x05, /** Universal **/ | |
102 | regLateCollisions_6_b = 0x04, /** Universal **/ | |
103 | regSingleCollisions_6_b = 0x03, /** Universal **/ | |
104 | regMultipleCollisions_6_b = 0x02, /** Universal **/ | |
105 | regSqeErrors_6_b = 0x01, /** Universal **/ | |
106 | regCarrierLost_6_b = 0x00, /** Universal **/ | |
107 | }; | |
108 | ||
109 | enum Registers5 | |
110 | { | |
111 | regIndicationEnable_5_w = 0x0c, /** Universal **/ | |
112 | regInterruptEnable_5_w = 0x0a, /** Universal **/ | |
113 | regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/ | |
114 | regRxFilter_5_b = 0x08, /** Universal **/ | |
115 | regRxEarlyThresh_5_w = 0x06, /** Universal **/ | |
116 | regTxStartThresh_5_w = 0x00, /** Universal **/ | |
117 | }; | |
118 | ||
119 | enum Registers4 | |
120 | { | |
121 | regUpperBytesOk_4_b = 0x0d, /** Universal **/ | |
122 | regBadSSD_4_b = 0x0c, /** Universal **/ | |
123 | regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/ | |
124 | regPhysicalMgmt_4_w = 0x08, /** Universal **/ | |
125 | regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/ | |
126 | regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/ | |
127 | regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/ | |
128 | }; | |
129 | ||
130 | enum Registers3 | |
131 | { | |
132 | regTxFree_3_w = 0x0c, /** Universal **/ | |
133 | regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/ | |
134 | regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/ | |
135 | /** Reset Options on Non-B Revision **/ | |
136 | regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/ | |
137 | regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/ | |
138 | regInternalConfig_3_l = 0x00, /** Universal, different bit **/ | |
139 | /** definitions, pg 59 **/ | |
140 | }; | |
141 | ||
142 | enum Registers2 | |
143 | { | |
144 | regResetOptions_2_w = 0x0c, /** 905B Revision Only **/ | |
145 | regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/ | |
146 | regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/ | |
147 | }; | |
148 | ||
149 | enum Registers1 | |
150 | { | |
151 | regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/ | |
152 | }; | |
153 | ||
154 | enum Registers0 | |
155 | { | |
156 | regEepromData_0_w = 0x0c, /** Universal **/ | |
157 | regEepromCommand_0_w = 0x0a, /** Universal **/ | |
158 | regBiosRomData_0_b = 0x08, /** 905B Revision Only **/ | |
159 | regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/ | |
160 | }; | |
161 | ||
162 | ||
163 | /*** The names for the eight register windows ***/ | |
164 | enum Windows | |
165 | { | |
166 | winPowerVlan7 = 0x07, | |
167 | winStatistics6 = 0x06, | |
168 | winTxRxControl5 = 0x05, | |
169 | winDiagnostics4 = 0x04, | |
170 | winTxRxOptions3 = 0x03, | |
171 | winAddressing2 = 0x02, | |
172 | winUnused1 = 0x01, | |
173 | winEepromBios0 = 0x00, | |
174 | }; | |
175 | ||
176 | ||
177 | /*** Command definitions for the 3c90X ***/ | |
178 | enum Commands | |
179 | { | |
180 | cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/ | |
181 | cmdSelectRegisterWindow = 0x01, /** Universal **/ | |
182 | cmdEnableDcConverter = 0x02, /** **/ | |
183 | cmdRxDisable = 0x03, /** **/ | |
184 | cmdRxEnable = 0x04, /** Universal **/ | |
185 | cmdRxReset = 0x05, /** Universal **/ | |
186 | cmdStallCtl = 0x06, /** Universal **/ | |
187 | cmdTxEnable = 0x09, /** Universal **/ | |
188 | cmdTxDisable = 0x0A, /** **/ | |
189 | cmdTxReset = 0x0B, /** Universal **/ | |
190 | cmdRequestInterrupt = 0x0C, /** **/ | |
191 | cmdAcknowledgeInterrupt = 0x0D, /** Universal **/ | |
192 | cmdSetInterruptEnable = 0x0E, /** Universal **/ | |
193 | cmdSetIndicationEnable = 0x0F, /** Universal **/ | |
194 | cmdSetRxFilter = 0x10, /** Universal **/ | |
195 | cmdSetRxEarlyThresh = 0x11, /** **/ | |
196 | cmdSetTxStartThresh = 0x13, /** **/ | |
197 | cmdStatisticsEnable = 0x15, /** **/ | |
198 | cmdStatisticsDisable = 0x16, /** **/ | |
199 | cmdDisableDcConverter = 0x17, /** **/ | |
200 | cmdSetTxReclaimThresh = 0x18, /** **/ | |
201 | cmdSetHashFilterBit = 0x19, /** **/ | |
202 | }; | |
203 | ||
204 | ||
205 | /*** Values for int status register bitmask **/ | |
206 | #define INT_INTERRUPTLATCH (1<<0) | |
207 | #define INT_HOSTERROR (1<<1) | |
208 | #define INT_TXCOMPLETE (1<<2) | |
209 | #define INT_RXCOMPLETE (1<<4) | |
210 | #define INT_RXEARLY (1<<5) | |
211 | #define INT_INTREQUESTED (1<<6) | |
212 | #define INT_UPDATESTATS (1<<7) | |
213 | #define INT_LINKEVENT (1<<8) | |
214 | #define INT_DNCOMPLETE (1<<9) | |
215 | #define INT_UPCOMPLETE (1<<10) | |
216 | #define INT_CMDINPROGRESS (1<<12) | |
217 | #define INT_WINDOWNUMBER (7<<13) | |
218 | ||
219 | ||
220 | /*** TX descriptor ***/ | |
221 | typedef struct | |
222 | { | |
223 | unsigned int DnNextPtr; | |
224 | unsigned int FrameStartHeader; | |
225 | unsigned int HdrAddr; | |
226 | unsigned int HdrLength; | |
227 | unsigned int DataAddr; | |
228 | unsigned int DataLength; | |
229 | } | |
230 | TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */ | |
231 | ||
232 | /*** RX descriptor ***/ | |
233 | typedef struct | |
234 | { | |
235 | unsigned int UpNextPtr; | |
236 | unsigned int UpPktStatus; | |
237 | unsigned int DataAddr; | |
238 | unsigned int DataLength; | |
239 | } | |
240 | RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */ | |
241 | ||
242 | /*** Global variables ***/ | |
243 | static struct | |
244 | { | |
245 | unsigned int is3c556; | |
246 | unsigned char isBrev; | |
247 | unsigned char CurrentWindow; | |
248 | unsigned int IOAddr; | |
249 | unsigned char HWAddr[ETH_ALEN]; | |
250 | TXD TransmitDPD; | |
251 | RXD ReceiveUPD; | |
252 | } | |
253 | INF_3C90X; | |
254 | ||
255 | ||
256 | /*** a3c90x_internal_IssueCommand: sends a command to the 3c90x card | |
257 | ***/ | |
258 | static int | |
259 | a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param) | |
260 | { | |
261 | unsigned int val; | |
262 | ||
263 | /** Build the cmd. **/ | |
264 | val = cmd; | |
265 | val <<= 11; | |
266 | val |= param; | |
267 | ||
268 | /** Send the cmd to the cmd register **/ | |
269 | outw(val, ioaddr + regCommandIntStatus_w); | |
270 | ||
271 | /** Wait for the cmd to complete, if necessary **/ | |
272 | while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | ||
278 | /*** a3c90x_internal_SetWindow: selects a register window set. | |
279 | ***/ | |
280 | static int | |
281 | a3c90x_internal_SetWindow(int ioaddr, int window) | |
282 | { | |
283 | ||
284 | /** Window already as set? **/ | |
285 | if (INF_3C90X.CurrentWindow == window) return 0; | |
286 | ||
287 | /** Issue the window command. **/ | |
288 | a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window); | |
289 | INF_3C90X.CurrentWindow = window; | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
294 | ||
295 | /*** a3c90x_internal_ReadEeprom - read data from the serial eeprom. | |
296 | ***/ | |
297 | static unsigned short | |
298 | a3c90x_internal_ReadEeprom(int ioaddr, int address) | |
299 | { | |
300 | unsigned short val; | |
301 | ||
302 | /** Select correct window **/ | |
303 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winEepromBios0); | |
304 | ||
305 | /** Make sure the eeprom isn't busy **/ | |
306 | while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); | |
307 | ||
308 | /** Read the value. **/ | |
309 | if (INF_3C90X.is3c556) | |
310 | { | |
311 | outw(address + (0x230), ioaddr + regEepromCommand_0_w); | |
312 | } | |
313 | else | |
314 | { | |
315 | outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w); | |
316 | } | |
317 | ||
318 | while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); | |
319 | val = inw(ioaddr + regEepromData_0_w); | |
320 | ||
321 | return val; | |
322 | } | |
323 | ||
324 | ||
325 | #ifdef CFG_3C90X_BOOTROM_FIX | |
326 | /*** a3c90x_internal_WriteEepromWord - write a physical word of | |
327 | *** data to the onboard serial eeprom (not the BIOS prom, but the | |
328 | *** nvram in the card that stores, among other things, the MAC | |
329 | *** address). | |
330 | ***/ | |
331 | static int | |
332 | a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value) | |
333 | { | |
334 | /** Select register window **/ | |
335 | a3c90x_internal_SetWindow(ioaddr, winEepromBios0); | |
336 | ||
337 | /** Verify Eeprom not busy **/ | |
338 | while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); | |
339 | ||
340 | /** Issue WriteEnable, and wait for completion. **/ | |
341 | outw(0x30, ioaddr + regEepromCommand_0_w); | |
342 | while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); | |
343 | ||
344 | /** Issue EraseRegister, and wait for completion. **/ | |
345 | outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w); | |
346 | while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); | |
347 | ||
348 | /** Send the new data to the eeprom, and wait for completion. **/ | |
349 | outw(value, ioaddr + regEepromData_0_w); | |
350 | outw(0x30, ioaddr + regEepromCommand_0_w); | |
351 | while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); | |
352 | ||
353 | /** Burn the new data into the eeprom, and wait for completion. **/ | |
354 | outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w); | |
355 | while((1<<15) & inw(ioaddr + regEepromCommand_0_w)); | |
356 | ||
357 | return 0; | |
358 | } | |
359 | #endif | |
360 | ||
361 | #ifdef CFG_3C90X_BOOTROM_FIX | |
362 | /*** a3c90x_internal_WriteEeprom - write data to the serial eeprom, | |
363 | *** and re-compute the eeprom checksum. | |
364 | ***/ | |
365 | static int | |
366 | a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value) | |
367 | { | |
368 | int cksum = 0,v; | |
369 | int i; | |
370 | int maxAddress, cksumAddress; | |
371 | ||
372 | if (INF_3C90X.isBrev) | |
373 | { | |
374 | maxAddress=0x1f; | |
375 | cksumAddress=0x20; | |
376 | } | |
377 | else | |
378 | { | |
379 | maxAddress=0x16; | |
380 | cksumAddress=0x17; | |
381 | } | |
382 | ||
383 | /** Write the value. **/ | |
384 | if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1) | |
385 | return -1; | |
386 | ||
387 | /** Recompute the checksum. **/ | |
388 | for(i=0;i<=maxAddress;i++) | |
389 | { | |
390 | v = a3c90x_internal_ReadEeprom(ioaddr, i); | |
391 | cksum ^= (v & 0xFF); | |
392 | cksum ^= ((v>>8) & 0xFF); | |
393 | } | |
394 | /** Write the checksum to the location in the eeprom **/ | |
395 | if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1) | |
396 | return -1; | |
397 | ||
398 | return 0; | |
399 | } | |
400 | #endif | |
401 | ||
402 | /*** a3c90x_reset: exported function that resets the card to its default | |
403 | *** state. This is so the Linux driver can re-set the card up the way | |
404 | *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will | |
405 | *** not alter the selected transceiver that we used to download the boot | |
406 | *** image. | |
407 | ***/ | |
408 | static void a3c90x_reset(void) | |
409 | { | |
410 | #ifdef CFG_3C90X_PRESERVE_XCVR | |
411 | int cfg; | |
412 | /** Read the current InternalConfig value. **/ | |
413 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3); | |
414 | cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l); | |
415 | #endif | |
416 | ||
417 | /** Send the reset command to the card **/ | |
418 | outputf("Issuing RESET:"); | |
419 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdGlobalReset, 0); | |
420 | ||
421 | /** wait for reset command to complete **/ | |
422 | while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS); | |
423 | ||
424 | /** global reset command resets station mask, non-B revision cards | |
425 | ** require explicit reset of values | |
426 | **/ | |
427 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2); | |
428 | outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0); | |
429 | outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2); | |
430 | outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4); | |
431 | ||
432 | #ifdef CFG_3C90X_PRESERVE_XCVR | |
433 | /** Re-set the original InternalConfig value from before reset **/ | |
434 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3); | |
435 | outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l); | |
436 | ||
437 | /** enable DC converter for 10-Base-T **/ | |
438 | if ((cfg&0x0300) == 0x0300) | |
439 | { | |
440 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0); | |
441 | } | |
442 | #endif | |
443 | ||
444 | /** Issue transmit reset, wait for command completion **/ | |
445 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0); | |
446 | while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS) | |
447 | ; | |
448 | if (! INF_3C90X.isBrev) | |
449 | outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b); | |
450 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0); | |
451 | ||
452 | /** | |
453 | ** reset of the receiver on B-revision cards re-negotiates the link | |
454 | ** takes several seconds (a computer eternity) | |
455 | **/ | |
456 | if (INF_3C90X.isBrev) | |
457 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04); | |
458 | else | |
459 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00); | |
460 | while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS); | |
461 | ; | |
462 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0); | |
463 | ||
464 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, | |
465 | cmdSetInterruptEnable, 0); | |
466 | /** enable rxComplete and txComplete **/ | |
467 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, | |
468 | cmdSetIndicationEnable, 0x0014); | |
469 | /** acknowledge any pending status flags **/ | |
470 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, | |
471 | cmdAcknowledgeInterrupt, 0x661); | |
472 | ||
473 | return; | |
474 | } | |
475 | ||
476 | ||
477 | ||
478 | /*** a3c90x_transmit: exported function that transmits a packet. Does not | |
479 | *** return any particular status. Parameters are: | |
480 | *** dest_addr[6] - destination address, ethernet; | |
481 | *** proto - protocol type (ARP, IP, etc); | |
482 | *** size - size of the non-header part of the packet that needs transmitted; | |
483 | *** pkt - the pointer to the packet data itself. | |
484 | ***/ | |
485 | static void | |
486 | a3c90x_transmit(const char *dest_addr, unsigned int proto, | |
487 | unsigned int size, const char *pkt) | |
488 | { | |
489 | ||
490 | struct eth_hdr | |
491 | { | |
492 | unsigned char dst_addr[ETH_ALEN]; | |
493 | unsigned char src_addr[ETH_ALEN]; | |
494 | unsigned short type; | |
495 | } hdr; | |
496 | ||
497 | unsigned char status; | |
498 | unsigned i, retries; | |
499 | ||
500 | for (retries=0; retries < XMIT_RETRIES ; retries++) | |
501 | { | |
502 | /** Stall the download engine **/ | |
503 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 2); | |
504 | ||
505 | /** Make sure the card is not waiting on us **/ | |
506 | inw(INF_3C90X.IOAddr + regCommandIntStatus_w); | |
507 | inw(INF_3C90X.IOAddr + regCommandIntStatus_w); | |
508 | ||
509 | while (inw(INF_3C90X.IOAddr+regCommandIntStatus_w) & | |
510 | INT_CMDINPROGRESS) | |
511 | ; | |
512 | ||
513 | /** Set the ethernet packet type **/ | |
514 | hdr.type = htons(proto); | |
515 | ||
516 | /** Copy the destination address **/ | |
517 | memcpy(hdr.dst_addr, dest_addr, ETH_ALEN); | |
518 | ||
519 | /** Copy our MAC address **/ | |
520 | memcpy(hdr.src_addr, INF_3C90X.HWAddr, ETH_ALEN); | |
521 | ||
522 | /** Setup the DPD (download descriptor) **/ | |
523 | INF_3C90X.TransmitDPD.DnNextPtr = 0; | |
524 | /** set notification for transmission completion (bit 15) **/ | |
525 | INF_3C90X.TransmitDPD.FrameStartHeader = (size + sizeof(hdr)) | 0x8000; | |
526 | INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr); | |
527 | INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr); | |
528 | INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(pkt); | |
529 | INF_3C90X.TransmitDPD.DataLength = size + (1<<31); | |
530 | ||
531 | /** Send the packet **/ | |
532 | outl(virt_to_bus(&(INF_3C90X.TransmitDPD)), | |
533 | INF_3C90X.IOAddr + regDnListPtr_l); | |
534 | ||
535 | /** End Stall and Wait for upload to complete. **/ | |
536 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 3); | |
537 | while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0) | |
538 | ; | |
539 | ||
540 | /** Wait for NIC Transmit to Complete **/ | |
541 | oneshot_start_ms(10); /* Give it 10 ms */ | |
542 | while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) && | |
543 | oneshot_running()) | |
544 | ; | |
545 | ||
546 | if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004)) | |
547 | { | |
548 | outputf("3C90X: Tx Timeout"); | |
549 | continue; | |
550 | } | |
551 | ||
552 | status = inb(INF_3C90X.IOAddr + regTxStatus_b); | |
553 | ||
554 | /** acknowledge transmit interrupt by writing status **/ | |
555 | outb(0x00, INF_3C90X.IOAddr + regTxStatus_b); | |
556 | ||
557 | /** successful completion (sans "interrupt Requested" bit) **/ | |
558 | if ((status & 0xbf) == 0x80) | |
559 | return; | |
560 | ||
561 | outputf("3C90X: Status (%hhX)", status); | |
562 | /** check error codes **/ | |
563 | if (status & 0x02) | |
564 | { | |
565 | outputf("3C90X: Tx Reclaim Error (%hhX)", status); | |
566 | a3c90x_reset(); | |
567 | } | |
568 | else if (status & 0x04) | |
569 | { | |
570 | outputf("3C90X: Tx Status Overflow (%hhX)", status); | |
571 | for (i=0; i<32; i++) | |
572 | outb(0x00, INF_3C90X.IOAddr + regTxStatus_b); | |
573 | /** must re-enable after max collisions before re-issuing tx **/ | |
574 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0); | |
575 | } | |
576 | else if (status & 0x08) | |
577 | { | |
578 | outputf("3C90X: Tx Max Collisions (%hhX)", status); | |
579 | /** must re-enable after max collisions before re-issuing tx **/ | |
580 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0); | |
581 | } | |
582 | else if (status & 0x10) | |
583 | { | |
584 | outputf("3C90X: Tx Underrun (%hhX)", status); | |
585 | a3c90x_reset(); | |
586 | } | |
587 | else if (status & 0x20) | |
588 | { | |
589 | outputf("3C90X: Tx Jabber (%hhX)", status); | |
590 | a3c90x_reset(); | |
591 | } | |
592 | else if ((status & 0x80) != 0x80) | |
593 | { | |
594 | outputf("3C90X: Internal Error - Incomplete Transmission (%hhX)", | |
595 | status); | |
596 | a3c90x_reset(); | |
597 | } | |
598 | } | |
599 | ||
600 | /** failed after RETRY attempts **/ | |
601 | outputf("Failed to send after %d retries", retries); | |
602 | return; | |
603 | ||
604 | } | |
605 | ||
606 | ||
607 | ||
608 | /*** a3c90x_poll: exported routine that waits for a certain length of time | |
609 | *** for a packet, and if it sees none, returns 0. This routine should | |
610 | *** copy the packet to nic->packet if it gets a packet and set the size | |
611 | *** in nic->packetlen. Return 1 if a packet was found. | |
612 | ***/ | |
613 | static int | |
614 | a3c90x_poll(struct nic *nic, int retrieve) | |
615 | { | |
616 | int i, errcode; | |
617 | ||
618 | if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010)) | |
619 | { | |
620 | return 0; | |
621 | } | |
622 | ||
623 | if ( ! retrieve ) return 1; | |
624 | ||
625 | /** we don't need to acknowledge rxComplete -- the upload engine | |
626 | ** does it for us. | |
627 | **/ | |
628 | ||
629 | /** Build the up-load descriptor **/ | |
630 | INF_3C90X.ReceiveUPD.UpNextPtr = 0; | |
631 | INF_3C90X.ReceiveUPD.UpPktStatus = 0; | |
632 | INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet); | |
633 | INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31); | |
634 | ||
635 | /** Submit the upload descriptor to the NIC **/ | |
636 | outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)), | |
637 | INF_3C90X.IOAddr + regUpListPtr_l); | |
638 | ||
639 | /** Wait for upload completion (upComplete(15) or upError (14)) **/ | |
640 | for(i=0;i<40000;i++); | |
641 | while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0) | |
642 | for(i=0;i<40000;i++); | |
643 | ||
644 | /** Check for Error (else we have good packet) **/ | |
645 | if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14)) | |
646 | { | |
647 | errcode = INF_3C90X.ReceiveUPD.UpPktStatus; | |
648 | if (errcode & (1<<16)) | |
649 | outputf("3C90X: Rx Overrun (%hX)",errcode>>16); | |
650 | else if (errcode & (1<<17)) | |
651 | outputf("3C90X: Runt Frame (%hX)",errcode>>16); | |
652 | else if (errcode & (1<<18)) | |
653 | outputf("3C90X: Alignment Error (%hX)",errcode>>16); | |
654 | else if (errcode & (1<<19)) | |
655 | outputf("3C90X: CRC Error (%hX)",errcode>>16); | |
656 | else if (errcode & (1<<20)) | |
657 | outputf("3C90X: Oversized Frame (%hX)",errcode>>16); | |
658 | else | |
659 | outputf("3C90X: Packet error (%hX)",errcode>>16); | |
660 | return 0; | |
661 | } | |
662 | ||
663 | /** Ok, got packet. Set length in nic->packetlen. **/ | |
664 | nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF); | |
665 | ||
666 | return 1; | |
667 | } | |
668 | ||
669 | ||
670 | ||
671 | /*** a3c90x_disable: exported routine to disable the card. What's this for? | |
672 | *** the eepro100.c driver didn't have one, so I just left this one empty too. | |
673 | *** Ideas anyone? | |
674 | *** Must turn off receiver at least so stray packets will not corrupt memory | |
675 | *** [Ken] | |
676 | ***/ | |
677 | void a3c90x_disable(struct dev *dev) | |
678 | { | |
679 | /* reset and disable merge */ | |
680 | a3c90x_reset(); | |
681 | /* Disable the receiver and transmitter. */ | |
682 | outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w); | |
683 | outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w); | |
684 | } | |
685 | ||
686 | ||
687 | /*** a3c90x_probe: exported routine to probe for the 3c905 card and perform | |
688 | *** initialization. If this routine is called, the pci functions did find the | |
689 | *** card. We just have to init it here. | |
690 | ***/ | |
691 | static int a3c90x_probe(struct pci_dev * pci, void * data) | |
692 | { | |
748534f4 JP |
693 | INF_3C90X.is3c556 = (pci->did == 0x6055); |
694 | ||
695 | int i, c; | |
696 | unsigned short eeprom[0x21]; | |
697 | unsigned int cfg; | |
698 | unsigned int mopt; | |
699 | unsigned int mstat; | |
700 | unsigned short linktype; | |
701 | #define HWADDR_OFFSET 10 | |
702 | ||
703 | unsigned long ioaddr = 0; | |
704 | for (i = 0; i < 6; i++) { | |
705 | if (pci->bars[i].type == PCI_BAR_IO) { | |
706 | ioaddr = pci->bars[i].addr; | |
707 | break; | |
708 | } | |
709 | } | |
710 | ||
711 | if (ioaddr == 0) | |
712 | return 0; | |
713 | /* | |
714 | adjust_pci_dev(pci); | |
715 | */ | |
42125f27 JP |
716 | nic.ioaddr = ioaddr & ~3; |
717 | nic.irqno = 0; | |
748534f4 JP |
718 | |
719 | INF_3C90X.IOAddr = ioaddr & ~3; | |
720 | INF_3C90X.CurrentWindow = 255; | |
721 | switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03)) | |
722 | { | |
723 | case 0x9000: /** 10 Base TPO **/ | |
724 | case 0x9001: /** 10/100 T4 **/ | |
725 | case 0x9050: /** 10/100 TPO **/ | |
726 | case 0x9051: /** 10 Base Combo **/ | |
727 | INF_3C90X.isBrev = 0; | |
728 | break; | |
729 | ||
730 | case 0x9004: /** 10 Base TPO **/ | |
731 | case 0x9005: /** 10 Base Combo **/ | |
732 | case 0x9006: /** 10 Base TPO and Base2 **/ | |
733 | case 0x900A: /** 10 Base FL **/ | |
734 | case 0x9055: /** 10/100 TPO **/ | |
735 | case 0x9056: /** 10/100 T4 **/ | |
736 | case 0x905A: /** 10 Base FX **/ | |
737 | default: | |
738 | INF_3C90X.isBrev = 1; | |
739 | break; | |
740 | } | |
741 | ||
742 | /** Load the EEPROM contents **/ | |
743 | if (INF_3C90X.isBrev) | |
744 | { | |
745 | for(i=0;i<=0x20;i++) | |
746 | { | |
747 | eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i); | |
748 | } | |
749 | ||
750 | #ifdef CFG_3C90X_BOOTROM_FIX | |
751 | /** Set xcvrSelect in InternalConfig in eeprom. **/ | |
752 | /* only necessary for 3c905b revision cards with boot PROM bug!!! */ | |
753 | a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160); | |
754 | #endif | |
755 | ||
756 | #ifdef CFG_3C90X_XCVR | |
757 | if (CFG_3C90X_XCVR == 255) | |
758 | { | |
759 | /** Clear the LanWorks register **/ | |
760 | a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0); | |
761 | } | |
762 | else | |
763 | { | |
764 | /** Set the selected permanent-xcvrSelect in the | |
765 | ** LanWorks register | |
766 | **/ | |
767 | a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, | |
768 | XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F)); | |
769 | } | |
770 | #endif | |
771 | } | |
772 | else | |
773 | { | |
774 | for(i=0;i<=0x17;i++) | |
775 | { | |
776 | eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i); | |
777 | } | |
778 | } | |
779 | ||
780 | /** Print identification message **/ | |
781 | #ifdef CFG_3C90X_BOOTROM_FIX | |
782 | if (INF_3C90X.isBrev) | |
783 | { | |
784 | outputf("NOTE: 3c905b bootrom fix enabled; has side " | |
785 | "effects. See 3c90x.txt for info."); | |
786 | } | |
787 | #endif | |
788 | ||
789 | /** Retrieve the Hardware address and print it on the screen. **/ | |
790 | INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8; | |
791 | INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF; | |
792 | INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8; | |
793 | INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF; | |
794 | INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8; | |
795 | INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF; | |
796 | outputf("MAC Address = %!", INF_3C90X.HWAddr); | |
797 | ||
798 | /** 3C556: Invert MII power **/ | |
799 | if (INF_3C90X.is3c556) { | |
800 | unsigned int tmp; | |
801 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2); | |
802 | tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w); | |
803 | tmp |= 0x4000; | |
804 | outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w); | |
805 | } | |
806 | ||
807 | /* Test if the link is good, if not continue */ | |
808 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winDiagnostics4); | |
809 | mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w); | |
810 | if((mstat & (1<<11)) == 0) { | |
811 | outputf("Valid link not established"); | |
812 | return 0; | |
813 | } | |
814 | ||
815 | /** Program the MAC address into the station address registers **/ | |
816 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2); | |
817 | outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w); | |
818 | outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2); | |
819 | outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4); | |
820 | outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0); | |
821 | outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2); | |
822 | outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4); | |
823 | ||
824 | /** Fill in our entry in the etherboot arp table **/ | |
825 | /* XXX ? for lwip? | |
826 | for(i=0;i<ETH_ALEN;i++) | |
42125f27 | 827 | nic.node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff; |
748534f4 JP |
828 | */ |
829 | ||
830 | /** Read the media options register, print a message and set default | |
831 | ** xcvr. | |
832 | ** | |
833 | ** Uses Media Option command on B revision, Reset Option on non-B | |
834 | ** revision cards -- same register address | |
835 | **/ | |
836 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3); | |
837 | mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w); | |
838 | ||
839 | /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/ | |
840 | if (! INF_3C90X.isBrev) | |
841 | { | |
842 | mopt &= 0x7F; | |
843 | } | |
844 | ||
845 | outputf("Connectors present: "); | |
846 | c = 0; | |
847 | linktype = 0x0008; | |
848 | if (mopt & 0x01) | |
849 | { | |
850 | outputf("%s100Base-T4",(c++)?", ":""); | |
851 | linktype = 0x0006; | |
852 | } | |
853 | if (mopt & 0x04) | |
854 | { | |
855 | outputf("%s100Base-FX",(c++)?", ":""); | |
856 | linktype = 0x0005; | |
857 | } | |
858 | if (mopt & 0x10) | |
859 | { | |
860 | outputf("%s10Base-2",(c++)?", ":""); | |
861 | linktype = 0x0003; | |
862 | } | |
863 | if (mopt & 0x20) | |
864 | { | |
865 | outputf("%sAUI",(c++)?", ":""); | |
866 | linktype = 0x0001; | |
867 | } | |
868 | if (mopt & 0x40) | |
869 | { | |
870 | outputf("%sMII",(c++)?", ":""); | |
871 | linktype = 0x0006; | |
872 | } | |
873 | if ((mopt & 0xA) == 0xA) | |
874 | { | |
875 | outputf("%s10Base-T / 100Base-TX",(c++)?", ":""); | |
876 | linktype = 0x0008; | |
877 | } | |
878 | else if ((mopt & 0xA) == 0x2) | |
879 | { | |
880 | outputf("%s100Base-TX",(c++)?", ":""); | |
881 | linktype = 0x0008; | |
882 | } | |
883 | else if ((mopt & 0xA) == 0x8) | |
884 | { | |
885 | outputf("%s10Base-T",(c++)?", ":""); | |
886 | linktype = 0x0008; | |
887 | } | |
888 | outputf("."); | |
889 | ||
890 | /** Determine transceiver type to use, depending on value stored in | |
891 | ** eeprom 0x16 | |
892 | **/ | |
893 | if (INF_3C90X.isBrev) | |
894 | { | |
895 | if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC) | |
896 | { | |
897 | /** User-defined **/ | |
898 | linktype = eeprom[0x16] & 0x000F; | |
899 | } | |
900 | } | |
901 | else | |
902 | { | |
903 | #ifdef CFG_3C90X_XCVR | |
904 | if (CFG_3C90X_XCVR != 255) | |
905 | linktype = CFG_3C90X_XCVR; | |
906 | #endif /* CFG_3C90X_XCVR */ | |
907 | ||
908 | /** I don't know what MII MAC only mode is!!! **/ | |
909 | if (linktype == 0x0009) | |
910 | { | |
911 | if (INF_3C90X.isBrev) | |
912 | outputf("WARNING: MII External MAC Mode only supported on B-revision " | |
913 | "cards!!!!\nFalling Back to MII Mode\n"); | |
914 | linktype = 0x0006; | |
915 | } | |
916 | } | |
917 | ||
918 | /** enable DC converter for 10-Base-T **/ | |
919 | if (linktype == 0x0003) | |
920 | { | |
921 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0); | |
922 | } | |
923 | ||
924 | /** Set the link to the type we just determined. **/ | |
925 | a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3); | |
926 | cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l); | |
927 | cfg &= ~(0xF<<20); | |
928 | cfg |= (linktype<<20); | |
929 | outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l); | |
930 | ||
931 | /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/ | |
932 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0x00); | |
933 | while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS) | |
934 | ; | |
935 | ||
936 | if (!INF_3C90X.isBrev) | |
937 | outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b); | |
938 | ||
939 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0); | |
940 | ||
941 | /** | |
942 | ** reset of the receiver on B-revision cards re-negotiates the link | |
943 | ** takes several seconds (a computer eternity) | |
944 | **/ | |
945 | if (INF_3C90X.isBrev) | |
946 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04); | |
947 | else | |
948 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00); | |
949 | while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS) | |
950 | ; | |
951 | ||
952 | /** Set the RX filter = receive only individual pkts & multicast & bcast. **/ | |
953 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04); | |
954 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0); | |
955 | ||
956 | ||
957 | /** | |
958 | ** set Indication and Interrupt flags , acknowledge any IRQ's | |
959 | **/ | |
960 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0); | |
961 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, | |
962 | cmdSetIndicationEnable, 0x0014); | |
963 | a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, | |
964 | cmdAcknowledgeInterrupt, 0x661); | |
965 | ||
966 | /* * Set our exported functions **/ | |
42125f27 JP |
967 | nic.poll = a3c90x_poll; |
968 | nic.transmit = a3c90x_transmit; | |
748534f4 JP |
969 | |
970 | return 1; | |
971 | } | |
972 | ||
973 | static struct pci_id a3c90x_nics[] = { | |
974 | /* Original 90x revisions: */ | |
975 | PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */ | |
976 | PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */ | |
977 | PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */ | |
978 | PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */ | |
979 | PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */ | |
980 | /* Newer 90xB revisions: */ | |
981 | PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */ | |
982 | PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */ | |
983 | PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */ | |
984 | PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */ | |
985 | PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */ | |
986 | PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */ | |
987 | PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */ | |
988 | PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */ | |
989 | /* Newer 90xC revision: */ | |
990 | PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */ | |
991 | PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */ | |
992 | PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"), | |
993 | PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */ | |
994 | PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */ | |
995 | PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */ | |
996 | PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"), | |
997 | PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"), | |
998 | PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"), | |
999 | }; | |
1000 | ||
1001 | struct pci_driver a3c90x_driver = { | |
1002 | .name = "3C90X", | |
1003 | .probe = a3c90x_probe, | |
1004 | .ids = a3c90x_nics, | |
1005 | .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]), | |
1006 | }; |