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Fix 'i r retard' bug in timer
[netwatch.git] / net / 3c90x.c
CommitLineData
748534f4
JP		 1/*
2 * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
3 * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
4 * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
5 *
6 * This program Copyright (C) 1999 LightSys Technology Services, Inc.
7 * Portions Copyright (C) 1999 Steve Smith
8 *
9 * This program may be re-distributed in source or binary form, modified,
10 * sold, or copied for any purpose, provided that the above copyright message
11 * and this text are included with all source copies or derivative works, and
12 * provided that the above copyright message and this text are included in the
13 * documentation of any binary-only distributions. This program is distributed
14 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
15 * PURPOSE or MERCHANTABILITY. Please read the associated documentation
16 * "3c90x.txt" before compiling and using this driver.
17 *
18 * --------
19 *
20 * Program written with the assistance of the 3com documentation for
21 * the 3c905B-TX card, as well as with some assistance from the 3c59x
22 * driver Donald Becker wrote for the Linux kernel, and with some assistance
23 * from the remainder of the Etherboot distribution.
24 *
25 * REVISION HISTORY:
26 *
27 * v0.10 1-26-1998 GRB Initial implementation.
28 * v0.90 1-27-1998 GRB System works.
29 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31 * Re-wrote poll and transmit for
32 * better error recovery and heavy
33 * network traffic operation
34 * v2.01 5-26-2003 NN Fixed driver alignment issue which
35 * caused system lockups if driver structures
36 * not 8-byte aligned.
37 *
38 */
39
40#include "etherboot-compat.h"
42125f27 41#include "net.h"
748534f4
JP		 42#include <timer.h>
43#include <io.h>
44#include <pci.h>
7a914840 45#include <pci-bother.h>
748534f4
JP		 46#include <minilib.h>
47#include <output.h>
48
49#define XCVR_MAGIC (0x5A00)
50/** any single transmission fails after 16 collisions or other errors
51 ** this is the number of times to retry the transmission -- this should
52 ** be plenty
53 **/
54#define XMIT_RETRIES 250
55
56/*** Register definitions for the 3c905 ***/
57enum Registers
58 {
59 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
60 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
61 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
62 regDebugControl_w = 0x74, /** 905B Revision Only **/
63 regDebugData_l = 0x70, /** 905B Revision Only **/
64 regRealTimeCnt_l = 0x40, /** Universal **/
65 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
66 regUpPoll_b = 0x3d, /** 905B Revision Only **/
67 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
68 regUpListPtr_l = 0x38, /** Universal **/
69 regCountdown_w = 0x36, /** Universal **/
70 regFreeTimer_w = 0x34, /** Universal **/
71 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
72 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
73 regDnPoll_b = 0x2d, /** 905B Revision Only **/
74 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
75 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
76 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
77 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
78 /** **/
79 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
80 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
81 regTimer_b = 0x1a, /** Universal **/
82 regTxPktId_b = 0x18, /** 905B Revision Only **/
83 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
84 };
85
86/** following are windowed registers **/
87enum Registers7
88 {
89 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
90 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
91 regVlanMask_7_w = 0x00, /** 905B Revision Only **/
92 };
93
94enum Registers6
95 {
96 regBytesXmittedOk_6_w = 0x0c, /** Universal **/
97 regBytesRcvdOk_6_w = 0x0a, /** Universal **/
98 regUpperFramesOk_6_b = 0x09, /** Universal **/
99 regFramesDeferred_6_b = 0x08, /** Universal **/
100 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
101 regFramesXmittedOk_6_b = 0x06, /** Universal **/
102 regRxOverruns_6_b = 0x05, /** Universal **/
103 regLateCollisions_6_b = 0x04, /** Universal **/
104 regSingleCollisions_6_b = 0x03, /** Universal **/
105 regMultipleCollisions_6_b = 0x02, /** Universal **/
106 regSqeErrors_6_b = 0x01, /** Universal **/
107 regCarrierLost_6_b = 0x00, /** Universal **/
108 };
109
110enum Registers5
111 {
112 regIndicationEnable_5_w = 0x0c, /** Universal **/
113 regInterruptEnable_5_w = 0x0a, /** Universal **/
114 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
115 regRxFilter_5_b = 0x08, /** Universal **/
116 regRxEarlyThresh_5_w = 0x06, /** Universal **/
117 regTxStartThresh_5_w = 0x00, /** Universal **/
118 };
119
120enum Registers4
121 {
122 regUpperBytesOk_4_b = 0x0d, /** Universal **/
123 regBadSSD_4_b = 0x0c, /** Universal **/
124 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
125 regPhysicalMgmt_4_w = 0x08, /** Universal **/
126 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
127 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
128 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
129 };
130
131enum Registers3
132 {
133 regTxFree_3_w = 0x0c, /** Universal **/
134 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
135 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
136 /** Reset Options on Non-B Revision **/
137 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
138 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
139 regInternalConfig_3_l = 0x00, /** Universal, different bit **/
140 /** definitions, pg 59 **/
141 };
142
143enum Registers2
144 {
145 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
146 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
147 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
148 };
149
150enum Registers1
151 {
152 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
153 };
154
155enum Registers0
156 {
157 regEepromData_0_w = 0x0c, /** Universal **/
158 regEepromCommand_0_w = 0x0a, /** Universal **/
159 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
160 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
161 };
162
163
164/*** The names for the eight register windows ***/
165enum Windows
166 {
167 winPowerVlan7 = 0x07,
168 winStatistics6 = 0x06,
169 winTxRxControl5 = 0x05,
170 winDiagnostics4 = 0x04,
171 winTxRxOptions3 = 0x03,
172 winAddressing2 = 0x02,
173 winUnused1 = 0x01,
174 winEepromBios0 = 0x00,
175 };
176
177
178/*** Command definitions for the 3c90X ***/
179enum Commands
180 {
181 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
182 cmdSelectRegisterWindow = 0x01, /** Universal **/
183 cmdEnableDcConverter = 0x02, /** **/
184 cmdRxDisable = 0x03, /** **/
185 cmdRxEnable = 0x04, /** Universal **/
186 cmdRxReset = 0x05, /** Universal **/
187 cmdStallCtl = 0x06, /** Universal **/
188 cmdTxEnable = 0x09, /** Universal **/
189 cmdTxDisable = 0x0A, /** **/
190 cmdTxReset = 0x0B, /** Universal **/
191 cmdRequestInterrupt = 0x0C, /** **/
192 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
193 cmdSetInterruptEnable = 0x0E, /** Universal **/
194 cmdSetIndicationEnable = 0x0F, /** Universal **/
195 cmdSetRxFilter = 0x10, /** Universal **/
196 cmdSetRxEarlyThresh = 0x11, /** **/
197 cmdSetTxStartThresh = 0x13, /** **/
198 cmdStatisticsEnable = 0x15, /** **/
199 cmdStatisticsDisable = 0x16, /** **/
200 cmdDisableDcConverter = 0x17, /** **/
201 cmdSetTxReclaimThresh = 0x18, /** **/
202 cmdSetHashFilterBit = 0x19, /** **/
203 };
204
205
206/*** Values for int status register bitmask **/
207#define INT_INTERRUPTLATCH (1<<0)
208#define INT_HOSTERROR (1<<1)
209#define INT_TXCOMPLETE (1<<2)
210#define INT_RXCOMPLETE (1<<4)
211#define INT_RXEARLY (1<<5)
212#define INT_INTREQUESTED (1<<6)
213#define INT_UPDATESTATS (1<<7)
214#define INT_LINKEVENT (1<<8)
215#define INT_DNCOMPLETE (1<<9)
216#define INT_UPCOMPLETE (1<<10)
217#define INT_CMDINPROGRESS (1<<12)
218#define INT_WINDOWNUMBER (7<<13)
219
220
221/*** TX descriptor ***/
222typedef struct
223 {
224 unsigned int DnNextPtr;
225 unsigned int FrameStartHeader;
226 unsigned int HdrAddr;
227 unsigned int HdrLength;
228 unsigned int DataAddr;
229 unsigned int DataLength;
230 }
231 TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
232
233/*** RX descriptor ***/
234typedef struct
235 {
236 unsigned int UpNextPtr;
237 unsigned int UpPktStatus;
238 unsigned int DataAddr;
239 unsigned int DataLength;
240 }
241 RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
242
243/*** Global variables ***/
244static struct
245 {
246 unsigned int is3c556;
247 unsigned char isBrev;
248 unsigned char CurrentWindow;
249 unsigned int IOAddr;
250 unsigned char HWAddr[ETH_ALEN];
251 TXD TransmitDPD;
252 RXD ReceiveUPD;
253 }
254 INF_3C90X;
7a914840 255static struct nic nic;
748534f4 256
c2e34447
JW		 257#define _outl(v,a) outl((a),(v))
258#define _outw(v,a) outw((a),(v))
259#define _outb(v,a) outb((a),(v))
748534f4
JP		 260
261/*** a3c90x_internal_IssueCommand: sends a command to the 3c90x card
262 ***/
263static int
264a3c90x_internal_IssueCommand(int ioaddr, int cmd, int param)
265 {
266 unsigned int val;
267
268 /** Build the cmd. **/
269 val = cmd;
270 val <<= 11;
271 val |= param;
272
273 /** Send the cmd to the cmd register **/
c2e34447 274 _outw(val, ioaddr + regCommandIntStatus_w);
748534f4
JP		 275
276 /** Wait for the cmd to complete, if necessary **/
277 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
278
279 return 0;
280 }
281
282
283/*** a3c90x_internal_SetWindow: selects a register window set.
284 ***/
285static int
286a3c90x_internal_SetWindow(int ioaddr, int window)
287 {
288
289 /** Window already as set? **/
290 if (INF_3C90X.CurrentWindow == window) return 0;
291
292 /** Issue the window command. **/
293 a3c90x_internal_IssueCommand(ioaddr, cmdSelectRegisterWindow, window);
294 INF_3C90X.CurrentWindow = window;
295
296 return 0;
297 }
298
299
300/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
301 ***/
302static unsigned short
303a3c90x_internal_ReadEeprom(int ioaddr, int address)
c2e34447
JW		 304{
305 unsigned short val;
748534f4
JP		 306
307 /** Select correct window **/
308 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winEepromBios0);
309
310 /** Make sure the eeprom isn't busy **/
c2e34447
JW		 311 do
312 {
313 int i;
314 for (i = 0; i < 165; i++)
315 inb(0x80); /* wait 165 usec */
316 }
317 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
748534f4
JP		 318
319 /** Read the value. **/
320 if (INF_3C90X.is3c556)
c2e34447 321 _outw(address + (0x230), ioaddr + regEepromCommand_0_w);
748534f4 322 else
c2e34447 323 _outw(address + 0x80, ioaddr + regEepromCommand_0_w);
748534f4 324
c2e34447
JW		 325 do
326 {
327 int i;
328 for (i = 0; i < 165; i++)
329 inb(0x80); /* wait 165 usec */
330 }
331 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
332 val = inw(ioaddr + regEepromData_0_w);
333
334 return val;
335}
748534f4
JP		 336
337
338#ifdef CFG_3C90X_BOOTROM_FIX
339/*** a3c90x_internal_WriteEepromWord - write a physical word of
340 *** data to the onboard serial eeprom (not the BIOS prom, but the
341 *** nvram in the card that stores, among other things, the MAC
342 *** address).
343 ***/
344static int
345a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
346 {
347 /** Select register window **/
348 a3c90x_internal_SetWindow(ioaddr, winEepromBios0);
349
350 /** Verify Eeprom not busy **/
351 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
352
353 /** Issue WriteEnable, and wait for completion. **/
c2e34447 354 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 355 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
356
357 /** Issue EraseRegister, and wait for completion. **/
c2e34447 358 _outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 359 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
360
361 /** Send the new data to the eeprom, and wait for completion. **/
c2e34447
JW		 362 _outw(value, ioaddr + regEepromData_0_w);
363 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 364 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
365
366 /** Burn the new data into the eeprom, and wait for completion. **/
c2e34447 367 _outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 368 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
369
370 return 0;
371 }
372#endif
373
374#ifdef CFG_3C90X_BOOTROM_FIX
375/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
376 *** and re-compute the eeprom checksum.
377 ***/
378static int
379a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
380 {
381 int cksum = 0,v;
382 int i;
383 int maxAddress, cksumAddress;
384
385 if (INF_3C90X.isBrev)
386 {
387 maxAddress=0x1f;
388 cksumAddress=0x20;
389 }
390 else
391 {
392 maxAddress=0x16;
393 cksumAddress=0x17;
394 }
395
396 /** Write the value. **/
397 if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
398 return -1;
399
400 /** Recompute the checksum. **/
401 for(i=0;i<=maxAddress;i++)
402 {
403 v = a3c90x_internal_ReadEeprom(ioaddr, i);
404 cksum ^= (v & 0xFF);
405 cksum ^= ((v>>8) & 0xFF);
406 }
407 /** Write the checksum to the location in the eeprom **/
408 if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
409 return -1;
410
411 return 0;
412 }
413#endif
414
415/*** a3c90x_reset: exported function that resets the card to its default
416 *** state. This is so the Linux driver can re-set the card up the way
417 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
418 *** not alter the selected transceiver that we used to download the boot
419 *** image.
420 ***/
421static void a3c90x_reset(void)
422 {
423#ifdef CFG_3C90X_PRESERVE_XCVR
424 int cfg;
425 /** Read the current InternalConfig value. **/
426 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
427 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
428#endif
429
430 /** Send the reset command to the card **/
99182958 431 outputf("3c90x: issuing RESET");
748534f4
JP		 432 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdGlobalReset, 0);
433
434 /** wait for reset command to complete **/
435 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
436
437 /** global reset command resets station mask, non-B revision cards
438 ** require explicit reset of values
439 **/
440 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 441 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
442 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
443 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 444
445#ifdef CFG_3C90X_PRESERVE_XCVR
446 /** Re-set the original InternalConfig value from before reset **/
447 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
c2e34447 448 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 449
450 /** enable DC converter for 10-Base-T **/
451 if ((cfg&0x0300) == 0x0300)
452 {
453 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
454 }
455#endif
456
457 /** Issue transmit reset, wait for command completion **/
458 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0);
459 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
460 ;
461 if (! INF_3C90X.isBrev)
c2e34447 462 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
748534f4
JP		 463 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
464
465 /**
466 ** reset of the receiver on B-revision cards re-negotiates the link
467 ** takes several seconds (a computer eternity)
468 **/
469 if (INF_3C90X.isBrev)
470 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
471 else
472 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
473 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS);
474 ;
475 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
476
477 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
478 cmdSetInterruptEnable, 0);
479 /** enable rxComplete and txComplete **/
480 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
481 cmdSetIndicationEnable, 0x0014);
482 /** acknowledge any pending status flags **/
483 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
484 cmdAcknowledgeInterrupt, 0x661);
485
486 return;
487 }
488
489
490
491/*** a3c90x_transmit: exported function that transmits a packet. Does not
492 *** return any particular status. Parameters are:
493 *** dest_addr[6] - destination address, ethernet;
494 *** proto - protocol type (ARP, IP, etc);
495 *** size - size of the non-header part of the packet that needs transmitted;
496 *** pkt - the pointer to the packet data itself.
497 ***/
498static void
499a3c90x_transmit(const char *dest_addr, unsigned int proto,
500 unsigned int size, const char *pkt)
501 {
502
503 struct eth_hdr
504 {
505 unsigned char dst_addr[ETH_ALEN];
506 unsigned char src_addr[ETH_ALEN];
507 unsigned short type;
508 } hdr;
509
510 unsigned char status;
511 unsigned i, retries;
512
513 for (retries=0; retries < XMIT_RETRIES ; retries++)
514 {
515 /** Stall the download engine **/
516 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 2);
517
518 /** Make sure the card is not waiting on us **/
519 inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
520 inw(INF_3C90X.IOAddr + regCommandIntStatus_w);
521
522 while (inw(INF_3C90X.IOAddr+regCommandIntStatus_w) &
523 INT_CMDINPROGRESS)
524 ;
525
526 /** Set the ethernet packet type **/
527 hdr.type = htons(proto);
528
529 /** Copy the destination address **/
530 memcpy(hdr.dst_addr, dest_addr, ETH_ALEN);
531
532 /** Copy our MAC address **/
533 memcpy(hdr.src_addr, INF_3C90X.HWAddr, ETH_ALEN);
534
535 /** Setup the DPD (download descriptor) **/
536 INF_3C90X.TransmitDPD.DnNextPtr = 0;
537 /** set notification for transmission completion (bit 15) **/
538 INF_3C90X.TransmitDPD.FrameStartHeader = (size + sizeof(hdr)) | 0x8000;
539 INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr);
540 INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr);
541 INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(pkt);
542 INF_3C90X.TransmitDPD.DataLength = size + (1<<31);
543
544 /** Send the packet **/
c2e34447 545 _outl(virt_to_bus(&(INF_3C90X.TransmitDPD)),
748534f4
JP		 546 INF_3C90X.IOAddr + regDnListPtr_l);
547
548 /** End Stall and Wait for upload to complete. **/
549 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdStallCtl, 3);
550 while(inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
551 ;
552
553 /** Wait for NIC Transmit to Complete **/
554 oneshot_start_ms(10); /* Give it 10 ms */
555 while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004) &&
556 oneshot_running())
557 ;
558
559 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0004))
560 {
561 outputf("3C90X: Tx Timeout");
562 continue;
563 }
564
565 status = inb(INF_3C90X.IOAddr + regTxStatus_b);
566
567 /** acknowledge transmit interrupt by writing status **/
c2e34447 568 _outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
748534f4
JP		 569
570 /** successful completion (sans "interrupt Requested" bit) **/
571 if ((status & 0xbf) == 0x80)
572 return;
573
574 outputf("3C90X: Status (%hhX)", status);
575 /** check error codes **/
576 if (status & 0x02)
577 {
578 outputf("3C90X: Tx Reclaim Error (%hhX)", status);
579 a3c90x_reset();
580 }
581 else if (status & 0x04)
582 {
583 outputf("3C90X: Tx Status Overflow (%hhX)", status);
584 for (i=0; i<32; i++)
c2e34447 585 _outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
748534f4
JP		 586 /** must re-enable after max collisions before re-issuing tx **/
587 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
588 }
589 else if (status & 0x08)
590 {
591 outputf("3C90X: Tx Max Collisions (%hhX)", status);
592 /** must re-enable after max collisions before re-issuing tx **/
593 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
594 }
595 else if (status & 0x10)
596 {
597 outputf("3C90X: Tx Underrun (%hhX)", status);
598 a3c90x_reset();
599 }
600 else if (status & 0x20)
601 {
602 outputf("3C90X: Tx Jabber (%hhX)", status);
603 a3c90x_reset();
604 }
605 else if ((status & 0x80) != 0x80)
606 {
607 outputf("3C90X: Internal Error - Incomplete Transmission (%hhX)",
608 status);
609 a3c90x_reset();
610 }
611 }
612
613 /** failed after RETRY attempts **/
614 outputf("Failed to send after %d retries", retries);
615 return;
616
617 }
618
619
620
621/*** a3c90x_poll: exported routine that waits for a certain length of time
622 *** for a packet, and if it sees none, returns 0. This routine should
623 *** copy the packet to nic->packet if it gets a packet and set the size
624 *** in nic->packetlen. Return 1 if a packet was found.
625 ***/
626static int
627a3c90x_poll(struct nic *nic, int retrieve)
628 {
629 int i, errcode;
630
631 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
632 {
633 return 0;
634 }
635
636 if ( ! retrieve ) return 1;
637
638 /** we don't need to acknowledge rxComplete -- the upload engine
639 ** does it for us.
640 **/
641
642 /** Build the up-load descriptor **/
643 INF_3C90X.ReceiveUPD.UpNextPtr = 0;
644 INF_3C90X.ReceiveUPD.UpPktStatus = 0;
645 INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet);
646 INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
647
648 /** Submit the upload descriptor to the NIC **/
c2e34447 649 _outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)),
748534f4
JP		 650 INF_3C90X.IOAddr + regUpListPtr_l);
651
652 /** Wait for upload completion (upComplete(15) or upError (14)) **/
653 for(i=0;i<40000;i++);
654 while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
655 for(i=0;i<40000;i++);
656
657 /** Check for Error (else we have good packet) **/
658 if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
659 {
660 errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
661 if (errcode & (1<<16))
662 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);
663 else if (errcode & (1<<17))
664 outputf("3C90X: Runt Frame (%hX)",errcode>>16);
665 else if (errcode & (1<<18))
666 outputf("3C90X: Alignment Error (%hX)",errcode>>16);
667 else if (errcode & (1<<19))
668 outputf("3C90X: CRC Error (%hX)",errcode>>16);
669 else if (errcode & (1<<20))
670 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);
671 else
672 outputf("3C90X: Packet error (%hX)",errcode>>16);
673 return 0;
674 }
675
676 /** Ok, got packet. Set length in nic->packetlen. **/
677 nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
678
679 return 1;
680 }
681
682
683
684/*** a3c90x_disable: exported routine to disable the card. What's this for?
685 *** the eepro100.c driver didn't have one, so I just left this one empty too.
686 *** Ideas anyone?
687 *** Must turn off receiver at least so stray packets will not corrupt memory
688 *** [Ken]
689 ***/
690void a3c90x_disable(struct dev *dev)
691{
692 /* reset and disable merge */
693 a3c90x_reset();
694 /* Disable the receiver and transmitter. */
c2e34447
JW		 695 _outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
696 _outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
748534f4
JP		 697}
698
699
700/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
701 *** initialization. If this routine is called, the pci functions did find the
702 *** card. We just have to init it here.
703 ***/
704static int a3c90x_probe(struct pci_dev * pci, void * data)
705{
748534f4
JP		 706 INF_3C90X.is3c556 = (pci->did == 0x6055);
707
708 int i, c;
c2e34447 709 unsigned short eeprom[0x100];
748534f4
JP		 710 unsigned int cfg;
711 unsigned int mopt;
712 unsigned int mstat;
713 unsigned short linktype;
714#define HWADDR_OFFSET 10
715
716 unsigned long ioaddr = 0;
717 for (i = 0; i < 6; i++) {
718 if (pci->bars[i].type == PCI_BAR_IO) {
719 ioaddr = pci->bars[i].addr;
720 break;
721 }
722 }
723
724 if (ioaddr == 0)
c2e34447
JW		 725 {
726 outputf("3c90x: Unable to find I/O address");
727 return 0;
728 }
729
730 /* Power it on */
731 pci_write16(pci->bus, pci->dev, pci->fn, 0xE0,
732 pci_read16(pci->bus, pci->dev, pci->fn, 0xE0) & ~0x3);
733
734 outputf("3c90x: Picked I/O address %04x", ioaddr);
7a914840 735 pci_bother_add(pci);
42125f27
JP		 736 nic.ioaddr = ioaddr & ~3;
737 nic.irqno = 0;
748534f4 738
c2e34447 739 INF_3C90X.IOAddr = ioaddr;
748534f4
JP		 740 INF_3C90X.CurrentWindow = 255;
741 switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
742 {
743 case 0x9000: /** 10 Base TPO **/
744 case 0x9001: /** 10/100 T4 **/
745 case 0x9050: /** 10/100 TPO **/
746 case 0x9051: /** 10 Base Combo **/
747 INF_3C90X.isBrev = 0;
748 break;
749
750 case 0x9004: /** 10 Base TPO **/
751 case 0x9005: /** 10 Base Combo **/
752 case 0x9006: /** 10 Base TPO and Base2 **/
753 case 0x900A: /** 10 Base FL **/
754 case 0x9055: /** 10/100 TPO **/
755 case 0x9056: /** 10/100 T4 **/
756 case 0x905A: /** 10 Base FX **/
757 default:
758 INF_3C90X.isBrev = 1;
759 break;
760 }
761
762 /** Load the EEPROM contents **/
763 if (INF_3C90X.isBrev)
764 {
c2e34447 765 for(i=0;i<=/*0x20*/0x7F;i++)
748534f4
JP		 766 {
767 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
768 }
769
770#ifdef CFG_3C90X_BOOTROM_FIX
771 /** Set xcvrSelect in InternalConfig in eeprom. **/
772 /* only necessary for 3c905b revision cards with boot PROM bug!!! */
773 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
774#endif
775
776#ifdef CFG_3C90X_XCVR
777 if (CFG_3C90X_XCVR == 255)
778 {
779 /** Clear the LanWorks register **/
780 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
781 }
782 else
783 {
784 /** Set the selected permanent-xcvrSelect in the
785 ** LanWorks register
786 **/
787 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
788 XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
789 }
790#endif
791 }
792 else
793 {
c2e34447 794 for(i=0;i<=/*0x17*/0x7F;i++)
748534f4
JP		 795 {
796 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
797 }
798 }
799
800 /** Print identification message **/
801#ifdef CFG_3C90X_BOOTROM_FIX
802 if (INF_3C90X.isBrev)
803 {
804 outputf("NOTE: 3c905b bootrom fix enabled; has side "
805 "effects. See 3c90x.txt for info.");
806 }
807#endif
c2e34447
JW		 808 {
809 unsigned int tmp;
810 for (tmp = 0; tmp < 0x10; tmp+= 4)
811 outputf("EEPROM adr %02x, data %04x %04x %04x %04x",
812 tmp, eeprom[tmp], eeprom[tmp+1], eeprom[tmp+2], eeprom[tmp+3]);
813 }
814
815 /* Some type A... */
748534f4
JP		 816
817 /** Retrieve the Hardware address and print it on the screen. **/
818 INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
819 INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
820 INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
821 INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
822 INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
823 INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
c2e34447
JW		 824 outputf("MAC Address = %02x:%02x:%02x:%02x:%02x:%02x",
825 INF_3C90X.HWAddr[0],
826 INF_3C90X.HWAddr[1],
827 INF_3C90X.HWAddr[2],
828 INF_3C90X.HWAddr[3],
829 INF_3C90X.HWAddr[4],
830 INF_3C90X.HWAddr[5]);
748534f4
JP		 831
832 /** 3C556: Invert MII power **/
833 if (INF_3C90X.is3c556) {
834 unsigned int tmp;
835 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
836 tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
837 tmp |= 0x4000;
c2e34447 838 _outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
748534f4
JP		 839 }
840
841 /* Test if the link is good, if not continue */
842 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winDiagnostics4);
843 mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
844 if((mstat & (1<<11)) == 0) {
845 outputf("Valid link not established");
846 return 0;
847 }
848
849 /** Program the MAC address into the station address registers **/
850 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 851 _outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
852 _outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
853 _outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
854 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
855 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
856 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 857
858 /** Fill in our entry in the etherboot arp table **/
859/* XXX ? for lwip?
860 for(i=0;i<ETH_ALEN;i++)
42125f27 861 nic.node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
748534f4
JP		 862*/
863
864 /** Read the media options register, print a message and set default
865 ** xcvr.
866 **
867 ** Uses Media Option command on B revision, Reset Option on non-B
868 ** revision cards -- same register address
869 **/
870 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
871 mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
872
873 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
874 if (! INF_3C90X.isBrev)
875 {
876 mopt &= 0x7F;
877 }
878
879 outputf("Connectors present: ");
880 c = 0;
881 linktype = 0x0008;
882 if (mopt & 0x01)
883 {
884 outputf("%s100Base-T4",(c++)?", ":"");
885 linktype = 0x0006;
886 }
887 if (mopt & 0x04)
888 {
889 outputf("%s100Base-FX",(c++)?", ":"");
890 linktype = 0x0005;
891 }
892 if (mopt & 0x10)
893 {
894 outputf("%s10Base-2",(c++)?", ":"");
895 linktype = 0x0003;
896 }
897 if (mopt & 0x20)
898 {
899 outputf("%sAUI",(c++)?", ":"");
900 linktype = 0x0001;
901 }
902 if (mopt & 0x40)
903 {
904 outputf("%sMII",(c++)?", ":"");
905 linktype = 0x0006;
906 }
907 if ((mopt & 0xA) == 0xA)
908 {
909 outputf("%s10Base-T / 100Base-TX",(c++)?", ":"");
910 linktype = 0x0008;
911 }
912 else if ((mopt & 0xA) == 0x2)
913 {
914 outputf("%s100Base-TX",(c++)?", ":"");
915 linktype = 0x0008;
916 }
917 else if ((mopt & 0xA) == 0x8)
918 {
919 outputf("%s10Base-T",(c++)?", ":"");
920 linktype = 0x0008;
921 }
922 outputf(".");
923
924 /** Determine transceiver type to use, depending on value stored in
925 ** eeprom 0x16
926 **/
927 if (INF_3C90X.isBrev)
928 {
929 if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
930 {
931 /** User-defined **/
932 linktype = eeprom[0x16] & 0x000F;
933 }
934 }
935 else
936 {
937#ifdef CFG_3C90X_XCVR
938 if (CFG_3C90X_XCVR != 255)
939 linktype = CFG_3C90X_XCVR;
940#endif /* CFG_3C90X_XCVR */
941
942 /** I don't know what MII MAC only mode is!!! **/
943 if (linktype == 0x0009)
944 {
945 if (INF_3C90X.isBrev)
946 outputf("WARNING: MII External MAC Mode only supported on B-revision "
947 "cards!!!!\nFalling Back to MII Mode\n");
948 linktype = 0x0006;
949 }
950 }
951
952 /** enable DC converter for 10-Base-T **/
953 if (linktype == 0x0003)
954 {
955 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
956 }
957
958 /** Set the link to the type we just determined. **/
959 a3c90x_internal_SetWindow(INF_3C90X.IOAddr, winTxRxOptions3);
960 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
961 cfg &= ~(0xF<<20);
962 cfg |= (linktype<<20);
c2e34447 963 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 964
965 /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
966 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxReset, 0x00);
967 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
968 ;
969
970 if (!INF_3C90X.isBrev)
c2e34447 971 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
748534f4
JP		 972
973 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdTxEnable, 0);
974
975 /**
976 ** reset of the receiver on B-revision cards re-negotiates the link
977 ** takes several seconds (a computer eternity)
978 **/
979 if (INF_3C90X.isBrev)
980 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x04);
981 else
982 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxReset, 0x00);
983 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
984 ;
985
986 /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
987 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
988 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdRxEnable, 0);
989
990
991 /**
992 ** set Indication and Interrupt flags , acknowledge any IRQ's
993 **/
994 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
995 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
996 cmdSetIndicationEnable, 0x0014);
997 a3c90x_internal_IssueCommand(INF_3C90X.IOAddr,
998 cmdAcknowledgeInterrupt, 0x661);
999
1000 /* * Set our exported functions **/
42125f27
JP		 1001 nic.poll = a3c90x_poll;
1002 nic.transmit = a3c90x_transmit;
c2e34447 1003 eth_register(&nic);
748534f4
JP		 1004
1005 return 1;
1006}
1007
1008static struct pci_id a3c90x_nics[] = {
1009/* Original 90x revisions: */
1010PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
1011PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
1012PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
1013PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
1014PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
1015/* Newer 90xB revisions: */
1016PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
1017PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
1018PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
1019PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
1020PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
1021PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
1022PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
1023PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
1024/* Newer 90xC revision: */
1025PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
1026PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
1027PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
1028PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
1029PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
1030PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
1031PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
1032PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
1033PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
1034};
1035
1036struct pci_driver a3c90x_driver = {
1037 .name = "3C90X",
1038 .probe = a3c90x_probe,
1039 .ids = a3c90x_nics,
1040 .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
1041};
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