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Tweak some values up a bit. Try harder to unstall the upload engine. Remove dead...
[netwatch.git] / net / 3c90x.c
CommitLineData
748534f4 1/*
421ccff4
JW		 2 * 3c90x.c
3 * NetWatch
748534f4 4 *
421ccff4
JW		 5 * A ring buffer-based, bus-mastering Ethernet driver.
6 *
7 * Derived from Etherboot's 3c90x.c, which is
8 * Copyright (C) 1999 LightSys Technology Services, Inc.
9 * Portions Copyright (C) 1999 Steve Smith
748534f4
JP		 10 *
11 * This program may be re-distributed in source or binary form, modified,
12 * sold, or copied for any purpose, provided that the above copyright message
13 * and this text are included with all source copies or derivative works, and
14 * provided that the above copyright message and this text are included in the
15 * documentation of any binary-only distributions. This program is distributed
16 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
17 * PURPOSE or MERCHANTABILITY. Please read the associated documentation
18 * "3c90x.txt" before compiling and using this driver.
19 *
748534f4
JP		 20 * REVISION HISTORY:
21 *
22 * v0.10 1-26-1998 GRB Initial implementation.
23 * v0.90 1-27-1998 GRB System works.
24 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
25 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
26 * Re-wrote poll and transmit for
27 * better error recovery and heavy
28 * network traffic operation
421ccff4
JW		 29 * v2.01 5-26-2003 NN Fixed driver alignment issue which
30 * caused system lockups if driver structures
31 * not 8-byte aligned.
32 * NetWatch0 12-07-2008 JAW Taken out back and shot.
748534f4
JP		 33 *
34 */
35
36#include "etherboot-compat.h"
42125f27 37#include "net.h"
748534f4
JP		 38#include <timer.h>
39#include <io.h>
40#include <pci.h>
7a914840 41#include <pci-bother.h>
748534f4
JP		 42#include <minilib.h>
43#include <output.h>
68beefa8 44#include <paging.h>
748534f4
JP		 45
46#define XCVR_MAGIC (0x5A00)
748534f4
JP		 47
48/*** Register definitions for the 3c905 ***/
49enum Registers
50 {
51 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
52 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
53 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
54 regDebugControl_w = 0x74, /** 905B Revision Only **/
55 regDebugData_l = 0x70, /** 905B Revision Only **/
56 regRealTimeCnt_l = 0x40, /** Universal **/
57 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
58 regUpPoll_b = 0x3d, /** 905B Revision Only **/
59 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
60 regUpListPtr_l = 0x38, /** Universal **/
61 regCountdown_w = 0x36, /** Universal **/
62 regFreeTimer_w = 0x34, /** Universal **/
63 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
64 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
65 regDnPoll_b = 0x2d, /** 905B Revision Only **/
66 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
67 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
68 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
69 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
70 /** **/
71 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
72 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
73 regTimer_b = 0x1a, /** Universal **/
74 regTxPktId_b = 0x18, /** 905B Revision Only **/
75 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
76 };
77
78/** following are windowed registers **/
79enum Registers7
80 {
81 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
82 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
83 regVlanMask_7_w = 0x00, /** 905B Revision Only **/
84 };
85
86enum Registers6
87 {
88 regBytesXmittedOk_6_w = 0x0c, /** Universal **/
89 regBytesRcvdOk_6_w = 0x0a, /** Universal **/
90 regUpperFramesOk_6_b = 0x09, /** Universal **/
91 regFramesDeferred_6_b = 0x08, /** Universal **/
92 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
93 regFramesXmittedOk_6_b = 0x06, /** Universal **/
94 regRxOverruns_6_b = 0x05, /** Universal **/
95 regLateCollisions_6_b = 0x04, /** Universal **/
96 regSingleCollisions_6_b = 0x03, /** Universal **/
97 regMultipleCollisions_6_b = 0x02, /** Universal **/
98 regSqeErrors_6_b = 0x01, /** Universal **/
99 regCarrierLost_6_b = 0x00, /** Universal **/
100 };
101
102enum Registers5
103 {
104 regIndicationEnable_5_w = 0x0c, /** Universal **/
105 regInterruptEnable_5_w = 0x0a, /** Universal **/
106 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
107 regRxFilter_5_b = 0x08, /** Universal **/
108 regRxEarlyThresh_5_w = 0x06, /** Universal **/
109 regTxStartThresh_5_w = 0x00, /** Universal **/
110 };
111
112enum Registers4
113 {
114 regUpperBytesOk_4_b = 0x0d, /** Universal **/
115 regBadSSD_4_b = 0x0c, /** Universal **/
116 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
117 regPhysicalMgmt_4_w = 0x08, /** Universal **/
118 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
119 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
120 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
121 };
122
123enum Registers3
124 {
125 regTxFree_3_w = 0x0c, /** Universal **/
126 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
127 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
128 /** Reset Options on Non-B Revision **/
129 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
130 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
131 regInternalConfig_3_l = 0x00, /** Universal, different bit **/
132 /** definitions, pg 59 **/
133 };
134
135enum Registers2
136 {
137 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
138 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
139 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
140 };
141
142enum Registers1
143 {
144 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
145 };
146
147enum Registers0
148 {
149 regEepromData_0_w = 0x0c, /** Universal **/
150 regEepromCommand_0_w = 0x0a, /** Universal **/
151 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
152 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
153 };
154
155
156/*** The names for the eight register windows ***/
157enum Windows
158 {
159 winPowerVlan7 = 0x07,
160 winStatistics6 = 0x06,
161 winTxRxControl5 = 0x05,
162 winDiagnostics4 = 0x04,
163 winTxRxOptions3 = 0x03,
164 winAddressing2 = 0x02,
165 winUnused1 = 0x01,
166 winEepromBios0 = 0x00,
167 };
168
169
170/*** Command definitions for the 3c90X ***/
171enum Commands
172 {
173 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
174 cmdSelectRegisterWindow = 0x01, /** Universal **/
175 cmdEnableDcConverter = 0x02, /** **/
176 cmdRxDisable = 0x03, /** **/
177 cmdRxEnable = 0x04, /** Universal **/
178 cmdRxReset = 0x05, /** Universal **/
179 cmdStallCtl = 0x06, /** Universal **/
180 cmdTxEnable = 0x09, /** Universal **/
181 cmdTxDisable = 0x0A, /** **/
182 cmdTxReset = 0x0B, /** Universal **/
183 cmdRequestInterrupt = 0x0C, /** **/
184 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
185 cmdSetInterruptEnable = 0x0E, /** Universal **/
186 cmdSetIndicationEnable = 0x0F, /** Universal **/
187 cmdSetRxFilter = 0x10, /** Universal **/
188 cmdSetRxEarlyThresh = 0x11, /** **/
189 cmdSetTxStartThresh = 0x13, /** **/
190 cmdStatisticsEnable = 0x15, /** **/
191 cmdStatisticsDisable = 0x16, /** **/
192 cmdDisableDcConverter = 0x17, /** **/
193 cmdSetTxReclaimThresh = 0x18, /** **/
194 cmdSetHashFilterBit = 0x19, /** **/
195 };
196
197
198/*** Values for int status register bitmask **/
199#define INT_INTERRUPTLATCH (1<<0)
200#define INT_HOSTERROR (1<<1)
201#define INT_TXCOMPLETE (1<<2)
202#define INT_RXCOMPLETE (1<<4)
203#define INT_RXEARLY (1<<5)
204#define INT_INTREQUESTED (1<<6)
205#define INT_UPDATESTATS (1<<7)
206#define INT_LINKEVENT (1<<8)
207#define INT_DNCOMPLETE (1<<9)
208#define INT_UPCOMPLETE (1<<10)
209#define INT_CMDINPROGRESS (1<<12)
210#define INT_WINDOWNUMBER (7<<13)
211
9c86d6da
JW		 212/* These structures are all 64-bit aligned, as needed for bus-mastering I/O. */
213typedef struct {
214 unsigned int addr;
215 unsigned int len;
216} segment_t __attribute__ ((aligned(8)));
217
218typedef struct {
219 unsigned int next;
220 unsigned int hdr;
221 segment_t segments[64 /* XXX magic */];
222} txdesc_t __attribute__ ((aligned(8)));
748534f4
JP		 223
224/*** RX descriptor ***/
9c86d6da
JW		 225typedef struct {
226 unsigned int next;
227 unsigned int status;
228 segment_t segments[64];
229} rxdesc_t __attribute__ ((aligned(8)));
748534f4
JP		 230
231/*** Global variables ***/
232static struct
233 {
234 unsigned int is3c556;
235 unsigned char isBrev;
236 unsigned char CurrentWindow;
237 unsigned int IOAddr;
238 unsigned char HWAddr[ETH_ALEN];
748534f4
JP		 239 }
240 INF_3C90X;
9c86d6da 241
7a914840 242static struct nic nic;
748534f4 243
c2e34447
JW		 244#define _outl(v,a) outl((a),(v))
245#define _outw(v,a) outw((a),(v))
246#define _outb(v,a) outb((a),(v))
748534f4 247
31ddf9b3
JW		 248static int _issue_command(int ioaddr, int cmd, int param)
249{
250 outw(ioaddr + regCommandIntStatus_w, (cmd << 11) | param);
748534f4 251
31ddf9b3
JW		 252 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
253 ;
748534f4 254
31ddf9b3
JW		 255 return 0;
256}
748534f4
JP		 257
258
259/*** a3c90x_internal_SetWindow: selects a register window set.
260 ***/
31ddf9b3
JW		 261static int _set_window(int ioaddr, int window)
262{
263 if (INF_3C90X.CurrentWindow == window)
264 return 0;
748534f4 265
31ddf9b3 266 _issue_command(ioaddr, cmdSelectRegisterWindow, window);
748534f4
JP		 267 INF_3C90X.CurrentWindow = window;
268
31ddf9b3
JW		 269 return 0;
270}
748534f4
JP		 271
272
273/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
274 ***/
275static unsigned short
276a3c90x_internal_ReadEeprom(int ioaddr, int address)
c2e34447
JW		 277{
278 unsigned short val;
748534f4
JP		 279
280 /** Select correct window **/
31ddf9b3 281 _set_window(INF_3C90X.IOAddr, winEepromBios0);
748534f4
JP		 282
283 /** Make sure the eeprom isn't busy **/
c2e34447
JW		 284 do
285 {
286 int i;
287 for (i = 0; i < 165; i++)
288 inb(0x80); /* wait 165 usec */
289 }
290 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
748534f4
JP		 291
292 /** Read the value. **/
293 if (INF_3C90X.is3c556)
c2e34447 294 _outw(address + (0x230), ioaddr + regEepromCommand_0_w);
748534f4 295 else
c2e34447 296 _outw(address + 0x80, ioaddr + regEepromCommand_0_w);
748534f4 297
c2e34447
JW		 298 do
299 {
300 int i;
301 for (i = 0; i < 165; i++)
302 inb(0x80); /* wait 165 usec */
303 }
304 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
305 val = inw(ioaddr + regEepromData_0_w);
306
307 return val;
308}
748534f4
JP		 309
310
748534f4
JP		 311/*** a3c90x_reset: exported function that resets the card to its default
312 *** state. This is so the Linux driver can re-set the card up the way
313 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
314 *** not alter the selected transceiver that we used to download the boot
315 *** image.
316 ***/
317static void a3c90x_reset(void)
318 {
748534f4 319 /** Send the reset command to the card **/
99182958 320 outputf("3c90x: issuing RESET");
31ddf9b3 321 _issue_command(INF_3C90X.IOAddr, cmdGlobalReset, 0);
748534f4
JP		 322
323 /** global reset command resets station mask, non-B revision cards
324 ** require explicit reset of values
325 **/
31ddf9b3 326 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 327 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
328 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
329 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4 330
748534f4 331 /** Issue transmit reset, wait for command completion **/
31ddf9b3 332 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 333 if (! INF_3C90X.isBrev)
c2e34447 334 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
31ddf9b3 335 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 336
337 /**
338 ** reset of the receiver on B-revision cards re-negotiates the link
339 ** takes several seconds (a computer eternity)
340 **/
341 if (INF_3C90X.isBrev)
31ddf9b3 342 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 343 else
31ddf9b3
JW		 344 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
345 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
346 ;
347 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4 348
31ddf9b3 349 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
748534f4 350 /** enable rxComplete and txComplete **/
31ddf9b3 351 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
748534f4 352 /** acknowledge any pending status flags **/
31ddf9b3 353 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 354
355 return;
356 }
357
73d65ee6 358/***************************** Transmit routines *****************************/
748534f4 359
73d65ee6 360#define XMIT_BUFS 8
748534f4 361
73d65ee6
JW		 362static txdesc_t txdescs[XMIT_BUFS];
363static struct pbuf *txpbufs[XMIT_BUFS] = {0,};
364
365/* txcons is the index into the ring buffer of the last packet that the
366 * 3c90x was seen processing, or -1 if the 3c90x was idle.
367 */
368static int txcons = -1;
369
370/* txprod is the index of the _next_ buffer that the driver will write into. */
371static int txprod = 0;
372
373/* _transmit adds a packet to the transmit ring buffer. If no space is
374 * available in the buffer, then _transmit blocks until a packet has been
375 * transmitted.
376 */
bc9e1044 377static void _transmit(struct pbuf *p)
31ddf9b3 378{
31ddf9b3 379 unsigned char status;
73d65ee6 380 int len, n;
f8903fdd 381
73d65ee6
JW		 382 /* Wait for there to be space. */
383 if (txcons == txprod)
f8903fdd 384 {
bec09bd1 385 int i = 0;
73d65ee6
JW		 386
387 outputf("3c90x: txbuf full, waiting for space...");
388 while (inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0)
bec09bd1 389 i++;
73d65ee6
JW		 390 outputf("3c90x: took %d iters", i);
391 }
392
393 /* Stall the download engine so it doesn't bother us. */
394 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 2 /* Stall download */);
395
396 /* Clean up old txcons. */
397 if (txcons != -1)
398 {
399 unsigned long curp = inl(INF_3C90X.IOAddr + regDnListPtr_l);
400 int end;
401
402 if (curp == 0)
403 end = txprod;
404 else
405 end = (curp - v2p(txdescs)) / sizeof(txdescs[0]);
406
407 while (txcons != end)
f8903fdd 408 {
73d65ee6
JW		 409 pbuf_free(txpbufs[txcons]);
410 txpbufs[txcons] = NULL;
411 txdescs[txcons].hdr = 0;
412 txdescs[txcons].next = 0;
413 txcons = (txcons + 1) % XMIT_BUFS;
f8903fdd 414 }
73d65ee6
JW		 415 if (txcons == txprod)
416 txcons = -1;
417 }
418
419 /* Look at the TX status */
420 status = inb(INF_3C90X.IOAddr + regTxStatus_b);
421 if (status)
422 {
423 outputf("3c90x: error: the nus.");
f8903fdd 424 outb(INF_3C90X.IOAddr + regTxStatus_b, 0x00);
f8903fdd 425 }
3dd054cf 426
73d65ee6
JW		 427 /* Set up the new txdesc. */
428 txdescs[txprod].next = 0;
54d4b877
JW		 429 len = 0;
430 n = 0;
73d65ee6 431 txpbufs[txprod] = p;
54d4b877
JW		 432 for (; p; p = p->next)
433 {
73d65ee6
JW		 434 txdescs[txprod].segments[n].addr = v2p(p->payload);
435 txdescs[txprod].segments[n].len = p->len | (p->next ? 0 : (1 << 31));
54d4b877 436 len += p->len;
057f0bb9 437 pbuf_ref(p);
54d4b877
JW		 438 n++;
439 }
73d65ee6 440 txdescs[txprod].hdr = len; /* If we wanted completion notification, bit 15 */
037ce545 441
73d65ee6
JW		 442 /* Now link the new one in, after it's been set up. */
443 txdescs[(txprod + XMIT_BUFS - 1) % XMIT_BUFS].next = v2p(&(txdescs[txprod]));
444
445 /* If the card is stopped, start it up again. */
446 if (inl(INF_3C90X.IOAddr + regDnListPtr_l) == 0)
037ce545 447 {
73d65ee6
JW		 448 outl(INF_3C90X.IOAddr + regDnListPtr_l, v2p(&(txdescs[txprod])));
449 txcons = txprod;
037ce545 450 }
73d65ee6
JW		 451
452 txprod = (txprod + 1) % XMIT_BUFS;
453
454 /* And let it proceed on its way. */
455 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 3 /* Unstall download */);
3dd054cf 456
3dd054cf 457#if 0
037ce545
JW		 458 /** successful completion (sans "interrupt Requested" bit) **/
459 if ((status & 0xbf) == 0x80)
460 return;
31ddf9b3 461
037ce545
JW		 462 outputf("3c90x: Status (%hhX)", status);
463 /** check error codes **/
464 if (status & 0x02)
465 {
466 outputf("3c90x: Tx Reclaim Error (%hhX)", status);
467 a3c90x_reset();
468 } else if (status & 0x04) {
469 outputf("3c90x: Tx Status Overflow (%hhX)", status);
470 for (i=0; i<32; i++)
471 _outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
472 /** must re-enable after max collisions before re-issuing tx **/
473 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
474 } else if (status & 0x08) {
475 outputf("3c90x: Tx Max Collisions (%hhX)", status);
476 /** must re-enable after max collisions before re-issuing tx **/
477 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
478 } else if (status & 0x10) {
479 outputf("3c90x: Tx Underrun (%hhX)", status);
480 a3c90x_reset();
481 } else if (status & 0x20) {
482 outputf("3c90x: Tx Jabber (%hhX)", status);
483 a3c90x_reset();
484 } else if ((status & 0x80) != 0x80) {
485 outputf("3c90x: Internal Error - Incomplete Transmission (%hhX)", status);
486 a3c90x_reset();
748534f4 487 }
037ce545 488#endif
31ddf9b3 489}
748534f4 490
bec09bd1
JW		 491/***************************** Receive routines *****************************/
492#define MAX_RECV_SIZE 1536
421ccff4 493#define RECV_BUFS 32
bec09bd1
JW		 494
495static rxdesc_t rxdescs[RECV_BUFS];
73d65ee6 496static struct pbuf *rxpbufs[RECV_BUFS] = {0,};
bec09bd1
JW		 497
498/* rxcons is the pointer to the receive descriptor that the ethernet card will
499 * write into next.
500 */
501static int rxcons = 0;
502
503/* rxprod is the pointer to the receive descriptor that the driver will
504 * allocate next.
80c7c8bf 505 */
bec09bd1
JW		 506static int rxprod = 0;
507
508/* _recv_prepare fills the 3c90x's ring buffer with fresh pbufs from lwIP.
509 * The upload engine need not be stalled.
510 */
511static void _recv_prepare(struct nic *nic)
9c86d6da 512{
bec09bd1
JW		 513 int oldprod;
514
515 oldprod = rxprod;
73d65ee6 516 while ((rxprod != rxcons) || !rxpbufs[rxprod])
748534f4 517 {
bec09bd1
JW		 518 int i;
519 struct pbuf *p;
520
73d65ee6
JW		 521 if (!rxpbufs[rxprod])
522 rxpbufs[rxprod] = p = pbuf_alloc(PBUF_RAW, MAX_RECV_SIZE, PBUF_POOL);
bec09bd1
JW		 523 else {
524 outputf("WARNING: 3c90x has pbuf in slot %d", rxprod);
73d65ee6 525 p = rxpbufs[rxprod];
bec09bd1
JW		 526 }
527
528 if (!p)
529 {
530 outputf("3c90x: out of memory for rx pbuf?");
531 break;
532 }
533
534 rxdescs[rxprod].status = 0;
535 rxdescs[rxprod].next = 0;
536 for (i = 0; p; p = p->next, i++)
537 {
538 rxdescs[rxprod].segments[i].addr = v2p(p->payload);
539 rxdescs[rxprod].segments[i].len = p->len | (p->next ? 0 : (1 << 31));
540 }
541
542 /* Hook in the new one after and only after it's been fully set up. */
543 rxdescs[(rxprod + RECV_BUFS - 1) % RECV_BUFS].next = v2p(&(rxdescs[rxprod]));
544 rxprod = (rxprod + 1) % RECV_BUFS;
748534f4 545 }
80c7c8bf 546
73d65ee6 547 if (inl(INF_3C90X.IOAddr + regUpListPtr_l) == 0 && rxpbufs[oldprod]) /* Ran out of shit, and got new shit? */
748534f4 548 {
bec09bd1
JW		 549 outl(INF_3C90X.IOAddr + regUpListPtr_l, v2p(&rxdescs[oldprod]));
550 outputf("3c90x: WARNING: Ran out of rx slots");
748534f4 551 }
80c7c8bf 552
421ccff4 553 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 1 /* Unstall upload */);
80c7c8bf 554}
748534f4 555
bec09bd1
JW		 556/* _recv polls the ring buffer to see if any packets are available. If any
557 * are, then eth_recv is called for each available. _recv returns how many
558 * packets it received successfully. Whether _recv got any packets or not,
559 * _recv does not block, and reinitializes the ring buffer with fresh pbufs.
560 */
561static int _recv(struct nic *nic)
80c7c8bf 562{
bec09bd1 563 int errcode, n = 0;
80c7c8bf
JW		 564 struct pbuf *p;
565
80c7c8bf 566 /* Nothing to do? */
bec09bd1 567 while ((rxdescs[rxcons].status & ((1<<14) | (1<<15))) != 0)
9c86d6da 568 {
bec09bd1
JW		 569 /** Check for Error (else we have good packet) **/
570 if (rxdescs[rxcons].status & (1<<14))
571 {
572 errcode = rxdescs[rxcons].status;
573 if (errcode & (1<<16))
574 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);
575 else if (errcode & (1<<17))
576 outputf("3C90X: Runt Frame (%hX)",errcode>>16);
577 else if (errcode & (1<<18))
578 outputf("3C90X: Alignment Error (%hX)",errcode>>16);
579 else if (errcode & (1<<19))
580 outputf("3C90X: CRC Error (%hX)",errcode>>16);
581 else if (errcode & (1<<20))
582 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);
583 else
584 outputf("3C90X: Packet error (%hX)",errcode>>16);
80c7c8bf 585
bec09bd1 586 p = NULL;
73d65ee6 587 pbuf_free(rxpbufs[rxcons]); /* Bounce the old one before setting it up again. */
bec09bd1 588 } else {
73d65ee6 589 p = rxpbufs[rxcons];
bec09bd1
JW		 590 pbuf_realloc(p, rxdescs[rxcons].status & 0x1FFF); /* Resize the packet to how large it actually is. */
591 }
592
73d65ee6 593 rxpbufs[rxcons] = NULL;
bec09bd1
JW		 594 rxdescs[rxcons].status = 0;
595 rxcons = (rxcons + 1) % RECV_BUFS;
596
597 if (p)
598 {
599 eth_recv(nic, p);
600 n++;
601 }
9c86d6da 602 }
748534f4 603
bec09bd1
JW		 604 _recv_prepare(nic); /* Light the NIC up again. */
605 return n;
9c86d6da 606}
748534f4
JP		 607
608/*** a3c90x_disable: exported routine to disable the card. What's this for?
609 *** the eepro100.c driver didn't have one, so I just left this one empty too.
610 *** Ideas anyone?
611 *** Must turn off receiver at least so stray packets will not corrupt memory
612 *** [Ken]
613 ***/
614void a3c90x_disable(struct dev *dev)
615{
616 /* reset and disable merge */
617 a3c90x_reset();
618 /* Disable the receiver and transmitter. */
c2e34447
JW		 619 _outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
620 _outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
748534f4
JP		 621}
622
623
624/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
625 *** initialization. If this routine is called, the pci functions did find the
626 *** card. We just have to init it here.
627 ***/
628static int a3c90x_probe(struct pci_dev * pci, void * data)
629{
748534f4
JP		 630 INF_3C90X.is3c556 = (pci->did == 0x6055);
631
632 int i, c;
c2e34447 633 unsigned short eeprom[0x100];
748534f4
JP		 634 unsigned int cfg;
635 unsigned int mopt;
636 unsigned int mstat;
637 unsigned short linktype;
638#define HWADDR_OFFSET 10
639
640 unsigned long ioaddr = 0;
641 for (i = 0; i < 6; i++) {
642 if (pci->bars[i].type == PCI_BAR_IO) {
643 ioaddr = pci->bars[i].addr;
644 break;
645 }
646 }
647
648 if (ioaddr == 0)
c2e34447
JW		 649 {
650 outputf("3c90x: Unable to find I/O address");
651 return 0;
652 }
653
654 /* Power it on */
655 pci_write16(pci->bus, pci->dev, pci->fn, 0xE0,
656 pci_read16(pci->bus, pci->dev, pci->fn, 0xE0) & ~0x3);
657
658 outputf("3c90x: Picked I/O address %04x", ioaddr);
047916ed 659 pci_bother_add(pci);
42125f27
JP		 660 nic.ioaddr = ioaddr & ~3;
661 nic.irqno = 0;
748534f4 662
c2e34447 663 INF_3C90X.IOAddr = ioaddr;
748534f4
JP		 664 INF_3C90X.CurrentWindow = 255;
665 switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
666 {
667 case 0x9000: /** 10 Base TPO **/
668 case 0x9001: /** 10/100 T4 **/
669 case 0x9050: /** 10/100 TPO **/
670 case 0x9051: /** 10 Base Combo **/
671 INF_3C90X.isBrev = 0;
672 break;
673
674 case 0x9004: /** 10 Base TPO **/
675 case 0x9005: /** 10 Base Combo **/
676 case 0x9006: /** 10 Base TPO and Base2 **/
677 case 0x900A: /** 10 Base FL **/
678 case 0x9055: /** 10/100 TPO **/
679 case 0x9056: /** 10/100 T4 **/
680 case 0x905A: /** 10 Base FX **/
681 default:
682 INF_3C90X.isBrev = 1;
683 break;
684 }
685
686 /** Load the EEPROM contents **/
687 if (INF_3C90X.isBrev)
688 {
c2e34447 689 for(i=0;i<=/*0x20*/0x7F;i++)
748534f4
JP		 690 {
691 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
692 }
693
748534f4
JP		 694#ifdef CFG_3C90X_XCVR
695 if (CFG_3C90X_XCVR == 255)
696 {
697 /** Clear the LanWorks register **/
698 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
699 }
700 else
701 {
702 /** Set the selected permanent-xcvrSelect in the
703 ** LanWorks register
704 **/
705 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
706 XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
707 }
708#endif
709 }
710 else
711 {
c2e34447 712 for(i=0;i<=/*0x17*/0x7F;i++)
748534f4
JP		 713 {
714 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
715 }
716 }
717
748534f4
JP		 718 /** Retrieve the Hardware address and print it on the screen. **/
719 INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
720 INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
721 INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
722 INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
723 INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
724 INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
c2e34447
JW		 725 outputf("MAC Address = %02x:%02x:%02x:%02x:%02x:%02x",
726 INF_3C90X.HWAddr[0],
727 INF_3C90X.HWAddr[1],
728 INF_3C90X.HWAddr[2],
729 INF_3C90X.HWAddr[3],
730 INF_3C90X.HWAddr[4],
731 INF_3C90X.HWAddr[5]);
748534f4
JP		 732
733 /** 3C556: Invert MII power **/
734 if (INF_3C90X.is3c556) {
735 unsigned int tmp;
31ddf9b3 736 _set_window(INF_3C90X.IOAddr, winAddressing2);
748534f4
JP		 737 tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
738 tmp |= 0x4000;
c2e34447 739 _outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
748534f4
JP		 740 }
741
742 /* Test if the link is good, if not continue */
31ddf9b3 743 _set_window(INF_3C90X.IOAddr, winDiagnostics4);
748534f4
JP		 744 mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
745 if((mstat & (1<<11)) == 0) {
746 outputf("Valid link not established");
747 return 0;
748 }
749
750 /** Program the MAC address into the station address registers **/
31ddf9b3 751 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 752 _outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
753 _outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
754 _outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
755 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
756 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
757 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4 758
748534f4
JP		 759 /** Read the media options register, print a message and set default
760 ** xcvr.
761 **
762 ** Uses Media Option command on B revision, Reset Option on non-B
763 ** revision cards -- same register address
764 **/
31ddf9b3 765 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 766 mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
767
768 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
769 if (! INF_3C90X.isBrev)
770 {
771 mopt &= 0x7F;
772 }
773
774 outputf("Connectors present: ");
775 c = 0;
776 linktype = 0x0008;
777 if (mopt & 0x01)
778 {
80c7c8bf 779 outputf(" 100Base-T4");
748534f4
JP		 780 linktype = 0x0006;
781 }
782 if (mopt & 0x04)
783 {
80c7c8bf 784 outputf(" 100Base-FX");
748534f4
JP		 785 linktype = 0x0005;
786 }
787 if (mopt & 0x10)
788 {
80c7c8bf 789 outputf(" 10Base-2");
748534f4
JP		 790 linktype = 0x0003;
791 }
792 if (mopt & 0x20)
793 {
80c7c8bf 794 outputf(" AUI");
748534f4
JP		 795 linktype = 0x0001;
796 }
797 if (mopt & 0x40)
798 {
80c7c8bf 799 outputf(" MII");
748534f4
JP		 800 linktype = 0x0006;
801 }
802 if ((mopt & 0xA) == 0xA)
803 {
80c7c8bf 804 outputf(" 10Base-T / 100Base-TX");
748534f4
JP		 805 linktype = 0x0008;
806 }
807 else if ((mopt & 0xA) == 0x2)
808 {
80c7c8bf 809 outputf(" 100Base-TX");
748534f4
JP		 810 linktype = 0x0008;
811 }
812 else if ((mopt & 0xA) == 0x8)
813 {
80c7c8bf 814 outputf(" 10Base-T");
748534f4
JP		 815 linktype = 0x0008;
816 }
748534f4
JP		 817
818 /** Determine transceiver type to use, depending on value stored in
819 ** eeprom 0x16
820 **/
821 if (INF_3C90X.isBrev)
822 {
823 if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
824 {
825 /** User-defined **/
826 linktype = eeprom[0x16] & 0x000F;
827 }
828 }
829 else
830 {
831#ifdef CFG_3C90X_XCVR
832 if (CFG_3C90X_XCVR != 255)
833 linktype = CFG_3C90X_XCVR;
834#endif /* CFG_3C90X_XCVR */
835
836 /** I don't know what MII MAC only mode is!!! **/
837 if (linktype == 0x0009)
838 {
839 if (INF_3C90X.isBrev)
840 outputf("WARNING: MII External MAC Mode only supported on B-revision "
841 "cards!!!!\nFalling Back to MII Mode\n");
842 linktype = 0x0006;
843 }
844 }
845
846 /** enable DC converter for 10-Base-T **/
847 if (linktype == 0x0003)
848 {
31ddf9b3 849 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 850 }
851
852 /** Set the link to the type we just determined. **/
31ddf9b3 853 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 854 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
855 cfg &= ~(0xF<<20);
856 cfg |= (linktype<<20);
c2e34447 857 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 858
859 /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
31ddf9b3 860 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 861 if (!INF_3C90X.isBrev)
c2e34447 862 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
748534f4 863
31ddf9b3 864 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 865
866 /**
867 ** reset of the receiver on B-revision cards re-negotiates the link
868 ** takes several seconds (a computer eternity)
869 **/
870 if (INF_3C90X.isBrev)
31ddf9b3 871 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 872 else
31ddf9b3 873 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
748534f4
JP		 874
875 /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
31ddf9b3 876 _issue_command(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
80c7c8bf 877
bec09bd1
JW		 878 /* Stick some packets in the queue. */
879 _recv_prepare(&nic);
880
881 /* And light up the RX engine. */
882 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4
JP		 883
884 /**
885 ** set Indication and Interrupt flags , acknowledge any IRQ's
886 **/
31ddf9b3
JW		 887 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
888 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
889 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 890
891 /* * Set our exported functions **/
bc9e1044
JW		 892 nic.recv = _recv;
893 nic.transmit = _transmit;
47c41031 894 memcpy(nic.hwaddr, INF_3C90X.HWAddr, 6);
c2e34447 895 eth_register(&nic);
748534f4
JP		 896
897 return 1;
898}
899
900static struct pci_id a3c90x_nics[] = {
901/* Original 90x revisions: */
902PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
903PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
904PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
905PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
906PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
907/* Newer 90xB revisions: */
908PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
909PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
910PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
911PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
912PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
913PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
914PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
915PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
916/* Newer 90xC revision: */
917PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
918PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
919PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
920PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
921PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
922PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
923PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
924PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
925PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
926};
927
928struct pci_driver a3c90x_driver = {
929 .name = "3C90X",
930 .probe = a3c90x_probe,
931 .ids = a3c90x_nics,
932 .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
933};
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