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748534f4
JP		 1/*
2 * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
3 * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
4 * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
5 *
6 * This program Copyright (C) 1999 LightSys Technology Services, Inc.
7 * Portions Copyright (C) 1999 Steve Smith
8 *
9 * This program may be re-distributed in source or binary form, modified,
10 * sold, or copied for any purpose, provided that the above copyright message
11 * and this text are included with all source copies or derivative works, and
12 * provided that the above copyright message and this text are included in the
13 * documentation of any binary-only distributions. This program is distributed
14 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
15 * PURPOSE or MERCHANTABILITY. Please read the associated documentation
16 * "3c90x.txt" before compiling and using this driver.
17 *
18 * --------
19 *
20 * Program written with the assistance of the 3com documentation for
21 * the 3c905B-TX card, as well as with some assistance from the 3c59x
22 * driver Donald Becker wrote for the Linux kernel, and with some assistance
23 * from the remainder of the Etherboot distribution.
24 *
25 * REVISION HISTORY:
26 *
27 * v0.10 1-26-1998 GRB Initial implementation.
28 * v0.90 1-27-1998 GRB System works.
29 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31 * Re-wrote poll and transmit for
32 * better error recovery and heavy
33 * network traffic operation
34 * v2.01 5-26-2003 NN Fixed driver alignment issue which
35 * caused system lockups if driver structures
36 * not 8-byte aligned.
37 *
38 */
39
40#include "etherboot-compat.h"
42125f27 41#include "net.h"
748534f4
JP		 42#include <timer.h>
43#include <io.h>
44#include <pci.h>
7a914840 45#include <pci-bother.h>
748534f4
JP		 46#include <minilib.h>
47#include <output.h>
48
49#define XCVR_MAGIC (0x5A00)
50/** any single transmission fails after 16 collisions or other errors
51 ** this is the number of times to retry the transmission -- this should
52 ** be plenty
53 **/
c25f3f39 54#define XMIT_RETRIES 5
748534f4
JP		 55
56/*** Register definitions for the 3c905 ***/
57enum Registers
58 {
59 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
60 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
61 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
62 regDebugControl_w = 0x74, /** 905B Revision Only **/
63 regDebugData_l = 0x70, /** 905B Revision Only **/
64 regRealTimeCnt_l = 0x40, /** Universal **/
65 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
66 regUpPoll_b = 0x3d, /** 905B Revision Only **/
67 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
68 regUpListPtr_l = 0x38, /** Universal **/
69 regCountdown_w = 0x36, /** Universal **/
70 regFreeTimer_w = 0x34, /** Universal **/
71 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
72 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
73 regDnPoll_b = 0x2d, /** 905B Revision Only **/
74 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
75 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
76 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
77 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
78 /** **/
79 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
80 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
81 regTimer_b = 0x1a, /** Universal **/
82 regTxPktId_b = 0x18, /** 905B Revision Only **/
83 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
84 };
85
86/** following are windowed registers **/
87enum Registers7
88 {
89 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
90 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
91 regVlanMask_7_w = 0x00, /** 905B Revision Only **/
92 };
93
94enum Registers6
95 {
96 regBytesXmittedOk_6_w = 0x0c, /** Universal **/
97 regBytesRcvdOk_6_w = 0x0a, /** Universal **/
98 regUpperFramesOk_6_b = 0x09, /** Universal **/
99 regFramesDeferred_6_b = 0x08, /** Universal **/
100 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
101 regFramesXmittedOk_6_b = 0x06, /** Universal **/
102 regRxOverruns_6_b = 0x05, /** Universal **/
103 regLateCollisions_6_b = 0x04, /** Universal **/
104 regSingleCollisions_6_b = 0x03, /** Universal **/
105 regMultipleCollisions_6_b = 0x02, /** Universal **/
106 regSqeErrors_6_b = 0x01, /** Universal **/
107 regCarrierLost_6_b = 0x00, /** Universal **/
108 };
109
110enum Registers5
111 {
112 regIndicationEnable_5_w = 0x0c, /** Universal **/
113 regInterruptEnable_5_w = 0x0a, /** Universal **/
114 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
115 regRxFilter_5_b = 0x08, /** Universal **/
116 regRxEarlyThresh_5_w = 0x06, /** Universal **/
117 regTxStartThresh_5_w = 0x00, /** Universal **/
118 };
119
120enum Registers4
121 {
122 regUpperBytesOk_4_b = 0x0d, /** Universal **/
123 regBadSSD_4_b = 0x0c, /** Universal **/
124 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
125 regPhysicalMgmt_4_w = 0x08, /** Universal **/
126 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
127 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
128 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
129 };
130
131enum Registers3
132 {
133 regTxFree_3_w = 0x0c, /** Universal **/
134 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
135 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
136 /** Reset Options on Non-B Revision **/
137 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
138 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
139 regInternalConfig_3_l = 0x00, /** Universal, different bit **/
140 /** definitions, pg 59 **/
141 };
142
143enum Registers2
144 {
145 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
146 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
147 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
148 };
149
150enum Registers1
151 {
152 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
153 };
154
155enum Registers0
156 {
157 regEepromData_0_w = 0x0c, /** Universal **/
158 regEepromCommand_0_w = 0x0a, /** Universal **/
159 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
160 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
161 };
162
163
164/*** The names for the eight register windows ***/
165enum Windows
166 {
167 winPowerVlan7 = 0x07,
168 winStatistics6 = 0x06,
169 winTxRxControl5 = 0x05,
170 winDiagnostics4 = 0x04,
171 winTxRxOptions3 = 0x03,
172 winAddressing2 = 0x02,
173 winUnused1 = 0x01,
174 winEepromBios0 = 0x00,
175 };
176
177
178/*** Command definitions for the 3c90X ***/
179enum Commands
180 {
181 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
182 cmdSelectRegisterWindow = 0x01, /** Universal **/
183 cmdEnableDcConverter = 0x02, /** **/
184 cmdRxDisable = 0x03, /** **/
185 cmdRxEnable = 0x04, /** Universal **/
186 cmdRxReset = 0x05, /** Universal **/
187 cmdStallCtl = 0x06, /** Universal **/
188 cmdTxEnable = 0x09, /** Universal **/
189 cmdTxDisable = 0x0A, /** **/
190 cmdTxReset = 0x0B, /** Universal **/
191 cmdRequestInterrupt = 0x0C, /** **/
192 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
193 cmdSetInterruptEnable = 0x0E, /** Universal **/
194 cmdSetIndicationEnable = 0x0F, /** Universal **/
195 cmdSetRxFilter = 0x10, /** Universal **/
196 cmdSetRxEarlyThresh = 0x11, /** **/
197 cmdSetTxStartThresh = 0x13, /** **/
198 cmdStatisticsEnable = 0x15, /** **/
199 cmdStatisticsDisable = 0x16, /** **/
200 cmdDisableDcConverter = 0x17, /** **/
201 cmdSetTxReclaimThresh = 0x18, /** **/
202 cmdSetHashFilterBit = 0x19, /** **/
203 };
204
205
206/*** Values for int status register bitmask **/
207#define INT_INTERRUPTLATCH (1<<0)
208#define INT_HOSTERROR (1<<1)
209#define INT_TXCOMPLETE (1<<2)
210#define INT_RXCOMPLETE (1<<4)
211#define INT_RXEARLY (1<<5)
212#define INT_INTREQUESTED (1<<6)
213#define INT_UPDATESTATS (1<<7)
214#define INT_LINKEVENT (1<<8)
215#define INT_DNCOMPLETE (1<<9)
216#define INT_UPCOMPLETE (1<<10)
217#define INT_CMDINPROGRESS (1<<12)
218#define INT_WINDOWNUMBER (7<<13)
219
220
221/*** TX descriptor ***/
222typedef struct
223 {
224 unsigned int DnNextPtr;
225 unsigned int FrameStartHeader;
226 unsigned int HdrAddr;
227 unsigned int HdrLength;
228 unsigned int DataAddr;
229 unsigned int DataLength;
230 }
231 TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
232
233/*** RX descriptor ***/
234typedef struct
235 {
236 unsigned int UpNextPtr;
237 unsigned int UpPktStatus;
238 unsigned int DataAddr;
239 unsigned int DataLength;
240 }
241 RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
242
243/*** Global variables ***/
244static struct
245 {
246 unsigned int is3c556;
247 unsigned char isBrev;
248 unsigned char CurrentWindow;
249 unsigned int IOAddr;
250 unsigned char HWAddr[ETH_ALEN];
251 TXD TransmitDPD;
252 RXD ReceiveUPD;
253 }
254 INF_3C90X;
7a914840 255static struct nic nic;
748534f4 256
c2e34447
JW		 257#define _outl(v,a) outl((a),(v))
258#define _outw(v,a) outw((a),(v))
259#define _outb(v,a) outb((a),(v))
748534f4 260
31ddf9b3
JW		 261static int _issue_command(int ioaddr, int cmd, int param)
262{
263 outw(ioaddr + regCommandIntStatus_w, (cmd << 11) | param);
748534f4 264
31ddf9b3
JW		 265 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
266 ;
748534f4 267
31ddf9b3
JW		 268 return 0;
269}
748534f4
JP		 270
271
272/*** a3c90x_internal_SetWindow: selects a register window set.
273 ***/
31ddf9b3
JW		 274static int _set_window(int ioaddr, int window)
275{
276 if (INF_3C90X.CurrentWindow == window)
277 return 0;
748534f4 278
31ddf9b3 279 _issue_command(ioaddr, cmdSelectRegisterWindow, window);
748534f4
JP		 280 INF_3C90X.CurrentWindow = window;
281
31ddf9b3
JW		 282 return 0;
283}
748534f4
JP		 284
285
286/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
287 ***/
288static unsigned short
289a3c90x_internal_ReadEeprom(int ioaddr, int address)
c2e34447
JW		 290{
291 unsigned short val;
748534f4
JP		 292
293 /** Select correct window **/
31ddf9b3 294 _set_window(INF_3C90X.IOAddr, winEepromBios0);
748534f4
JP		 295
296 /** Make sure the eeprom isn't busy **/
c2e34447
JW		 297 do
298 {
299 int i;
300 for (i = 0; i < 165; i++)
301 inb(0x80); /* wait 165 usec */
302 }
303 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
748534f4
JP		 304
305 /** Read the value. **/
306 if (INF_3C90X.is3c556)
c2e34447 307 _outw(address + (0x230), ioaddr + regEepromCommand_0_w);
748534f4 308 else
c2e34447 309 _outw(address + 0x80, ioaddr + regEepromCommand_0_w);
748534f4 310
c2e34447
JW		 311 do
312 {
313 int i;
314 for (i = 0; i < 165; i++)
315 inb(0x80); /* wait 165 usec */
316 }
317 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
318 val = inw(ioaddr + regEepromData_0_w);
319
320 return val;
321}
748534f4
JP		 322
323
324#ifdef CFG_3C90X_BOOTROM_FIX
325/*** a3c90x_internal_WriteEepromWord - write a physical word of
326 *** data to the onboard serial eeprom (not the BIOS prom, but the
327 *** nvram in the card that stores, among other things, the MAC
328 *** address).
329 ***/
330static int
331a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
332 {
333 /** Select register window **/
31ddf9b3 334 _set_window(ioaddr, winEepromBios0);
748534f4
JP		 335
336 /** Verify Eeprom not busy **/
337 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
338
339 /** Issue WriteEnable, and wait for completion. **/
c2e34447 340 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 341 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
342
343 /** Issue EraseRegister, and wait for completion. **/
c2e34447 344 _outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 345 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
346
347 /** Send the new data to the eeprom, and wait for completion. **/
c2e34447
JW		 348 _outw(value, ioaddr + regEepromData_0_w);
349 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 350 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
351
352 /** Burn the new data into the eeprom, and wait for completion. **/
c2e34447 353 _outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 354 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
355
356 return 0;
357 }
358#endif
359
360#ifdef CFG_3C90X_BOOTROM_FIX
361/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
362 *** and re-compute the eeprom checksum.
363 ***/
364static int
365a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
366 {
367 int cksum = 0,v;
368 int i;
369 int maxAddress, cksumAddress;
370
371 if (INF_3C90X.isBrev)
372 {
373 maxAddress=0x1f;
374 cksumAddress=0x20;
375 }
376 else
377 {
378 maxAddress=0x16;
379 cksumAddress=0x17;
380 }
381
382 /** Write the value. **/
383 if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
384 return -1;
385
386 /** Recompute the checksum. **/
387 for(i=0;i<=maxAddress;i++)
388 {
389 v = a3c90x_internal_ReadEeprom(ioaddr, i);
390 cksum ^= (v & 0xFF);
391 cksum ^= ((v>>8) & 0xFF);
392 }
393 /** Write the checksum to the location in the eeprom **/
394 if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
395 return -1;
396
397 return 0;
398 }
399#endif
400
401/*** a3c90x_reset: exported function that resets the card to its default
402 *** state. This is so the Linux driver can re-set the card up the way
403 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
404 *** not alter the selected transceiver that we used to download the boot
405 *** image.
406 ***/
407static void a3c90x_reset(void)
408 {
409#ifdef CFG_3C90X_PRESERVE_XCVR
410 int cfg;
411 /** Read the current InternalConfig value. **/
31ddf9b3 412 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 413 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
414#endif
415
416 /** Send the reset command to the card **/
99182958 417 outputf("3c90x: issuing RESET");
31ddf9b3 418 _issue_command(INF_3C90X.IOAddr, cmdGlobalReset, 0);
748534f4
JP		 419
420 /** global reset command resets station mask, non-B revision cards
421 ** require explicit reset of values
422 **/
31ddf9b3 423 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 424 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
425 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
426 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 427
428#ifdef CFG_3C90X_PRESERVE_XCVR
429 /** Re-set the original InternalConfig value from before reset **/
31ddf9b3 430 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
c2e34447 431 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 432
433 /** enable DC converter for 10-Base-T **/
434 if ((cfg&0x0300) == 0x0300)
435 {
31ddf9b3 436 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 437 }
438#endif
439
440 /** Issue transmit reset, wait for command completion **/
31ddf9b3 441 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 442 if (! INF_3C90X.isBrev)
c2e34447 443 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
31ddf9b3 444 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 445
446 /**
447 ** reset of the receiver on B-revision cards re-negotiates the link
448 ** takes several seconds (a computer eternity)
449 **/
450 if (INF_3C90X.isBrev)
31ddf9b3 451 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 452 else
31ddf9b3
JW		 453 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
454 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
455 ;
456 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4 457
31ddf9b3 458 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
748534f4 459 /** enable rxComplete and txComplete **/
31ddf9b3 460 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
748534f4 461 /** acknowledge any pending status flags **/
31ddf9b3 462 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 463
464 return;
465 }
466
467
468
469/*** a3c90x_transmit: exported function that transmits a packet. Does not
470 *** return any particular status. Parameters are:
471 *** dest_addr[6] - destination address, ethernet;
472 *** proto - protocol type (ARP, IP, etc);
473 *** size - size of the non-header part of the packet that needs transmitted;
474 *** pkt - the pointer to the packet data itself.
475 ***/
476static void
477a3c90x_transmit(const char *dest_addr, unsigned int proto,
478 unsigned int size, const char *pkt)
31ddf9b3
JW		 479{
480 struct eth_hdr
748534f4 481 {
31ddf9b3
JW		 482 unsigned char dst_addr[ETH_ALEN];
483 unsigned char src_addr[ETH_ALEN];
484 unsigned short type;
748534f4 485 } hdr;
31ddf9b3
JW		 486
487 unsigned char status;
488 unsigned int i, retries;
748534f4 489
31ddf9b3 490 for (retries=0; retries < XMIT_RETRIES; retries++)
748534f4 491 {
31ddf9b3
JW		 492 if (retries != 0)
493 outputf("3c90x: retrying packet send (%d)", retries);
494
31ddf9b3
JW		 495 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 2 /* Stall download */);
496
497 hdr.type = htons(proto);
498 memcpy(hdr.dst_addr, dest_addr, ETH_ALEN);
499 memcpy(hdr.src_addr, INF_3C90X.HWAddr, ETH_ALEN);
500
501 /** Setup the DPD (download descriptor) **/
502 INF_3C90X.TransmitDPD.DnNextPtr = 0;
503 /** set notification for transmission completion (bit 15) **/
c25f3f39 504 INF_3C90X.TransmitDPD.FrameStartHeader = (size + sizeof(hdr)) | 0x8000;
31ddf9b3
JW		 505 INF_3C90X.TransmitDPD.HdrAddr = virt_to_bus(&hdr);
506 INF_3C90X.TransmitDPD.HdrLength = sizeof(hdr);
507 INF_3C90X.TransmitDPD.DataAddr = virt_to_bus(pkt);
508 INF_3C90X.TransmitDPD.DataLength = size + (1<<31);
509
510 /** Send the packet **/
31ddf9b3 511 outl(INF_3C90X.IOAddr + regDnListPtr_l, virt_to_bus(&(INF_3C90X.TransmitDPD)));
31ddf9b3
JW		 512 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 3 /* Unstall download */);
513
31ddf9b3
JW		 514 oneshot_start_ms(100);
515 while((inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0) && oneshot_running())
516 ;
517 if (!oneshot_running())
31ddf9b3 518 outputf("3c90x: Download engine pointer timeout");
748534f4 519
31ddf9b3
JW		 520 oneshot_start_ms(10); /* Give it 10 ms */
521 while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE) && oneshot_running())
522 ;
748534f4 523
31ddf9b3
JW		 524 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE))
525 {
047916ed
JW		 526 outputf("3c90x: tx timeout? txstat %02x", inb(INF_3C90X.IOAddr + regTxStatus_b));
527 outputf("3c90x: Gen sts %04x", inw(INF_3C90X.IOAddr + regCommandIntStatus_w));
31ddf9b3
JW		 528 continue;
529 }
530 status = inb(INF_3C90X.IOAddr + regTxStatus_b);
531 outb(INF_3C90X.IOAddr + regTxStatus_b, 0x00);
532
31ddf9b3
JW		 533 /** successful completion (sans "interrupt Requested" bit) **/
534 if ((status & 0xbf) == 0x80)
535 return;
536
537 outputf("3c90x: Status (%hhX)", status);
538 /** check error codes **/
539 if (status & 0x02)
540 {
541 outputf("3c90x: Tx Reclaim Error (%hhX)", status);
542 a3c90x_reset();
543 } else if (status & 0x04) {
544 outputf("3c90x: Tx Status Overflow (%hhX)", status);
545 for (i=0; i<32; i++)
546 _outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
547 /** must re-enable after max collisions before re-issuing tx **/
548 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
549 } else if (status & 0x08) {
550 outputf("3c90x: Tx Max Collisions (%hhX)", status);
551 /** must re-enable after max collisions before re-issuing tx **/
552 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
553 } else if (status & 0x10) {
554 outputf("3c90x: Tx Underrun (%hhX)", status);
555 a3c90x_reset();
556 } else if (status & 0x20) {
557 outputf("3c90x: Tx Jabber (%hhX)", status);
558 a3c90x_reset();
559 } else if ((status & 0x80) != 0x80) {
560 outputf("3c90x: Internal Error - Incomplete Transmission (%hhX)", status);
561 a3c90x_reset();
562 }
748534f4
JP		 563 }
564
31ddf9b3
JW		 565 /** failed after RETRY attempts **/
566 outputf("3c90x: Failed to send after %d retries", retries);
567 return;
568}
748534f4
JP		 569
570
571
572/*** a3c90x_poll: exported routine that waits for a certain length of time
573 *** for a packet, and if it sees none, returns 0. This routine should
574 *** copy the packet to nic->packet if it gets a packet and set the size
575 *** in nic->packetlen. Return 1 if a packet was found.
576 ***/
577static int
578a3c90x_poll(struct nic *nic, int retrieve)
579 {
580 int i, errcode;
581
582 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
583 {
584 return 0;
585 }
586
587 if ( ! retrieve ) return 1;
588
589 /** we don't need to acknowledge rxComplete -- the upload engine
590 ** does it for us.
591 **/
592
593 /** Build the up-load descriptor **/
594 INF_3C90X.ReceiveUPD.UpNextPtr = 0;
595 INF_3C90X.ReceiveUPD.UpPktStatus = 0;
596 INF_3C90X.ReceiveUPD.DataAddr = virt_to_bus(nic->packet);
597 INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
598
599 /** Submit the upload descriptor to the NIC **/
c2e34447 600 _outl(virt_to_bus(&(INF_3C90X.ReceiveUPD)),
748534f4
JP		 601 INF_3C90X.IOAddr + regUpListPtr_l);
602
603 /** Wait for upload completion (upComplete(15) or upError (14)) **/
604 for(i=0;i<40000;i++);
605 while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
606 for(i=0;i<40000;i++);
607
608 /** Check for Error (else we have good packet) **/
609 if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
610 {
611 errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
612 if (errcode & (1<<16))
613 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);
614 else if (errcode & (1<<17))
615 outputf("3C90X: Runt Frame (%hX)",errcode>>16);
616 else if (errcode & (1<<18))
617 outputf("3C90X: Alignment Error (%hX)",errcode>>16);
618 else if (errcode & (1<<19))
619 outputf("3C90X: CRC Error (%hX)",errcode>>16);
620 else if (errcode & (1<<20))
621 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);
622 else
623 outputf("3C90X: Packet error (%hX)",errcode>>16);
624 return 0;
625 }
626
627 /** Ok, got packet. Set length in nic->packetlen. **/
628 nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
629
630 return 1;
631 }
632
633
634
635/*** a3c90x_disable: exported routine to disable the card. What's this for?
636 *** the eepro100.c driver didn't have one, so I just left this one empty too.
637 *** Ideas anyone?
638 *** Must turn off receiver at least so stray packets will not corrupt memory
639 *** [Ken]
640 ***/
641void a3c90x_disable(struct dev *dev)
642{
643 /* reset and disable merge */
644 a3c90x_reset();
645 /* Disable the receiver and transmitter. */
c2e34447
JW		 646 _outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
647 _outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
748534f4
JP		 648}
649
650
651/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
652 *** initialization. If this routine is called, the pci functions did find the
653 *** card. We just have to init it here.
654 ***/
655static int a3c90x_probe(struct pci_dev * pci, void * data)
656{
748534f4
JP		 657 INF_3C90X.is3c556 = (pci->did == 0x6055);
658
659 int i, c;
c2e34447 660 unsigned short eeprom[0x100];
748534f4
JP		 661 unsigned int cfg;
662 unsigned int mopt;
663 unsigned int mstat;
664 unsigned short linktype;
665#define HWADDR_OFFSET 10
666
667 unsigned long ioaddr = 0;
668 for (i = 0; i < 6; i++) {
669 if (pci->bars[i].type == PCI_BAR_IO) {
670 ioaddr = pci->bars[i].addr;
671 break;
672 }
673 }
674
675 if (ioaddr == 0)
c2e34447
JW		 676 {
677 outputf("3c90x: Unable to find I/O address");
678 return 0;
679 }
680
681 /* Power it on */
682 pci_write16(pci->bus, pci->dev, pci->fn, 0xE0,
683 pci_read16(pci->bus, pci->dev, pci->fn, 0xE0) & ~0x3);
684
685 outputf("3c90x: Picked I/O address %04x", ioaddr);
047916ed 686 pci_bother_add(pci);
42125f27
JP		 687 nic.ioaddr = ioaddr & ~3;
688 nic.irqno = 0;
748534f4 689
c2e34447 690 INF_3C90X.IOAddr = ioaddr;
748534f4
JP		 691 INF_3C90X.CurrentWindow = 255;
692 switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
693 {
694 case 0x9000: /** 10 Base TPO **/
695 case 0x9001: /** 10/100 T4 **/
696 case 0x9050: /** 10/100 TPO **/
697 case 0x9051: /** 10 Base Combo **/
698 INF_3C90X.isBrev = 0;
699 break;
700
701 case 0x9004: /** 10 Base TPO **/
702 case 0x9005: /** 10 Base Combo **/
703 case 0x9006: /** 10 Base TPO and Base2 **/
704 case 0x900A: /** 10 Base FL **/
705 case 0x9055: /** 10/100 TPO **/
706 case 0x9056: /** 10/100 T4 **/
707 case 0x905A: /** 10 Base FX **/
708 default:
709 INF_3C90X.isBrev = 1;
710 break;
711 }
712
713 /** Load the EEPROM contents **/
714 if (INF_3C90X.isBrev)
715 {
c2e34447 716 for(i=0;i<=/*0x20*/0x7F;i++)
748534f4
JP		 717 {
718 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
719 }
720
721#ifdef CFG_3C90X_BOOTROM_FIX
722 /** Set xcvrSelect in InternalConfig in eeprom. **/
723 /* only necessary for 3c905b revision cards with boot PROM bug!!! */
724 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
725#endif
726
727#ifdef CFG_3C90X_XCVR
728 if (CFG_3C90X_XCVR == 255)
729 {
730 /** Clear the LanWorks register **/
731 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
732 }
733 else
734 {
735 /** Set the selected permanent-xcvrSelect in the
736 ** LanWorks register
737 **/
738 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
739 XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
740 }
741#endif
742 }
743 else
744 {
c2e34447 745 for(i=0;i<=/*0x17*/0x7F;i++)
748534f4
JP		 746 {
747 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
748 }
749 }
750
751 /** Print identification message **/
752#ifdef CFG_3C90X_BOOTROM_FIX
753 if (INF_3C90X.isBrev)
754 {
755 outputf("NOTE: 3c905b bootrom fix enabled; has side "
756 "effects. See 3c90x.txt for info.");
757 }
758#endif
759
760 /** Retrieve the Hardware address and print it on the screen. **/
761 INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
762 INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
763 INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
764 INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
765 INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
766 INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
c2e34447
JW		 767 outputf("MAC Address = %02x:%02x:%02x:%02x:%02x:%02x",
768 INF_3C90X.HWAddr[0],
769 INF_3C90X.HWAddr[1],
770 INF_3C90X.HWAddr[2],
771 INF_3C90X.HWAddr[3],
772 INF_3C90X.HWAddr[4],
773 INF_3C90X.HWAddr[5]);
748534f4
JP		 774
775 /** 3C556: Invert MII power **/
776 if (INF_3C90X.is3c556) {
777 unsigned int tmp;
31ddf9b3 778 _set_window(INF_3C90X.IOAddr, winAddressing2);
748534f4
JP		 779 tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
780 tmp |= 0x4000;
c2e34447 781 _outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
748534f4
JP		 782 }
783
784 /* Test if the link is good, if not continue */
31ddf9b3 785 _set_window(INF_3C90X.IOAddr, winDiagnostics4);
748534f4
JP		 786 mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
787 if((mstat & (1<<11)) == 0) {
788 outputf("Valid link not established");
789 return 0;
790 }
791
792 /** Program the MAC address into the station address registers **/
31ddf9b3 793 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 794 _outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
795 _outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
796 _outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
797 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
798 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
799 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 800
801 /** Fill in our entry in the etherboot arp table **/
802/* XXX ? for lwip?
803 for(i=0;i<ETH_ALEN;i++)
42125f27 804 nic.node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
748534f4
JP		 805*/
806
807 /** Read the media options register, print a message and set default
808 ** xcvr.
809 **
810 ** Uses Media Option command on B revision, Reset Option on non-B
811 ** revision cards -- same register address
812 **/
31ddf9b3 813 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 814 mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
815
816 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
817 if (! INF_3C90X.isBrev)
818 {
819 mopt &= 0x7F;
820 }
821
822 outputf("Connectors present: ");
823 c = 0;
824 linktype = 0x0008;
825 if (mopt & 0x01)
826 {
827 outputf("%s100Base-T4",(c++)?", ":"");
828 linktype = 0x0006;
829 }
830 if (mopt & 0x04)
831 {
832 outputf("%s100Base-FX",(c++)?", ":"");
833 linktype = 0x0005;
834 }
835 if (mopt & 0x10)
836 {
837 outputf("%s10Base-2",(c++)?", ":"");
838 linktype = 0x0003;
839 }
840 if (mopt & 0x20)
841 {
842 outputf("%sAUI",(c++)?", ":"");
843 linktype = 0x0001;
844 }
845 if (mopt & 0x40)
846 {
847 outputf("%sMII",(c++)?", ":"");
848 linktype = 0x0006;
849 }
850 if ((mopt & 0xA) == 0xA)
851 {
852 outputf("%s10Base-T / 100Base-TX",(c++)?", ":"");
853 linktype = 0x0008;
854 }
855 else if ((mopt & 0xA) == 0x2)
856 {
857 outputf("%s100Base-TX",(c++)?", ":"");
858 linktype = 0x0008;
859 }
860 else if ((mopt & 0xA) == 0x8)
861 {
862 outputf("%s10Base-T",(c++)?", ":"");
863 linktype = 0x0008;
864 }
865 outputf(".");
866
867 /** Determine transceiver type to use, depending on value stored in
868 ** eeprom 0x16
869 **/
870 if (INF_3C90X.isBrev)
871 {
872 if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
873 {
874 /** User-defined **/
875 linktype = eeprom[0x16] & 0x000F;
876 }
877 }
878 else
879 {
880#ifdef CFG_3C90X_XCVR
881 if (CFG_3C90X_XCVR != 255)
882 linktype = CFG_3C90X_XCVR;
883#endif /* CFG_3C90X_XCVR */
884
885 /** I don't know what MII MAC only mode is!!! **/
886 if (linktype == 0x0009)
887 {
888 if (INF_3C90X.isBrev)
889 outputf("WARNING: MII External MAC Mode only supported on B-revision "
890 "cards!!!!\nFalling Back to MII Mode\n");
891 linktype = 0x0006;
892 }
893 }
894
895 /** enable DC converter for 10-Base-T **/
896 if (linktype == 0x0003)
897 {
31ddf9b3 898 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 899 }
900
901 /** Set the link to the type we just determined. **/
31ddf9b3 902 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 903 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
904 cfg &= ~(0xF<<20);
905 cfg |= (linktype<<20);
c2e34447 906 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 907
908 /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
31ddf9b3 909 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 910 if (!INF_3C90X.isBrev)
c2e34447 911 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
748534f4 912
31ddf9b3 913 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 914
915 /**
916 ** reset of the receiver on B-revision cards re-negotiates the link
917 ** takes several seconds (a computer eternity)
918 **/
919 if (INF_3C90X.isBrev)
31ddf9b3 920 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 921 else
31ddf9b3 922 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
748534f4
JP		 923
924 /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
31ddf9b3
JW		 925 _issue_command(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
926 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4
JP		 927
928
929 /**
930 ** set Indication and Interrupt flags , acknowledge any IRQ's
931 **/
31ddf9b3
JW		 932 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
933 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
934 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 935
936 /* * Set our exported functions **/
42125f27
JP		 937 nic.poll = a3c90x_poll;
938 nic.transmit = a3c90x_transmit;
c2e34447 939 eth_register(&nic);
748534f4
JP		 940
941 return 1;
942}
943
944static struct pci_id a3c90x_nics[] = {
945/* Original 90x revisions: */
946PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
947PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
948PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
949PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
950PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
951/* Newer 90xB revisions: */
952PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
953PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
954PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
955PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
956PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
957PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
958PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
959PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
960/* Newer 90xC revision: */
961PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
962PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
963PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
964PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
965PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
966PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
967PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
968PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
969PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
970};
971
972struct pci_driver a3c90x_driver = {
973 .name = "3C90X",
974 .probe = a3c90x_probe,
975 .ids = a3c90x_nics,
976 .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
977};
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