]> Joshua Wise's Git repositories - netwatch.git/blame - net/3c90x.c
git.joshuawise.com / netwatch.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Manage to get a nice big packet queue going inside lwIP.
[netwatch.git] / net / 3c90x.c
CommitLineData
748534f4
JP		 1/*
2 * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
3 * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
4 * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
5 *
6 * This program Copyright (C) 1999 LightSys Technology Services, Inc.
7 * Portions Copyright (C) 1999 Steve Smith
8 *
9 * This program may be re-distributed in source or binary form, modified,
10 * sold, or copied for any purpose, provided that the above copyright message
11 * and this text are included with all source copies or derivative works, and
12 * provided that the above copyright message and this text are included in the
13 * documentation of any binary-only distributions. This program is distributed
14 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
15 * PURPOSE or MERCHANTABILITY. Please read the associated documentation
16 * "3c90x.txt" before compiling and using this driver.
17 *
18 * --------
19 *
20 * Program written with the assistance of the 3com documentation for
21 * the 3c905B-TX card, as well as with some assistance from the 3c59x
22 * driver Donald Becker wrote for the Linux kernel, and with some assistance
23 * from the remainder of the Etherboot distribution.
24 *
25 * REVISION HISTORY:
26 *
27 * v0.10 1-26-1998 GRB Initial implementation.
28 * v0.90 1-27-1998 GRB System works.
29 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31 * Re-wrote poll and transmit for
32 * better error recovery and heavy
33 * network traffic operation
34 * v2.01 5-26-2003 NN Fixed driver alignment issue which
35 * caused system lockups if driver structures
36 * not 8-byte aligned.
37 *
38 */
39
40#include "etherboot-compat.h"
42125f27 41#include "net.h"
748534f4
JP		 42#include <timer.h>
43#include <io.h>
44#include <pci.h>
7a914840 45#include <pci-bother.h>
748534f4
JP		 46#include <minilib.h>
47#include <output.h>
68beefa8 48#include <paging.h>
748534f4
JP		 49
50#define XCVR_MAGIC (0x5A00)
51/** any single transmission fails after 16 collisions or other errors
52 ** this is the number of times to retry the transmission -- this should
53 ** be plenty
54 **/
c25f3f39 55#define XMIT_RETRIES 5
748534f4
JP		 56
57/*** Register definitions for the 3c905 ***/
58enum Registers
59 {
60 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
61 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
62 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
63 regDebugControl_w = 0x74, /** 905B Revision Only **/
64 regDebugData_l = 0x70, /** 905B Revision Only **/
65 regRealTimeCnt_l = 0x40, /** Universal **/
66 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
67 regUpPoll_b = 0x3d, /** 905B Revision Only **/
68 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
69 regUpListPtr_l = 0x38, /** Universal **/
70 regCountdown_w = 0x36, /** Universal **/
71 regFreeTimer_w = 0x34, /** Universal **/
72 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
73 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
74 regDnPoll_b = 0x2d, /** 905B Revision Only **/
75 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
76 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
77 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
78 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
79 /** **/
80 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
81 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
82 regTimer_b = 0x1a, /** Universal **/
83 regTxPktId_b = 0x18, /** 905B Revision Only **/
84 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
85 };
86
87/** following are windowed registers **/
88enum Registers7
89 {
90 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
91 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
92 regVlanMask_7_w = 0x00, /** 905B Revision Only **/
93 };
94
95enum Registers6
96 {
97 regBytesXmittedOk_6_w = 0x0c, /** Universal **/
98 regBytesRcvdOk_6_w = 0x0a, /** Universal **/
99 regUpperFramesOk_6_b = 0x09, /** Universal **/
100 regFramesDeferred_6_b = 0x08, /** Universal **/
101 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
102 regFramesXmittedOk_6_b = 0x06, /** Universal **/
103 regRxOverruns_6_b = 0x05, /** Universal **/
104 regLateCollisions_6_b = 0x04, /** Universal **/
105 regSingleCollisions_6_b = 0x03, /** Universal **/
106 regMultipleCollisions_6_b = 0x02, /** Universal **/
107 regSqeErrors_6_b = 0x01, /** Universal **/
108 regCarrierLost_6_b = 0x00, /** Universal **/
109 };
110
111enum Registers5
112 {
113 regIndicationEnable_5_w = 0x0c, /** Universal **/
114 regInterruptEnable_5_w = 0x0a, /** Universal **/
115 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
116 regRxFilter_5_b = 0x08, /** Universal **/
117 regRxEarlyThresh_5_w = 0x06, /** Universal **/
118 regTxStartThresh_5_w = 0x00, /** Universal **/
119 };
120
121enum Registers4
122 {
123 regUpperBytesOk_4_b = 0x0d, /** Universal **/
124 regBadSSD_4_b = 0x0c, /** Universal **/
125 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
126 regPhysicalMgmt_4_w = 0x08, /** Universal **/
127 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
128 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
129 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
130 };
131
132enum Registers3
133 {
134 regTxFree_3_w = 0x0c, /** Universal **/
135 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
136 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
137 /** Reset Options on Non-B Revision **/
138 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
139 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
140 regInternalConfig_3_l = 0x00, /** Universal, different bit **/
141 /** definitions, pg 59 **/
142 };
143
144enum Registers2
145 {
146 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
147 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
148 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
149 };
150
151enum Registers1
152 {
153 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
154 };
155
156enum Registers0
157 {
158 regEepromData_0_w = 0x0c, /** Universal **/
159 regEepromCommand_0_w = 0x0a, /** Universal **/
160 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
161 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
162 };
163
164
165/*** The names for the eight register windows ***/
166enum Windows
167 {
168 winPowerVlan7 = 0x07,
169 winStatistics6 = 0x06,
170 winTxRxControl5 = 0x05,
171 winDiagnostics4 = 0x04,
172 winTxRxOptions3 = 0x03,
173 winAddressing2 = 0x02,
174 winUnused1 = 0x01,
175 winEepromBios0 = 0x00,
176 };
177
178
179/*** Command definitions for the 3c90X ***/
180enum Commands
181 {
182 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
183 cmdSelectRegisterWindow = 0x01, /** Universal **/
184 cmdEnableDcConverter = 0x02, /** **/
185 cmdRxDisable = 0x03, /** **/
186 cmdRxEnable = 0x04, /** Universal **/
187 cmdRxReset = 0x05, /** Universal **/
188 cmdStallCtl = 0x06, /** Universal **/
189 cmdTxEnable = 0x09, /** Universal **/
190 cmdTxDisable = 0x0A, /** **/
191 cmdTxReset = 0x0B, /** Universal **/
192 cmdRequestInterrupt = 0x0C, /** **/
193 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
194 cmdSetInterruptEnable = 0x0E, /** Universal **/
195 cmdSetIndicationEnable = 0x0F, /** Universal **/
196 cmdSetRxFilter = 0x10, /** Universal **/
197 cmdSetRxEarlyThresh = 0x11, /** **/
198 cmdSetTxStartThresh = 0x13, /** **/
199 cmdStatisticsEnable = 0x15, /** **/
200 cmdStatisticsDisable = 0x16, /** **/
201 cmdDisableDcConverter = 0x17, /** **/
202 cmdSetTxReclaimThresh = 0x18, /** **/
203 cmdSetHashFilterBit = 0x19, /** **/
204 };
205
206
207/*** Values for int status register bitmask **/
208#define INT_INTERRUPTLATCH (1<<0)
209#define INT_HOSTERROR (1<<1)
210#define INT_TXCOMPLETE (1<<2)
211#define INT_RXCOMPLETE (1<<4)
212#define INT_RXEARLY (1<<5)
213#define INT_INTREQUESTED (1<<6)
214#define INT_UPDATESTATS (1<<7)
215#define INT_LINKEVENT (1<<8)
216#define INT_DNCOMPLETE (1<<9)
217#define INT_UPCOMPLETE (1<<10)
218#define INT_CMDINPROGRESS (1<<12)
219#define INT_WINDOWNUMBER (7<<13)
220
221
222/*** TX descriptor ***/
223typedef struct
224 {
225 unsigned int DnNextPtr;
226 unsigned int FrameStartHeader;
54d4b877
JW		 227 struct {
228 unsigned int addr;
229 unsigned int len;
230 } __attribute ((aligned(8))) segments[64];
748534f4
JP		 231 }
232 TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
233
234/*** RX descriptor ***/
235typedef struct
236 {
237 unsigned int UpNextPtr;
238 unsigned int UpPktStatus;
239 unsigned int DataAddr;
240 unsigned int DataLength;
241 }
242 RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
243
244/*** Global variables ***/
245static struct
246 {
247 unsigned int is3c556;
248 unsigned char isBrev;
249 unsigned char CurrentWindow;
250 unsigned int IOAddr;
251 unsigned char HWAddr[ETH_ALEN];
252 TXD TransmitDPD;
253 RXD ReceiveUPD;
254 }
255 INF_3C90X;
7a914840 256static struct nic nic;
748534f4 257
c2e34447
JW		 258#define _outl(v,a) outl((a),(v))
259#define _outw(v,a) outw((a),(v))
260#define _outb(v,a) outb((a),(v))
748534f4 261
31ddf9b3
JW		 262static int _issue_command(int ioaddr, int cmd, int param)
263{
264 outw(ioaddr + regCommandIntStatus_w, (cmd << 11) | param);
748534f4 265
31ddf9b3
JW		 266 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
267 ;
748534f4 268
31ddf9b3
JW		 269 return 0;
270}
748534f4
JP		 271
272
273/*** a3c90x_internal_SetWindow: selects a register window set.
274 ***/
31ddf9b3
JW		 275static int _set_window(int ioaddr, int window)
276{
277 if (INF_3C90X.CurrentWindow == window)
278 return 0;
748534f4 279
31ddf9b3 280 _issue_command(ioaddr, cmdSelectRegisterWindow, window);
748534f4
JP		 281 INF_3C90X.CurrentWindow = window;
282
31ddf9b3
JW		 283 return 0;
284}
748534f4
JP		 285
286
287/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
288 ***/
289static unsigned short
290a3c90x_internal_ReadEeprom(int ioaddr, int address)
c2e34447
JW		 291{
292 unsigned short val;
748534f4
JP		 293
294 /** Select correct window **/
31ddf9b3 295 _set_window(INF_3C90X.IOAddr, winEepromBios0);
748534f4
JP		 296
297 /** Make sure the eeprom isn't busy **/
c2e34447
JW		 298 do
299 {
300 int i;
301 for (i = 0; i < 165; i++)
302 inb(0x80); /* wait 165 usec */
303 }
304 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
748534f4
JP		 305
306 /** Read the value. **/
307 if (INF_3C90X.is3c556)
c2e34447 308 _outw(address + (0x230), ioaddr + regEepromCommand_0_w);
748534f4 309 else
c2e34447 310 _outw(address + 0x80, ioaddr + regEepromCommand_0_w);
748534f4 311
c2e34447
JW		 312 do
313 {
314 int i;
315 for (i = 0; i < 165; i++)
316 inb(0x80); /* wait 165 usec */
317 }
318 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
319 val = inw(ioaddr + regEepromData_0_w);
320
321 return val;
322}
748534f4
JP		 323
324
325#ifdef CFG_3C90X_BOOTROM_FIX
326/*** a3c90x_internal_WriteEepromWord - write a physical word of
327 *** data to the onboard serial eeprom (not the BIOS prom, but the
328 *** nvram in the card that stores, among other things, the MAC
329 *** address).
330 ***/
331static int
332a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
333 {
334 /** Select register window **/
31ddf9b3 335 _set_window(ioaddr, winEepromBios0);
748534f4
JP		 336
337 /** Verify Eeprom not busy **/
338 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
339
340 /** Issue WriteEnable, and wait for completion. **/
c2e34447 341 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 342 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
343
344 /** Issue EraseRegister, and wait for completion. **/
c2e34447 345 _outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 346 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
347
348 /** Send the new data to the eeprom, and wait for completion. **/
c2e34447
JW		 349 _outw(value, ioaddr + regEepromData_0_w);
350 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 351 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
352
353 /** Burn the new data into the eeprom, and wait for completion. **/
c2e34447 354 _outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 355 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
356
357 return 0;
358 }
359#endif
360
361#ifdef CFG_3C90X_BOOTROM_FIX
362/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
363 *** and re-compute the eeprom checksum.
364 ***/
365static int
366a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
367 {
368 int cksum = 0,v;
369 int i;
370 int maxAddress, cksumAddress;
371
372 if (INF_3C90X.isBrev)
373 {
374 maxAddress=0x1f;
375 cksumAddress=0x20;
376 }
377 else
378 {
379 maxAddress=0x16;
380 cksumAddress=0x17;
381 }
382
383 /** Write the value. **/
384 if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
385 return -1;
386
387 /** Recompute the checksum. **/
388 for(i=0;i<=maxAddress;i++)
389 {
390 v = a3c90x_internal_ReadEeprom(ioaddr, i);
391 cksum ^= (v & 0xFF);
392 cksum ^= ((v>>8) & 0xFF);
393 }
394 /** Write the checksum to the location in the eeprom **/
395 if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
396 return -1;
397
398 return 0;
399 }
400#endif
401
402/*** a3c90x_reset: exported function that resets the card to its default
403 *** state. This is so the Linux driver can re-set the card up the way
404 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
405 *** not alter the selected transceiver that we used to download the boot
406 *** image.
407 ***/
408static void a3c90x_reset(void)
409 {
410#ifdef CFG_3C90X_PRESERVE_XCVR
411 int cfg;
412 /** Read the current InternalConfig value. **/
31ddf9b3 413 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 414 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
415#endif
416
417 /** Send the reset command to the card **/
99182958 418 outputf("3c90x: issuing RESET");
31ddf9b3 419 _issue_command(INF_3C90X.IOAddr, cmdGlobalReset, 0);
748534f4
JP		 420
421 /** global reset command resets station mask, non-B revision cards
422 ** require explicit reset of values
423 **/
31ddf9b3 424 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 425 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
426 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
427 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 428
429#ifdef CFG_3C90X_PRESERVE_XCVR
430 /** Re-set the original InternalConfig value from before reset **/
31ddf9b3 431 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
c2e34447 432 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 433
434 /** enable DC converter for 10-Base-T **/
435 if ((cfg&0x0300) == 0x0300)
436 {
31ddf9b3 437 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 438 }
439#endif
440
441 /** Issue transmit reset, wait for command completion **/
31ddf9b3 442 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 443 if (! INF_3C90X.isBrev)
c2e34447 444 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
31ddf9b3 445 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 446
447 /**
448 ** reset of the receiver on B-revision cards re-negotiates the link
449 ** takes several seconds (a computer eternity)
450 **/
451 if (INF_3C90X.isBrev)
31ddf9b3 452 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 453 else
31ddf9b3
JW		 454 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
455 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
456 ;
457 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4 458
31ddf9b3 459 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
748534f4 460 /** enable rxComplete and txComplete **/
31ddf9b3 461 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
748534f4 462 /** acknowledge any pending status flags **/
31ddf9b3 463 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 464
465 return;
466 }
467
468
469
470/*** a3c90x_transmit: exported function that transmits a packet. Does not
471 *** return any particular status. Parameters are:
472 *** dest_addr[6] - destination address, ethernet;
473 *** proto - protocol type (ARP, IP, etc);
474 *** size - size of the non-header part of the packet that needs transmitted;
475 *** pkt - the pointer to the packet data itself.
476 ***/
477static void
54d4b877 478a3c90x_transmit(struct pbuf *p)
31ddf9b3 479{
31ddf9b3 480 unsigned char status;
3dd054cf 481 static unsigned int stillwaiting = 0;
54d4b877 482 unsigned int n, len;
f8903fdd
JW		 483
484 if (stillwaiting)
485 {
486 while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE) && oneshot_running())
487 ;
488 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE))
489 {
490 outputf("3c90x: tx timeout? txstat %02x", inb(INF_3C90X.IOAddr + regTxStatus_b));
491 outputf("3c90x: Gen sts %04x", inw(INF_3C90X.IOAddr + regCommandIntStatus_w));
492 }
493 status = inb(INF_3C90X.IOAddr + regTxStatus_b);
494 outb(INF_3C90X.IOAddr + regTxStatus_b, 0x00);
495 stillwaiting = 0;
496 }
3dd054cf 497
037ce545
JW		 498 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 2 /* Stall download */);
499
500 /** Setup the DPD (download descriptor) **/
501 INF_3C90X.TransmitDPD.DnNextPtr = 0;
54d4b877
JW		 502 len = 0;
503 n = 0;
504 for (; p; p = p->next)
505 {
d401e73e 506 INF_3C90X.TransmitDPD.segments[n].addr = v2p(p->payload);
54d4b877
JW		 507 INF_3C90X.TransmitDPD.segments[n].len = p->len | (p->next ? 0 : (1 << 31));
508 len += p->len;
509 n++;
510 }
037ce545 511 /** set notification for transmission completion (bit 15) **/
54d4b877 512 INF_3C90X.TransmitDPD.FrameStartHeader = (len) | 0x8000;
037ce545 513
54d4b877
JW		 514 outputf("3c90x: Sending %d byte %d seg packet", len, n);
515
037ce545
JW		 516 /** Send the packet **/
517 outl(INF_3C90X.IOAddr + regDnListPtr_l, v2p(&(INF_3C90X.TransmitDPD)));
518 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 3 /* Unstall download */);
31ddf9b3 519
037ce545
JW		 520 oneshot_start_ms(10);
521 while((inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0) && oneshot_running())
522 ;
523 if (!oneshot_running())
524 {
525 outputf("3c90x: Download engine pointer timeout");
526 return;
527 }
3dd054cf 528
037ce545
JW		 529 oneshot_start_ms(10);
530 stillwaiting = 1;
31ddf9b3 531
3dd054cf 532#if 0
037ce545
JW		 533 /** successful completion (sans "interrupt Requested" bit) **/
534 if ((status & 0xbf) == 0x80)
535 return;
31ddf9b3 536
037ce545
JW		 537 outputf("3c90x: Status (%hhX)", status);
538 /** check error codes **/
539 if (status & 0x02)
540 {
541 outputf("3c90x: Tx Reclaim Error (%hhX)", status);
542 a3c90x_reset();
543 } else if (status & 0x04) {
544 outputf("3c90x: Tx Status Overflow (%hhX)", status);
545 for (i=0; i<32; i++)
546 _outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
547 /** must re-enable after max collisions before re-issuing tx **/
548 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
549 } else if (status & 0x08) {
550 outputf("3c90x: Tx Max Collisions (%hhX)", status);
551 /** must re-enable after max collisions before re-issuing tx **/
552 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
553 } else if (status & 0x10) {
554 outputf("3c90x: Tx Underrun (%hhX)", status);
555 a3c90x_reset();
556 } else if (status & 0x20) {
557 outputf("3c90x: Tx Jabber (%hhX)", status);
558 a3c90x_reset();
559 } else if ((status & 0x80) != 0x80) {
560 outputf("3c90x: Internal Error - Incomplete Transmission (%hhX)", status);
561 a3c90x_reset();
748534f4 562 }
037ce545 563#endif
31ddf9b3 564}
748534f4
JP		 565
566
567
568/*** a3c90x_poll: exported routine that waits for a certain length of time
569 *** for a packet, and if it sees none, returns 0. This routine should
570 *** copy the packet to nic->packet if it gets a packet and set the size
571 *** in nic->packetlen. Return 1 if a packet was found.
572 ***/
573static int
574a3c90x_poll(struct nic *nic, int retrieve)
575 {
576 int i, errcode;
577
578 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
579 {
580 return 0;
581 }
582
583 if ( ! retrieve ) return 1;
584
585 /** we don't need to acknowledge rxComplete -- the upload engine
586 ** does it for us.
587 **/
588
589 /** Build the up-load descriptor **/
590 INF_3C90X.ReceiveUPD.UpNextPtr = 0;
591 INF_3C90X.ReceiveUPD.UpPktStatus = 0;
923ea2c2 592 INF_3C90X.ReceiveUPD.DataAddr = v2p(nic->packet);
748534f4
JP		 593 INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
594
595 /** Submit the upload descriptor to the NIC **/
923ea2c2 596 _outl(v2p(&(INF_3C90X.ReceiveUPD)),
748534f4
JP		 597 INF_3C90X.IOAddr + regUpListPtr_l);
598
599 /** Wait for upload completion (upComplete(15) or upError (14)) **/
600 for(i=0;i<40000;i++);
601 while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
602 for(i=0;i<40000;i++);
603
604 /** Check for Error (else we have good packet) **/
605 if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
606 {
607 errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
608 if (errcode & (1<<16))
609 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);
610 else if (errcode & (1<<17))
611 outputf("3C90X: Runt Frame (%hX)",errcode>>16);
612 else if (errcode & (1<<18))
613 outputf("3C90X: Alignment Error (%hX)",errcode>>16);
614 else if (errcode & (1<<19))
615 outputf("3C90X: CRC Error (%hX)",errcode>>16);
616 else if (errcode & (1<<20))
617 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);
618 else
619 outputf("3C90X: Packet error (%hX)",errcode>>16);
620 return 0;
621 }
622
623 /** Ok, got packet. Set length in nic->packetlen. **/
624 nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
625
626 return 1;
627 }
628
629
630
631/*** a3c90x_disable: exported routine to disable the card. What's this for?
632 *** the eepro100.c driver didn't have one, so I just left this one empty too.
633 *** Ideas anyone?
634 *** Must turn off receiver at least so stray packets will not corrupt memory
635 *** [Ken]
636 ***/
637void a3c90x_disable(struct dev *dev)
638{
639 /* reset and disable merge */
640 a3c90x_reset();
641 /* Disable the receiver and transmitter. */
c2e34447
JW		 642 _outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
643 _outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
748534f4
JP		 644}
645
646
647/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
648 *** initialization. If this routine is called, the pci functions did find the
649 *** card. We just have to init it here.
650 ***/
651static int a3c90x_probe(struct pci_dev * pci, void * data)
652{
748534f4
JP		 653 INF_3C90X.is3c556 = (pci->did == 0x6055);
654
655 int i, c;
c2e34447 656 unsigned short eeprom[0x100];
748534f4
JP		 657 unsigned int cfg;
658 unsigned int mopt;
659 unsigned int mstat;
660 unsigned short linktype;
661#define HWADDR_OFFSET 10
662
663 unsigned long ioaddr = 0;
664 for (i = 0; i < 6; i++) {
665 if (pci->bars[i].type == PCI_BAR_IO) {
666 ioaddr = pci->bars[i].addr;
667 break;
668 }
669 }
670
671 if (ioaddr == 0)
c2e34447
JW		 672 {
673 outputf("3c90x: Unable to find I/O address");
674 return 0;
675 }
676
677 /* Power it on */
678 pci_write16(pci->bus, pci->dev, pci->fn, 0xE0,
679 pci_read16(pci->bus, pci->dev, pci->fn, 0xE0) & ~0x3);
680
681 outputf("3c90x: Picked I/O address %04x", ioaddr);
047916ed 682 pci_bother_add(pci);
42125f27
JP		 683 nic.ioaddr = ioaddr & ~3;
684 nic.irqno = 0;
748534f4 685
c2e34447 686 INF_3C90X.IOAddr = ioaddr;
748534f4
JP		 687 INF_3C90X.CurrentWindow = 255;
688 switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
689 {
690 case 0x9000: /** 10 Base TPO **/
691 case 0x9001: /** 10/100 T4 **/
692 case 0x9050: /** 10/100 TPO **/
693 case 0x9051: /** 10 Base Combo **/
694 INF_3C90X.isBrev = 0;
695 break;
696
697 case 0x9004: /** 10 Base TPO **/
698 case 0x9005: /** 10 Base Combo **/
699 case 0x9006: /** 10 Base TPO and Base2 **/
700 case 0x900A: /** 10 Base FL **/
701 case 0x9055: /** 10/100 TPO **/
702 case 0x9056: /** 10/100 T4 **/
703 case 0x905A: /** 10 Base FX **/
704 default:
705 INF_3C90X.isBrev = 1;
706 break;
707 }
708
709 /** Load the EEPROM contents **/
710 if (INF_3C90X.isBrev)
711 {
c2e34447 712 for(i=0;i<=/*0x20*/0x7F;i++)
748534f4
JP		 713 {
714 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
715 }
716
717#ifdef CFG_3C90X_BOOTROM_FIX
718 /** Set xcvrSelect in InternalConfig in eeprom. **/
719 /* only necessary for 3c905b revision cards with boot PROM bug!!! */
720 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
721#endif
722
723#ifdef CFG_3C90X_XCVR
724 if (CFG_3C90X_XCVR == 255)
725 {
726 /** Clear the LanWorks register **/
727 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
728 }
729 else
730 {
731 /** Set the selected permanent-xcvrSelect in the
732 ** LanWorks register
733 **/
734 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
735 XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
736 }
737#endif
738 }
739 else
740 {
c2e34447 741 for(i=0;i<=/*0x17*/0x7F;i++)
748534f4
JP		 742 {
743 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
744 }
745 }
746
747 /** Print identification message **/
748#ifdef CFG_3C90X_BOOTROM_FIX
749 if (INF_3C90X.isBrev)
750 {
751 outputf("NOTE: 3c905b bootrom fix enabled; has side "
752 "effects. See 3c90x.txt for info.");
753 }
754#endif
755
756 /** Retrieve the Hardware address and print it on the screen. **/
757 INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
758 INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
759 INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
760 INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
761 INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
762 INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
c2e34447
JW		 763 outputf("MAC Address = %02x:%02x:%02x:%02x:%02x:%02x",
764 INF_3C90X.HWAddr[0],
765 INF_3C90X.HWAddr[1],
766 INF_3C90X.HWAddr[2],
767 INF_3C90X.HWAddr[3],
768 INF_3C90X.HWAddr[4],
769 INF_3C90X.HWAddr[5]);
748534f4
JP		 770
771 /** 3C556: Invert MII power **/
772 if (INF_3C90X.is3c556) {
773 unsigned int tmp;
31ddf9b3 774 _set_window(INF_3C90X.IOAddr, winAddressing2);
748534f4
JP		 775 tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
776 tmp |= 0x4000;
c2e34447 777 _outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
748534f4
JP		 778 }
779
780 /* Test if the link is good, if not continue */
31ddf9b3 781 _set_window(INF_3C90X.IOAddr, winDiagnostics4);
748534f4
JP		 782 mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
783 if((mstat & (1<<11)) == 0) {
784 outputf("Valid link not established");
785 return 0;
786 }
787
788 /** Program the MAC address into the station address registers **/
31ddf9b3 789 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 790 _outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
791 _outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
792 _outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
793 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
794 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
795 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 796
797 /** Fill in our entry in the etherboot arp table **/
798/* XXX ? for lwip?
799 for(i=0;i<ETH_ALEN;i++)
42125f27 800 nic.node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
748534f4
JP		 801*/
802
803 /** Read the media options register, print a message and set default
804 ** xcvr.
805 **
806 ** Uses Media Option command on B revision, Reset Option on non-B
807 ** revision cards -- same register address
808 **/
31ddf9b3 809 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 810 mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
811
812 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
813 if (! INF_3C90X.isBrev)
814 {
815 mopt &= 0x7F;
816 }
817
818 outputf("Connectors present: ");
819 c = 0;
820 linktype = 0x0008;
821 if (mopt & 0x01)
822 {
823 outputf("%s100Base-T4",(c++)?", ":"");
824 linktype = 0x0006;
825 }
826 if (mopt & 0x04)
827 {
828 outputf("%s100Base-FX",(c++)?", ":"");
829 linktype = 0x0005;
830 }
831 if (mopt & 0x10)
832 {
833 outputf("%s10Base-2",(c++)?", ":"");
834 linktype = 0x0003;
835 }
836 if (mopt & 0x20)
837 {
838 outputf("%sAUI",(c++)?", ":"");
839 linktype = 0x0001;
840 }
841 if (mopt & 0x40)
842 {
843 outputf("%sMII",(c++)?", ":"");
844 linktype = 0x0006;
845 }
846 if ((mopt & 0xA) == 0xA)
847 {
848 outputf("%s10Base-T / 100Base-TX",(c++)?", ":"");
849 linktype = 0x0008;
850 }
851 else if ((mopt & 0xA) == 0x2)
852 {
853 outputf("%s100Base-TX",(c++)?", ":"");
854 linktype = 0x0008;
855 }
856 else if ((mopt & 0xA) == 0x8)
857 {
858 outputf("%s10Base-T",(c++)?", ":"");
859 linktype = 0x0008;
860 }
861 outputf(".");
862
863 /** Determine transceiver type to use, depending on value stored in
864 ** eeprom 0x16
865 **/
866 if (INF_3C90X.isBrev)
867 {
868 if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
869 {
870 /** User-defined **/
871 linktype = eeprom[0x16] & 0x000F;
872 }
873 }
874 else
875 {
876#ifdef CFG_3C90X_XCVR
877 if (CFG_3C90X_XCVR != 255)
878 linktype = CFG_3C90X_XCVR;
879#endif /* CFG_3C90X_XCVR */
880
881 /** I don't know what MII MAC only mode is!!! **/
882 if (linktype == 0x0009)
883 {
884 if (INF_3C90X.isBrev)
885 outputf("WARNING: MII External MAC Mode only supported on B-revision "
886 "cards!!!!\nFalling Back to MII Mode\n");
887 linktype = 0x0006;
888 }
889 }
890
891 /** enable DC converter for 10-Base-T **/
892 if (linktype == 0x0003)
893 {
31ddf9b3 894 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 895 }
896
897 /** Set the link to the type we just determined. **/
31ddf9b3 898 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 899 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
900 cfg &= ~(0xF<<20);
901 cfg |= (linktype<<20);
c2e34447 902 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 903
904 /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
31ddf9b3 905 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 906 if (!INF_3C90X.isBrev)
c2e34447 907 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
748534f4 908
31ddf9b3 909 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 910
911 /**
912 ** reset of the receiver on B-revision cards re-negotiates the link
913 ** takes several seconds (a computer eternity)
914 **/
915 if (INF_3C90X.isBrev)
31ddf9b3 916 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 917 else
31ddf9b3 918 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
748534f4
JP		 919
920 /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
31ddf9b3
JW		 921 _issue_command(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
922 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4
JP		 923
924
925 /**
926 ** set Indication and Interrupt flags , acknowledge any IRQ's
927 **/
31ddf9b3
JW		 928 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
929 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
930 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 931
932 /* * Set our exported functions **/
42125f27
JP		 933 nic.poll = a3c90x_poll;
934 nic.transmit = a3c90x_transmit;
47c41031 935 memcpy(nic.hwaddr, INF_3C90X.HWAddr, 6);
c2e34447 936 eth_register(&nic);
748534f4
JP		 937
938 return 1;
939}
940
941static struct pci_id a3c90x_nics[] = {
942/* Original 90x revisions: */
943PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
944PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
945PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
946PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
947PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
948/* Newer 90xB revisions: */
949PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
950PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
951PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
952PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
953PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
954PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
955PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
956PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
957/* Newer 90xC revision: */
958PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
959PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
960PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
961PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
962PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
963PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
964PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
965PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
966PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
967};
968
969struct pci_driver a3c90x_driver = {
970 .name = "3C90X",
971 .probe = a3c90x_probe,
972 .ids = a3c90x_nics,
973 .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
974};
NetWatch system management mode lights out box
This page took 0.111577 seconds and 4 git commands to generate.