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CommitLineData
748534f4
JP		 1/*
2 * 3c90x.c -- This file implements the 3c90x driver for etherboot. Written
3 * by Greg Beeley, Greg.Beeley@LightSys.org. Modified by Steve Smith,
4 * Steve.Smith@Juno.Com. Alignment bug fix Neil Newell (nn@icenoir.net).
5 *
6 * This program Copyright (C) 1999 LightSys Technology Services, Inc.
7 * Portions Copyright (C) 1999 Steve Smith
8 *
9 * This program may be re-distributed in source or binary form, modified,
10 * sold, or copied for any purpose, provided that the above copyright message
11 * and this text are included with all source copies or derivative works, and
12 * provided that the above copyright message and this text are included in the
13 * documentation of any binary-only distributions. This program is distributed
14 * WITHOUT ANY WARRANTY, without even the warranty of FITNESS FOR A PARTICULAR
15 * PURPOSE or MERCHANTABILITY. Please read the associated documentation
16 * "3c90x.txt" before compiling and using this driver.
17 *
18 * --------
19 *
20 * Program written with the assistance of the 3com documentation for
21 * the 3c905B-TX card, as well as with some assistance from the 3c59x
22 * driver Donald Becker wrote for the Linux kernel, and with some assistance
23 * from the remainder of the Etherboot distribution.
24 *
25 * REVISION HISTORY:
26 *
27 * v0.10 1-26-1998 GRB Initial implementation.
28 * v0.90 1-27-1998 GRB System works.
29 * v1.00pre1 2-11-1998 GRB Got prom boot issue fixed.
30 * v2.0 9-24-1999 SCS Modified for 3c905 (from 3c905b code)
31 * Re-wrote poll and transmit for
32 * better error recovery and heavy
33 * network traffic operation
34 * v2.01 5-26-2003 NN Fixed driver alignment issue which
35 * caused system lockups if driver structures
36 * not 8-byte aligned.
37 *
38 */
39
40#include "etherboot-compat.h"
42125f27 41#include "net.h"
748534f4
JP		 42#include <timer.h>
43#include <io.h>
44#include <pci.h>
7a914840 45#include <pci-bother.h>
748534f4
JP		 46#include <minilib.h>
47#include <output.h>
68beefa8 48#include <paging.h>
748534f4
JP		 49
50#define XCVR_MAGIC (0x5A00)
51/** any single transmission fails after 16 collisions or other errors
52 ** this is the number of times to retry the transmission -- this should
53 ** be plenty
54 **/
c25f3f39 55#define XMIT_RETRIES 5
748534f4
JP		 56
57/*** Register definitions for the 3c905 ***/
58enum Registers
59 {
60 regPowerMgmtCtrl_w = 0x7c, /** 905B Revision Only **/
61 regUpMaxBurst_w = 0x7a, /** 905B Revision Only **/
62 regDnMaxBurst_w = 0x78, /** 905B Revision Only **/
63 regDebugControl_w = 0x74, /** 905B Revision Only **/
64 regDebugData_l = 0x70, /** 905B Revision Only **/
65 regRealTimeCnt_l = 0x40, /** Universal **/
66 regUpBurstThresh_b = 0x3e, /** 905B Revision Only **/
67 regUpPoll_b = 0x3d, /** 905B Revision Only **/
68 regUpPriorityThresh_b = 0x3c, /** 905B Revision Only **/
69 regUpListPtr_l = 0x38, /** Universal **/
70 regCountdown_w = 0x36, /** Universal **/
71 regFreeTimer_w = 0x34, /** Universal **/
72 regUpPktStatus_l = 0x30, /** Universal with Exception, pg 130 **/
73 regTxFreeThresh_b = 0x2f, /** 90X Revision Only **/
74 regDnPoll_b = 0x2d, /** 905B Revision Only **/
75 regDnPriorityThresh_b = 0x2c, /** 905B Revision Only **/
76 regDnBurstThresh_b = 0x2a, /** 905B Revision Only **/
77 regDnListPtr_l = 0x24, /** Universal with Exception, pg 107 **/
78 regDmaCtrl_l = 0x20, /** Universal with Exception, pg 106 **/
79 /** **/
80 regIntStatusAuto_w = 0x1e, /** 905B Revision Only **/
81 regTxStatus_b = 0x1b, /** Universal with Exception, pg 113 **/
82 regTimer_b = 0x1a, /** Universal **/
83 regTxPktId_b = 0x18, /** 905B Revision Only **/
84 regCommandIntStatus_w = 0x0e, /** Universal (Command Variations) **/
85 };
86
87/** following are windowed registers **/
88enum Registers7
89 {
90 regPowerMgmtEvent_7_w = 0x0c, /** 905B Revision Only **/
91 regVlanEtherType_7_w = 0x04, /** 905B Revision Only **/
92 regVlanMask_7_w = 0x00, /** 905B Revision Only **/
93 };
94
95enum Registers6
96 {
97 regBytesXmittedOk_6_w = 0x0c, /** Universal **/
98 regBytesRcvdOk_6_w = 0x0a, /** Universal **/
99 regUpperFramesOk_6_b = 0x09, /** Universal **/
100 regFramesDeferred_6_b = 0x08, /** Universal **/
101 regFramesRecdOk_6_b = 0x07, /** Universal with Exceptions, pg 142 **/
102 regFramesXmittedOk_6_b = 0x06, /** Universal **/
103 regRxOverruns_6_b = 0x05, /** Universal **/
104 regLateCollisions_6_b = 0x04, /** Universal **/
105 regSingleCollisions_6_b = 0x03, /** Universal **/
106 regMultipleCollisions_6_b = 0x02, /** Universal **/
107 regSqeErrors_6_b = 0x01, /** Universal **/
108 regCarrierLost_6_b = 0x00, /** Universal **/
109 };
110
111enum Registers5
112 {
113 regIndicationEnable_5_w = 0x0c, /** Universal **/
114 regInterruptEnable_5_w = 0x0a, /** Universal **/
115 regTxReclaimThresh_5_b = 0x09, /** 905B Revision Only **/
116 regRxFilter_5_b = 0x08, /** Universal **/
117 regRxEarlyThresh_5_w = 0x06, /** Universal **/
118 regTxStartThresh_5_w = 0x00, /** Universal **/
119 };
120
121enum Registers4
122 {
123 regUpperBytesOk_4_b = 0x0d, /** Universal **/
124 regBadSSD_4_b = 0x0c, /** Universal **/
125 regMediaStatus_4_w = 0x0a, /** Universal with Exceptions, pg 201 **/
126 regPhysicalMgmt_4_w = 0x08, /** Universal **/
127 regNetworkDiagnostic_4_w = 0x06, /** Universal with Exceptions, pg 203 **/
128 regFifoDiagnostic_4_w = 0x04, /** Universal with Exceptions, pg 196 **/
129 regVcoDiagnostic_4_w = 0x02, /** Undocumented? **/
130 };
131
132enum Registers3
133 {
134 regTxFree_3_w = 0x0c, /** Universal **/
135 regRxFree_3_w = 0x0a, /** Universal with Exceptions, pg 125 **/
136 regResetMediaOptions_3_w = 0x08, /** Media Options on B Revision, **/
137 /** Reset Options on Non-B Revision **/
138 regMacControl_3_w = 0x06, /** Universal with Exceptions, pg 199 **/
139 regMaxPktSize_3_w = 0x04, /** 905B Revision Only **/
140 regInternalConfig_3_l = 0x00, /** Universal, different bit **/
141 /** definitions, pg 59 **/
142 };
143
144enum Registers2
145 {
146 regResetOptions_2_w = 0x0c, /** 905B Revision Only **/
147 regStationMask_2_3w = 0x06, /** Universal with Exceptions, pg 127 **/
148 regStationAddress_2_3w = 0x00, /** Universal with Exceptions, pg 127 **/
149 };
150
151enum Registers1
152 {
153 regRxStatus_1_w = 0x0a, /** 90X Revision Only, Pg 126 **/
154 };
155
156enum Registers0
157 {
158 regEepromData_0_w = 0x0c, /** Universal **/
159 regEepromCommand_0_w = 0x0a, /** Universal **/
160 regBiosRomData_0_b = 0x08, /** 905B Revision Only **/
161 regBiosRomAddr_0_l = 0x04, /** 905B Revision Only **/
162 };
163
164
165/*** The names for the eight register windows ***/
166enum Windows
167 {
168 winPowerVlan7 = 0x07,
169 winStatistics6 = 0x06,
170 winTxRxControl5 = 0x05,
171 winDiagnostics4 = 0x04,
172 winTxRxOptions3 = 0x03,
173 winAddressing2 = 0x02,
174 winUnused1 = 0x01,
175 winEepromBios0 = 0x00,
176 };
177
178
179/*** Command definitions for the 3c90X ***/
180enum Commands
181 {
182 cmdGlobalReset = 0x00, /** Universal with Exceptions, pg 151 **/
183 cmdSelectRegisterWindow = 0x01, /** Universal **/
184 cmdEnableDcConverter = 0x02, /** **/
185 cmdRxDisable = 0x03, /** **/
186 cmdRxEnable = 0x04, /** Universal **/
187 cmdRxReset = 0x05, /** Universal **/
188 cmdStallCtl = 0x06, /** Universal **/
189 cmdTxEnable = 0x09, /** Universal **/
190 cmdTxDisable = 0x0A, /** **/
191 cmdTxReset = 0x0B, /** Universal **/
192 cmdRequestInterrupt = 0x0C, /** **/
193 cmdAcknowledgeInterrupt = 0x0D, /** Universal **/
194 cmdSetInterruptEnable = 0x0E, /** Universal **/
195 cmdSetIndicationEnable = 0x0F, /** Universal **/
196 cmdSetRxFilter = 0x10, /** Universal **/
197 cmdSetRxEarlyThresh = 0x11, /** **/
198 cmdSetTxStartThresh = 0x13, /** **/
199 cmdStatisticsEnable = 0x15, /** **/
200 cmdStatisticsDisable = 0x16, /** **/
201 cmdDisableDcConverter = 0x17, /** **/
202 cmdSetTxReclaimThresh = 0x18, /** **/
203 cmdSetHashFilterBit = 0x19, /** **/
204 };
205
206
207/*** Values for int status register bitmask **/
208#define INT_INTERRUPTLATCH (1<<0)
209#define INT_HOSTERROR (1<<1)
210#define INT_TXCOMPLETE (1<<2)
211#define INT_RXCOMPLETE (1<<4)
212#define INT_RXEARLY (1<<5)
213#define INT_INTREQUESTED (1<<6)
214#define INT_UPDATESTATS (1<<7)
215#define INT_LINKEVENT (1<<8)
216#define INT_DNCOMPLETE (1<<9)
217#define INT_UPCOMPLETE (1<<10)
218#define INT_CMDINPROGRESS (1<<12)
219#define INT_WINDOWNUMBER (7<<13)
220
221
222/*** TX descriptor ***/
223typedef struct
224 {
225 unsigned int DnNextPtr;
226 unsigned int FrameStartHeader;
748534f4
JP		 227 unsigned int DataAddr;
228 unsigned int DataLength;
229 }
230 TXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
231
232/*** RX descriptor ***/
233typedef struct
234 {
235 unsigned int UpNextPtr;
236 unsigned int UpPktStatus;
237 unsigned int DataAddr;
238 unsigned int DataLength;
239 }
240 RXD __attribute__ ((aligned(8))); /* 64-bit aligned for bus mastering */
241
242/*** Global variables ***/
243static struct
244 {
245 unsigned int is3c556;
246 unsigned char isBrev;
247 unsigned char CurrentWindow;
248 unsigned int IOAddr;
249 unsigned char HWAddr[ETH_ALEN];
250 TXD TransmitDPD;
251 RXD ReceiveUPD;
252 }
253 INF_3C90X;
7a914840 254static struct nic nic;
748534f4 255
c2e34447
JW		 256#define _outl(v,a) outl((a),(v))
257#define _outw(v,a) outw((a),(v))
258#define _outb(v,a) outb((a),(v))
748534f4 259
31ddf9b3
JW		 260static int _issue_command(int ioaddr, int cmd, int param)
261{
262 outw(ioaddr + regCommandIntStatus_w, (cmd << 11) | param);
748534f4 263
31ddf9b3
JW		 264 while (inw(ioaddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
265 ;
748534f4 266
31ddf9b3
JW		 267 return 0;
268}
748534f4
JP		 269
270
271/*** a3c90x_internal_SetWindow: selects a register window set.
272 ***/
31ddf9b3
JW		 273static int _set_window(int ioaddr, int window)
274{
275 if (INF_3C90X.CurrentWindow == window)
276 return 0;
748534f4 277
31ddf9b3 278 _issue_command(ioaddr, cmdSelectRegisterWindow, window);
748534f4
JP		 279 INF_3C90X.CurrentWindow = window;
280
31ddf9b3
JW		 281 return 0;
282}
748534f4
JP		 283
284
285/*** a3c90x_internal_ReadEeprom - read data from the serial eeprom.
286 ***/
287static unsigned short
288a3c90x_internal_ReadEeprom(int ioaddr, int address)
c2e34447
JW		 289{
290 unsigned short val;
748534f4
JP		 291
292 /** Select correct window **/
31ddf9b3 293 _set_window(INF_3C90X.IOAddr, winEepromBios0);
748534f4
JP		 294
295 /** Make sure the eeprom isn't busy **/
c2e34447
JW		 296 do
297 {
298 int i;
299 for (i = 0; i < 165; i++)
300 inb(0x80); /* wait 165 usec */
301 }
302 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
748534f4
JP		 303
304 /** Read the value. **/
305 if (INF_3C90X.is3c556)
c2e34447 306 _outw(address + (0x230), ioaddr + regEepromCommand_0_w);
748534f4 307 else
c2e34447 308 _outw(address + 0x80, ioaddr + regEepromCommand_0_w);
748534f4 309
c2e34447
JW		 310 do
311 {
312 int i;
313 for (i = 0; i < 165; i++)
314 inb(0x80); /* wait 165 usec */
315 }
316 while(0x8000 & inw(ioaddr + regEepromCommand_0_w));
317 val = inw(ioaddr + regEepromData_0_w);
318
319 return val;
320}
748534f4
JP		 321
322
323#ifdef CFG_3C90X_BOOTROM_FIX
324/*** a3c90x_internal_WriteEepromWord - write a physical word of
325 *** data to the onboard serial eeprom (not the BIOS prom, but the
326 *** nvram in the card that stores, among other things, the MAC
327 *** address).
328 ***/
329static int
330a3c90x_internal_WriteEepromWord(int ioaddr, int address, unsigned short value)
331 {
332 /** Select register window **/
31ddf9b3 333 _set_window(ioaddr, winEepromBios0);
748534f4
JP		 334
335 /** Verify Eeprom not busy **/
336 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
337
338 /** Issue WriteEnable, and wait for completion. **/
c2e34447 339 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 340 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
341
342 /** Issue EraseRegister, and wait for completion. **/
c2e34447 343 _outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 344 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
345
346 /** Send the new data to the eeprom, and wait for completion. **/
c2e34447
JW		 347 _outw(value, ioaddr + regEepromData_0_w);
348 _outw(0x30, ioaddr + regEepromCommand_0_w);
748534f4
JP		 349 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
350
351 /** Burn the new data into the eeprom, and wait for completion. **/
c2e34447 352 _outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
748534f4
JP		 353 while((1<<15) & inw(ioaddr + regEepromCommand_0_w));
354
355 return 0;
356 }
357#endif
358
359#ifdef CFG_3C90X_BOOTROM_FIX
360/*** a3c90x_internal_WriteEeprom - write data to the serial eeprom,
361 *** and re-compute the eeprom checksum.
362 ***/
363static int
364a3c90x_internal_WriteEeprom(int ioaddr, int address, unsigned short value)
365 {
366 int cksum = 0,v;
367 int i;
368 int maxAddress, cksumAddress;
369
370 if (INF_3C90X.isBrev)
371 {
372 maxAddress=0x1f;
373 cksumAddress=0x20;
374 }
375 else
376 {
377 maxAddress=0x16;
378 cksumAddress=0x17;
379 }
380
381 /** Write the value. **/
382 if (a3c90x_internal_WriteEepromWord(ioaddr, address, value) == -1)
383 return -1;
384
385 /** Recompute the checksum. **/
386 for(i=0;i<=maxAddress;i++)
387 {
388 v = a3c90x_internal_ReadEeprom(ioaddr, i);
389 cksum ^= (v & 0xFF);
390 cksum ^= ((v>>8) & 0xFF);
391 }
392 /** Write the checksum to the location in the eeprom **/
393 if (a3c90x_internal_WriteEepromWord(ioaddr, cksumAddress, cksum) == -1)
394 return -1;
395
396 return 0;
397 }
398#endif
399
400/*** a3c90x_reset: exported function that resets the card to its default
401 *** state. This is so the Linux driver can re-set the card up the way
402 *** it wants to. If CFG_3C90X_PRESERVE_XCVR is defined, then the reset will
403 *** not alter the selected transceiver that we used to download the boot
404 *** image.
405 ***/
406static void a3c90x_reset(void)
407 {
408#ifdef CFG_3C90X_PRESERVE_XCVR
409 int cfg;
410 /** Read the current InternalConfig value. **/
31ddf9b3 411 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 412 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
413#endif
414
415 /** Send the reset command to the card **/
99182958 416 outputf("3c90x: issuing RESET");
31ddf9b3 417 _issue_command(INF_3C90X.IOAddr, cmdGlobalReset, 0);
748534f4
JP		 418
419 /** global reset command resets station mask, non-B revision cards
420 ** require explicit reset of values
421 **/
31ddf9b3 422 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 423 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
424 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
425 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 426
427#ifdef CFG_3C90X_PRESERVE_XCVR
428 /** Re-set the original InternalConfig value from before reset **/
31ddf9b3 429 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
c2e34447 430 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 431
432 /** enable DC converter for 10-Base-T **/
433 if ((cfg&0x0300) == 0x0300)
434 {
31ddf9b3 435 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 436 }
437#endif
438
439 /** Issue transmit reset, wait for command completion **/
31ddf9b3 440 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 441 if (! INF_3C90X.isBrev)
c2e34447 442 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
31ddf9b3 443 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 444
445 /**
446 ** reset of the receiver on B-revision cards re-negotiates the link
447 ** takes several seconds (a computer eternity)
448 **/
449 if (INF_3C90X.isBrev)
31ddf9b3 450 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 451 else
31ddf9b3
JW		 452 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
453 while (inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_CMDINPROGRESS)
454 ;
455 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4 456
31ddf9b3 457 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
748534f4 458 /** enable rxComplete and txComplete **/
31ddf9b3 459 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
748534f4 460 /** acknowledge any pending status flags **/
31ddf9b3 461 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 462
463 return;
464 }
465
466
467
468/*** a3c90x_transmit: exported function that transmits a packet. Does not
469 *** return any particular status. Parameters are:
470 *** dest_addr[6] - destination address, ethernet;
471 *** proto - protocol type (ARP, IP, etc);
472 *** size - size of the non-header part of the packet that needs transmitted;
473 *** pkt - the pointer to the packet data itself.
474 ***/
475static void
47c41031 476a3c90x_transmit(unsigned int size, const char *pkt)
31ddf9b3 477{
31ddf9b3 478 unsigned char status;
3dd054cf
JW		 479 static unsigned int stillwaiting = 0;
480
481 if (stillwaiting)
482 {
483 while (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE) && oneshot_running())
484 ;
485 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w) & INT_TXCOMPLETE))
486 {
487 outputf("3c90x: tx timeout? txstat %02x", inb(INF_3C90X.IOAddr + regTxStatus_b));
488 outputf("3c90x: Gen sts %04x", inw(INF_3C90X.IOAddr + regCommandIntStatus_w));
489 }
490 status = inb(INF_3C90X.IOAddr + regTxStatus_b);
491 outb(INF_3C90X.IOAddr + regTxStatus_b, 0x00);
492 stillwaiting = 0;
493 }
748534f4 494
037ce545
JW		 495 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 2 /* Stall download */);
496
497 /** Setup the DPD (download descriptor) **/
498 INF_3C90X.TransmitDPD.DnNextPtr = 0;
499 /** set notification for transmission completion (bit 15) **/
500 INF_3C90X.TransmitDPD.FrameStartHeader = (size) | 0x8000;
501 INF_3C90X.TransmitDPD.DataAddr = v2p((void*)pkt);
502 INF_3C90X.TransmitDPD.DataLength = size + (1<<31);
503
504 /** Send the packet **/
505 outl(INF_3C90X.IOAddr + regDnListPtr_l, v2p(&(INF_3C90X.TransmitDPD)));
506 _issue_command(INF_3C90X.IOAddr, cmdStallCtl, 3 /* Unstall download */);
31ddf9b3 507
037ce545
JW		 508 oneshot_start_ms(10);
509 while((inl(INF_3C90X.IOAddr + regDnListPtr_l) != 0) && oneshot_running())
510 ;
511 if (!oneshot_running())
512 {
513 outputf("3c90x: Download engine pointer timeout");
514 return;
515 }
3dd054cf 516
037ce545
JW		 517 oneshot_start_ms(10);
518 stillwaiting = 1;
31ddf9b3 519
3dd054cf 520#if 0
037ce545
JW		 521 /** successful completion (sans "interrupt Requested" bit) **/
522 if ((status & 0xbf) == 0x80)
523 return;
31ddf9b3 524
037ce545
JW		 525 outputf("3c90x: Status (%hhX)", status);
526 /** check error codes **/
527 if (status & 0x02)
528 {
529 outputf("3c90x: Tx Reclaim Error (%hhX)", status);
530 a3c90x_reset();
531 } else if (status & 0x04) {
532 outputf("3c90x: Tx Status Overflow (%hhX)", status);
533 for (i=0; i<32; i++)
534 _outb(0x00, INF_3C90X.IOAddr + regTxStatus_b);
535 /** must re-enable after max collisions before re-issuing tx **/
536 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
537 } else if (status & 0x08) {
538 outputf("3c90x: Tx Max Collisions (%hhX)", status);
539 /** must re-enable after max collisions before re-issuing tx **/
540 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
541 } else if (status & 0x10) {
542 outputf("3c90x: Tx Underrun (%hhX)", status);
543 a3c90x_reset();
544 } else if (status & 0x20) {
545 outputf("3c90x: Tx Jabber (%hhX)", status);
546 a3c90x_reset();
547 } else if ((status & 0x80) != 0x80) {
548 outputf("3c90x: Internal Error - Incomplete Transmission (%hhX)", status);
549 a3c90x_reset();
748534f4 550 }
037ce545 551#endif
31ddf9b3 552}
748534f4
JP		 553
554
555
556/*** a3c90x_poll: exported routine that waits for a certain length of time
557 *** for a packet, and if it sees none, returns 0. This routine should
558 *** copy the packet to nic->packet if it gets a packet and set the size
559 *** in nic->packetlen. Return 1 if a packet was found.
560 ***/
561static int
562a3c90x_poll(struct nic *nic, int retrieve)
563 {
564 int i, errcode;
565
566 if (!(inw(INF_3C90X.IOAddr + regCommandIntStatus_w)&0x0010))
567 {
568 return 0;
569 }
570
571 if ( ! retrieve ) return 1;
572
573 /** we don't need to acknowledge rxComplete -- the upload engine
574 ** does it for us.
575 **/
576
577 /** Build the up-load descriptor **/
578 INF_3C90X.ReceiveUPD.UpNextPtr = 0;
579 INF_3C90X.ReceiveUPD.UpPktStatus = 0;
923ea2c2 580 INF_3C90X.ReceiveUPD.DataAddr = v2p(nic->packet);
748534f4
JP		 581 INF_3C90X.ReceiveUPD.DataLength = 1536 + (1<<31);
582
583 /** Submit the upload descriptor to the NIC **/
923ea2c2 584 _outl(v2p(&(INF_3C90X.ReceiveUPD)),
748534f4
JP		 585 INF_3C90X.IOAddr + regUpListPtr_l);
586
587 /** Wait for upload completion (upComplete(15) or upError (14)) **/
588 for(i=0;i<40000;i++);
589 while((INF_3C90X.ReceiveUPD.UpPktStatus & ((1<<14) | (1<<15))) == 0)
590 for(i=0;i<40000;i++);
591
592 /** Check for Error (else we have good packet) **/
593 if (INF_3C90X.ReceiveUPD.UpPktStatus & (1<<14))
594 {
595 errcode = INF_3C90X.ReceiveUPD.UpPktStatus;
596 if (errcode & (1<<16))
597 outputf("3C90X: Rx Overrun (%hX)",errcode>>16);
598 else if (errcode & (1<<17))
599 outputf("3C90X: Runt Frame (%hX)",errcode>>16);
600 else if (errcode & (1<<18))
601 outputf("3C90X: Alignment Error (%hX)",errcode>>16);
602 else if (errcode & (1<<19))
603 outputf("3C90X: CRC Error (%hX)",errcode>>16);
604 else if (errcode & (1<<20))
605 outputf("3C90X: Oversized Frame (%hX)",errcode>>16);
606 else
607 outputf("3C90X: Packet error (%hX)",errcode>>16);
608 return 0;
609 }
610
611 /** Ok, got packet. Set length in nic->packetlen. **/
612 nic->packetlen = (INF_3C90X.ReceiveUPD.UpPktStatus & 0x1FFF);
613
614 return 1;
615 }
616
617
618
619/*** a3c90x_disable: exported routine to disable the card. What's this for?
620 *** the eepro100.c driver didn't have one, so I just left this one empty too.
621 *** Ideas anyone?
622 *** Must turn off receiver at least so stray packets will not corrupt memory
623 *** [Ken]
624 ***/
625void a3c90x_disable(struct dev *dev)
626{
627 /* reset and disable merge */
628 a3c90x_reset();
629 /* Disable the receiver and transmitter. */
c2e34447
JW		 630 _outw(cmdRxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
631 _outw(cmdTxDisable, INF_3C90X.IOAddr + regCommandIntStatus_w);
748534f4
JP		 632}
633
634
635/*** a3c90x_probe: exported routine to probe for the 3c905 card and perform
636 *** initialization. If this routine is called, the pci functions did find the
637 *** card. We just have to init it here.
638 ***/
639static int a3c90x_probe(struct pci_dev * pci, void * data)
640{
748534f4
JP		 641 INF_3C90X.is3c556 = (pci->did == 0x6055);
642
643 int i, c;
c2e34447 644 unsigned short eeprom[0x100];
748534f4
JP		 645 unsigned int cfg;
646 unsigned int mopt;
647 unsigned int mstat;
648 unsigned short linktype;
649#define HWADDR_OFFSET 10
650
651 unsigned long ioaddr = 0;
652 for (i = 0; i < 6; i++) {
653 if (pci->bars[i].type == PCI_BAR_IO) {
654 ioaddr = pci->bars[i].addr;
655 break;
656 }
657 }
658
659 if (ioaddr == 0)
c2e34447
JW		 660 {
661 outputf("3c90x: Unable to find I/O address");
662 return 0;
663 }
664
665 /* Power it on */
666 pci_write16(pci->bus, pci->dev, pci->fn, 0xE0,
667 pci_read16(pci->bus, pci->dev, pci->fn, 0xE0) & ~0x3);
668
669 outputf("3c90x: Picked I/O address %04x", ioaddr);
047916ed 670 pci_bother_add(pci);
42125f27
JP		 671 nic.ioaddr = ioaddr & ~3;
672 nic.irqno = 0;
748534f4 673
c2e34447 674 INF_3C90X.IOAddr = ioaddr;
748534f4
JP		 675 INF_3C90X.CurrentWindow = 255;
676 switch (a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, 0x03))
677 {
678 case 0x9000: /** 10 Base TPO **/
679 case 0x9001: /** 10/100 T4 **/
680 case 0x9050: /** 10/100 TPO **/
681 case 0x9051: /** 10 Base Combo **/
682 INF_3C90X.isBrev = 0;
683 break;
684
685 case 0x9004: /** 10 Base TPO **/
686 case 0x9005: /** 10 Base Combo **/
687 case 0x9006: /** 10 Base TPO and Base2 **/
688 case 0x900A: /** 10 Base FL **/
689 case 0x9055: /** 10/100 TPO **/
690 case 0x9056: /** 10/100 T4 **/
691 case 0x905A: /** 10 Base FX **/
692 default:
693 INF_3C90X.isBrev = 1;
694 break;
695 }
696
697 /** Load the EEPROM contents **/
698 if (INF_3C90X.isBrev)
699 {
c2e34447 700 for(i=0;i<=/*0x20*/0x7F;i++)
748534f4
JP		 701 {
702 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
703 }
704
705#ifdef CFG_3C90X_BOOTROM_FIX
706 /** Set xcvrSelect in InternalConfig in eeprom. **/
707 /* only necessary for 3c905b revision cards with boot PROM bug!!! */
708 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x13, 0x0160);
709#endif
710
711#ifdef CFG_3C90X_XCVR
712 if (CFG_3C90X_XCVR == 255)
713 {
714 /** Clear the LanWorks register **/
715 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16, 0);
716 }
717 else
718 {
719 /** Set the selected permanent-xcvrSelect in the
720 ** LanWorks register
721 **/
722 a3c90x_internal_WriteEeprom(INF_3C90X.IOAddr, 0x16,
723 XCVR_MAGIC + ((CFG_3C90X_XCVR) & 0x000F));
724 }
725#endif
726 }
727 else
728 {
c2e34447 729 for(i=0;i<=/*0x17*/0x7F;i++)
748534f4
JP		 730 {
731 eeprom[i] = a3c90x_internal_ReadEeprom(INF_3C90X.IOAddr, i);
732 }
733 }
734
735 /** Print identification message **/
736#ifdef CFG_3C90X_BOOTROM_FIX
737 if (INF_3C90X.isBrev)
738 {
739 outputf("NOTE: 3c905b bootrom fix enabled; has side "
740 "effects. See 3c90x.txt for info.");
741 }
742#endif
743
744 /** Retrieve the Hardware address and print it on the screen. **/
745 INF_3C90X.HWAddr[0] = eeprom[HWADDR_OFFSET + 0]>>8;
746 INF_3C90X.HWAddr[1] = eeprom[HWADDR_OFFSET + 0]&0xFF;
747 INF_3C90X.HWAddr[2] = eeprom[HWADDR_OFFSET + 1]>>8;
748 INF_3C90X.HWAddr[3] = eeprom[HWADDR_OFFSET + 1]&0xFF;
749 INF_3C90X.HWAddr[4] = eeprom[HWADDR_OFFSET + 2]>>8;
750 INF_3C90X.HWAddr[5] = eeprom[HWADDR_OFFSET + 2]&0xFF;
c2e34447
JW		 751 outputf("MAC Address = %02x:%02x:%02x:%02x:%02x:%02x",
752 INF_3C90X.HWAddr[0],
753 INF_3C90X.HWAddr[1],
754 INF_3C90X.HWAddr[2],
755 INF_3C90X.HWAddr[3],
756 INF_3C90X.HWAddr[4],
757 INF_3C90X.HWAddr[5]);
748534f4
JP		 758
759 /** 3C556: Invert MII power **/
760 if (INF_3C90X.is3c556) {
761 unsigned int tmp;
31ddf9b3 762 _set_window(INF_3C90X.IOAddr, winAddressing2);
748534f4
JP		 763 tmp = inw(INF_3C90X.IOAddr + regResetOptions_2_w);
764 tmp |= 0x4000;
c2e34447 765 _outw(tmp, INF_3C90X.IOAddr + regResetOptions_2_w);
748534f4
JP		 766 }
767
768 /* Test if the link is good, if not continue */
31ddf9b3 769 _set_window(INF_3C90X.IOAddr, winDiagnostics4);
748534f4
JP		 770 mstat = inw(INF_3C90X.IOAddr + regMediaStatus_4_w);
771 if((mstat & (1<<11)) == 0) {
772 outputf("Valid link not established");
773 return 0;
774 }
775
776 /** Program the MAC address into the station address registers **/
31ddf9b3 777 _set_window(INF_3C90X.IOAddr, winAddressing2);
c2e34447
JW		 778 _outw(htons(eeprom[HWADDR_OFFSET + 0]), INF_3C90X.IOAddr + regStationAddress_2_3w);
779 _outw(htons(eeprom[HWADDR_OFFSET + 1]), INF_3C90X.IOAddr + regStationAddress_2_3w+2);
780 _outw(htons(eeprom[HWADDR_OFFSET + 2]), INF_3C90X.IOAddr + regStationAddress_2_3w+4);
781 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
782 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
783 _outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+4);
748534f4
JP		 784
785 /** Fill in our entry in the etherboot arp table **/
786/* XXX ? for lwip?
787 for(i=0;i<ETH_ALEN;i++)
42125f27 788 nic.node_addr[i] = (eeprom[HWADDR_OFFSET + i/2] >> (8*((i&1)^1))) & 0xff;
748534f4
JP		 789*/
790
791 /** Read the media options register, print a message and set default
792 ** xcvr.
793 **
794 ** Uses Media Option command on B revision, Reset Option on non-B
795 ** revision cards -- same register address
796 **/
31ddf9b3 797 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 798 mopt = inw(INF_3C90X.IOAddr + regResetMediaOptions_3_w);
799
800 /** mask out VCO bit that is defined as 10baseFL bit on B-rev cards **/
801 if (! INF_3C90X.isBrev)
802 {
803 mopt &= 0x7F;
804 }
805
806 outputf("Connectors present: ");
807 c = 0;
808 linktype = 0x0008;
809 if (mopt & 0x01)
810 {
811 outputf("%s100Base-T4",(c++)?", ":"");
812 linktype = 0x0006;
813 }
814 if (mopt & 0x04)
815 {
816 outputf("%s100Base-FX",(c++)?", ":"");
817 linktype = 0x0005;
818 }
819 if (mopt & 0x10)
820 {
821 outputf("%s10Base-2",(c++)?", ":"");
822 linktype = 0x0003;
823 }
824 if (mopt & 0x20)
825 {
826 outputf("%sAUI",(c++)?", ":"");
827 linktype = 0x0001;
828 }
829 if (mopt & 0x40)
830 {
831 outputf("%sMII",(c++)?", ":"");
832 linktype = 0x0006;
833 }
834 if ((mopt & 0xA) == 0xA)
835 {
836 outputf("%s10Base-T / 100Base-TX",(c++)?", ":"");
837 linktype = 0x0008;
838 }
839 else if ((mopt & 0xA) == 0x2)
840 {
841 outputf("%s100Base-TX",(c++)?", ":"");
842 linktype = 0x0008;
843 }
844 else if ((mopt & 0xA) == 0x8)
845 {
846 outputf("%s10Base-T",(c++)?", ":"");
847 linktype = 0x0008;
848 }
849 outputf(".");
850
851 /** Determine transceiver type to use, depending on value stored in
852 ** eeprom 0x16
853 **/
854 if (INF_3C90X.isBrev)
855 {
856 if ((eeprom[0x16] & 0xFF00) == XCVR_MAGIC)
857 {
858 /** User-defined **/
859 linktype = eeprom[0x16] & 0x000F;
860 }
861 }
862 else
863 {
864#ifdef CFG_3C90X_XCVR
865 if (CFG_3C90X_XCVR != 255)
866 linktype = CFG_3C90X_XCVR;
867#endif /* CFG_3C90X_XCVR */
868
869 /** I don't know what MII MAC only mode is!!! **/
870 if (linktype == 0x0009)
871 {
872 if (INF_3C90X.isBrev)
873 outputf("WARNING: MII External MAC Mode only supported on B-revision "
874 "cards!!!!\nFalling Back to MII Mode\n");
875 linktype = 0x0006;
876 }
877 }
878
879 /** enable DC converter for 10-Base-T **/
880 if (linktype == 0x0003)
881 {
31ddf9b3 882 _issue_command(INF_3C90X.IOAddr, cmdEnableDcConverter, 0);
748534f4
JP		 883 }
884
885 /** Set the link to the type we just determined. **/
31ddf9b3 886 _set_window(INF_3C90X.IOAddr, winTxRxOptions3);
748534f4
JP		 887 cfg = inl(INF_3C90X.IOAddr + regInternalConfig_3_l);
888 cfg &= ~(0xF<<20);
889 cfg |= (linktype<<20);
c2e34447 890 _outl(cfg, INF_3C90X.IOAddr + regInternalConfig_3_l);
748534f4
JP		 891
892 /** Now that we set the xcvr type, reset the Tx and Rx, re-enable. **/
31ddf9b3 893 _issue_command(INF_3C90X.IOAddr, cmdTxReset, 0);
748534f4 894 if (!INF_3C90X.isBrev)
c2e34447 895 _outb(0x01, INF_3C90X.IOAddr + regTxFreeThresh_b);
748534f4 896
31ddf9b3 897 _issue_command(INF_3C90X.IOAddr, cmdTxEnable, 0);
748534f4
JP		 898
899 /**
900 ** reset of the receiver on B-revision cards re-negotiates the link
901 ** takes several seconds (a computer eternity)
902 **/
903 if (INF_3C90X.isBrev)
31ddf9b3 904 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x04);
748534f4 905 else
31ddf9b3 906 _issue_command(INF_3C90X.IOAddr, cmdRxReset, 0x00);
748534f4
JP		 907
908 /** Set the RX filter = receive only individual pkts & multicast & bcast. **/
31ddf9b3
JW		 909 _issue_command(INF_3C90X.IOAddr, cmdSetRxFilter, 0x01 + 0x02 + 0x04);
910 _issue_command(INF_3C90X.IOAddr, cmdRxEnable, 0);
748534f4
JP		 911
912
913 /**
914 ** set Indication and Interrupt flags , acknowledge any IRQ's
915 **/
31ddf9b3
JW		 916 _issue_command(INF_3C90X.IOAddr, cmdSetInterruptEnable, 0);
917 _issue_command(INF_3C90X.IOAddr, cmdSetIndicationEnable, 0x0014);
918 _issue_command(INF_3C90X.IOAddr, cmdAcknowledgeInterrupt, 0x661);
748534f4
JP		 919
920 /* * Set our exported functions **/
42125f27
JP		 921 nic.poll = a3c90x_poll;
922 nic.transmit = a3c90x_transmit;
47c41031 923 memcpy(nic.hwaddr, INF_3C90X.HWAddr, 6);
c2e34447 924 eth_register(&nic);
748534f4
JP		 925
926 return 1;
927}
928
929static struct pci_id a3c90x_nics[] = {
930/* Original 90x revisions: */
931PCI_ROM(0x10b7, 0x6055, "3c556", "3C556"), /* Huricane */
932PCI_ROM(0x10b7, 0x9000, "3c905-tpo", "3Com900-TPO"), /* 10 Base TPO */
933PCI_ROM(0x10b7, 0x9001, "3c905-t4", "3Com900-Combo"), /* 10/100 T4 */
934PCI_ROM(0x10b7, 0x9050, "3c905-tpo100", "3Com905-TX"), /* 100 Base TX / 10/100 TPO */
935PCI_ROM(0x10b7, 0x9051, "3c905-combo", "3Com905-T4"), /* 100 Base T4 / 10 Base Combo */
936/* Newer 90xB revisions: */
937PCI_ROM(0x10b7, 0x9004, "3c905b-tpo", "3Com900B-TPO"), /* 10 Base TPO */
938PCI_ROM(0x10b7, 0x9005, "3c905b-combo", "3Com900B-Combo"), /* 10 Base Combo */
939PCI_ROM(0x10b7, 0x9006, "3c905b-tpb2", "3Com900B-2/T"), /* 10 Base TP and Base2 */
940PCI_ROM(0x10b7, 0x900a, "3c905b-fl", "3Com900B-FL"), /* 10 Base FL */
941PCI_ROM(0x10b7, 0x9055, "3c905b-tpo100", "3Com905B-TX"), /* 10/100 TPO */
942PCI_ROM(0x10b7, 0x9056, "3c905b-t4", "3Com905B-T4"), /* 10/100 T4 */
943PCI_ROM(0x10b7, 0x9058, "3c905b-9058", "3Com905B-9058"), /* Cyclone 10/100/BNC */
944PCI_ROM(0x10b7, 0x905a, "3c905b-fx", "3Com905B-FL"), /* 100 Base FX / 10 Base FX */
945/* Newer 90xC revision: */
946PCI_ROM(0x10b7, 0x9200, "3c905c-tpo", "3Com905C-TXM"), /* 10/100 TPO (3C905C-TXM) */
947PCI_ROM(0x10b7, 0x9202, "3c920b-emb-ati", "3c920B-EMB-WNM (ATI Radeon 9100 IGP)"), /* 3c920B-EMB-WNM (ATI Radeon 9100 IGP) */
948PCI_ROM(0x10b7, 0x9210, "3c920b-emb-wnm","3Com20B-EMB WNM"),
949PCI_ROM(0x10b7, 0x9800, "3c980", "3Com980-Cyclone"), /* Cyclone */
950PCI_ROM(0x10b7, 0x9805, "3c9805", "3Com9805"), /* Dual Port Server Cyclone */
951PCI_ROM(0x10b7, 0x7646, "3csoho100-tx", "3CSOHO100-TX"), /* Hurricane */
952PCI_ROM(0x10b7, 0x4500, "3c450", "3Com450 HomePNA Tornado"),
953PCI_ROM(0x10b7, 0x1201, "3c982a", "3Com982A"),
954PCI_ROM(0x10b7, 0x1202, "3c982b", "3Com982B"),
955};
956
957struct pci_driver a3c90x_driver = {
958 .name = "3C90X",
959 .probe = a3c90x_probe,
960 .ids = a3c90x_nics,
961 .id_count = sizeof(a3c90x_nics)/sizeof(a3c90x_nics[0]),
962};
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