It works, but why?

diff --git a/FPGABoy.ise b/FPGABoy.ise
index e4050d100b69264e355502b03b45426fea86725d..c324dd08d4b24700eae5182eb7ecb7bfb381e8e1 100644 (file)
Binary files a/FPGABoy.ise and b/FPGABoy.ise differ

diff --git a/Makefile b/Makefile
index 41aff51aa32f9553b22e26e390b90bc260fddb60..26e2289e0ed89d5d72257cf5b9ec3c29994e26d8 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -27,6 +27,18 @@ CoreTop.twr: CoreTop_map.ncd
 CoreTop.bit: CoreTop.ut CoreTop.ncd
        bitgen -f CoreTop.ut CoreTop.ncd
 
+netgen/par/CoreTop_timesim.v: CoreTop.twr CoreTop.ncd
+       netgen -ise FPGABoy.ise -s 5  -pcf CoreTop.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim CoreTop.ncd CoreTop_timesim.v
+
+netgen/par/.CoreTop_timesim.v_work: netgen/par/CoreTop_timesim.v
+       vlogcomp netgen/par/CoreTop_timesim.v
+       vlogcomp /home/joshua/projects/fpga/ise/Xilinx101/verilog/src/glbl.v
+       
+CoreTop_isim_par.exe: netgen/par/.CoreTop_timesim.v_work
+       fuse -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o CoreTop_isim_par.exe netgen/par/CoreTop_timesim.v -top CoreTop -top glbl
+
+parsim: CoreTop_isim_par.exe
+
 %.o: %.asm
        rgbasm -o$@ $<
 
@@ -48,3 +60,6 @@ CoreTop_%.bit: %.mem CoreTop.bit foo_bd.bmm
 CoreTop_%.svf: CoreTop_%.bit impact.cmd
        sed -e s/XXX/$(subst .bit,,$<)/ < impact.cmd > tmp.cmd
        impact -batch tmp.cmd
+
+parsim: CoreTop
+       
\ No newline at end of file

diff --git a/System.v b/System.v
index 40817714e138de5885341d98c866d41634db6805..00ee4ecee5d67c006b0adc276aac752eede763ed 100644 (file)
--- a/System.v
+++ b/System.v
@@ -73,7 +73,8 @@ module CoreTop(
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
        
        wire cclk;
-       IBUFG ibuf (.O(cclk), .I(switches[0]));
+//     IBUFG ibuf (.O(cclk), .I(switches[0] & clk));
+       assign cclk = clk;
 
        wire [15:0] addr;       
        wire [7:0] data;
@@ -82,9 +83,9 @@ module CoreTop(
        wire irq, tmrirq;
        wire [7:0] jaddr;
        wire [1:0] state;
-
+       
        GBZ80Core core(
-               .clk(cclk),
+               .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
@@ -107,10 +108,10 @@ module CoreTop(
                .out(seven),
                .freeze(buttons[0]),
                .periods(
-                       (state == 2'b00) ? 4'b1000 :
-                       (state == 2'b01) ? 4'b0100 :
-                       (state == 2'b10) ? 4'b0010 :
-                                          4'b0001) );
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );
         
        Switches sw(
                .address(addr),
@@ -175,7 +176,7 @@ module TestBench();
        wire [7:0] leds;
        wire [7:0] switches;
        
-       always #10 clk <= ~clk;
+       always #62 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),