9 reg [7:0] rom [2047:0];
10 initial $readmemh("rom.hex", rom);
12 wire decode = address[15:13] == 0;
13 wire [7:0] odata = rom[address[11:0]];
14 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
15 //assign data = rd ? odata : 8'bzzzzzzzz;
24 // synthesis attribute ram_style of reg is block
25 reg [7:0] ram [8191:0];
27 wire decode = address[15:13] == 3'b110;
29 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
33 if (decode) // This has to go this way. The only way XST knows how to do
34 begin // block ram is chip select, write enable, and always
35 if (wr) // reading. "else if rd" does not cut it ...
36 ram[address[12:0]] <= data;
37 odata <= ram[address[12:0]];
48 output reg [7:0] ledout = 0);
50 wire decode = address == 16'hFF51;
52 assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
58 else if (decode && wr)
67 output wire [7:0] leds,
69 output wire [3:0] digits,
70 output wire [7:0] seven);
73 CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
76 IBUFG ibuf (.O(cclk), .I(switches[0]));
110 (state == 2'b00) ? 4'b1000 :
111 (state == 2'b01) ? 4'b0100 :
112 (state == 2'b10) ? 4'b0010 :
122 .switches({switches[7:1],1'b0})
125 UART nouart ( /* no u */
178 always #10 clk <= ~clk;